2 ******************************************************************************
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3 * @file stm32l1xx_rcc.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the RCC firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32l1xx_rcc.h"
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24 /** @addtogroup STM32L1xx_StdPeriph_Driver
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29 * @brief RCC driver modules
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33 /** @defgroup RCC_Private_TypesDefinitions
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41 /** @defgroup RCC_Private_Defines
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45 /* ------------ RCC registers bit address in the alias region ----------- */
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46 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
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48 /* --- CR Register ---*/
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50 /* Alias word address of HSION bit */
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51 #define CR_OFFSET (RCC_OFFSET + 0x00)
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52 #define HSION_BitNumber 0x00
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53 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
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55 /* Alias word address of MSION bit */
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56 #define MSION_BitNumber 0x08
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57 #define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
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59 /* Alias word address of PLLON bit */
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60 #define PLLON_BitNumber 0x18
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61 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
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63 /* Alias word address of CSSON bit */
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64 #define CSSON_BitNumber 0x1C
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65 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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67 /* --- CSR Register ---*/
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69 /* Alias word address of LSION bit */
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70 #define CSR_OFFSET (RCC_OFFSET + 0x34)
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71 #define LSION_BitNumber 0x00
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72 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
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74 /* Alias word address of RTCEN bit */
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75 #define RTCEN_BitNumber 0x16
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76 #define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
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78 /* Alias word address of RTCRST bit */
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79 #define RTCRST_BitNumber 0x17
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80 #define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
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83 /* ---------------------- RCC registers mask -------------------------------- */
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85 #define FLAG_MASK ((uint8_t)0x1F)
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87 /* CR register byte 3 (Bits[23:16]) base address */
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88 #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
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90 /* ICSCR register byte 4 (Bits[31:24]) base address */
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91 #define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)
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93 /* CFGR register byte 3 (Bits[23:16]) base address */
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94 #define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)
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96 /* CFGR register byte 4 (Bits[31:24]) base address */
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97 #define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)
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99 /* CIR register byte 2 (Bits[15:8]) base address */
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100 #define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)
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102 /* CIR register byte 3 (Bits[23:16]) base address */
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103 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)
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105 /* CSR register byte 2 (Bits[15:8]) base address */
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106 #define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)
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112 /** @defgroup RCC_Private_Macros
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120 /** @defgroup RCC_Private_Variables
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124 static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
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125 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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126 static __I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};
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132 /** @defgroup RCC_Private_FunctionPrototypes
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140 /** @defgroup RCC_Private_Functions
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145 * @brief Resets the RCC clock configuration to the default reset state.
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149 void RCC_DeInit(void)
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152 /* Set MSION bit */
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153 RCC->CR |= (uint32_t)0x00000100;
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155 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
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156 RCC->CFGR &= (uint32_t)0x88FFC00C;
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158 /* Reset HSION, HSEON, CSSON and PLLON bits */
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159 RCC->CR &= (uint32_t)0xEEFEFFFE;
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161 /* Reset HSEBYP bit */
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162 RCC->CR &= (uint32_t)0xFFFBFFFF;
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164 /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
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165 RCC->CFGR &= (uint32_t)0xFF02FFFF;
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167 /* Disable all interrupts */
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168 RCC->CIR = 0x00000000;
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172 * @brief Configures the External High Speed oscillator (HSE).
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173 * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
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174 * @param RCC_HSE: specifies the new state of the HSE.
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175 * This parameter can be one of the following values:
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176 * @arg RCC_HSE_OFF: HSE oscillator OFF
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177 * @arg RCC_HSE_ON: HSE oscillator ON
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178 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
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181 void RCC_HSEConfig(uint8_t RCC_HSE)
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183 /* Check the parameters */
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184 assert_param(IS_RCC_HSE(RCC_HSE));
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186 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
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187 *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
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189 /* Set the new HSE configuration -------------------------------------------*/
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190 *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
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195 * @brief Waits for HSE start-up.
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197 * @retval An ErrorStatus enumuration value:
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198 * - SUCCESS: HSE oscillator is stable and ready to use
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199 * - ERROR: HSE oscillator not yet ready
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201 ErrorStatus RCC_WaitForHSEStartUp(void)
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203 __IO uint32_t StartUpCounter = 0;
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204 ErrorStatus status = ERROR;
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205 FlagStatus HSEStatus = RESET;
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207 /* Wait till HSE is ready and if Time out is reached exit */
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210 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
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212 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
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214 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
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226 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
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227 * @param HSICalibrationValue: specifies the HSI calibration trimming value.
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228 * This parameter must be a number between 0 and 0x1F.
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231 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
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233 uint32_t tmpreg = 0;
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235 /* Check the parameters */
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236 assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
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238 tmpreg = RCC->ICSCR;
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240 /* Clear HSITRIM[4:0] bits */
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241 tmpreg &= ~RCC_ICSCR_HSITRIM;
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243 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
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244 tmpreg |= (uint32_t)HSICalibrationValue << 8;
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246 /* Store the new value */
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247 RCC->ICSCR = tmpreg;
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251 * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
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252 * @param MSICalibrationValue: specifies the MSI calibration trimming value.
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253 * This parameter must be a number between 0 and 0xFF.
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256 void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)
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259 /* Check the parameters */
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260 assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));
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262 *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue;
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266 * @brief Configures the Internal Multi Speed oscillator (MSI) clock range.
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267 * @param RCC_MSIRange: specifies the MSI Clcok range.
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268 * This parameter must be one of the following values:
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269 * @arg RCC_MSIRange_64KHz: MSI clock is around 64 KHz
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270 * @arg RCC_MSIRange_128KHz: MSI clock is around 128 KHz
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271 * @arg RCC_MSIRange_256KHz: MSI clock is around 256 KHz
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272 * @arg RCC_MSIRange_512KHz: MSI clock is around 512 KHz
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273 * @arg RCC_MSIRange_1MHz: MSI clock is around 1 MHz
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274 * @arg RCC_MSIRange_2MHz: MSI clock is around 2 MHz
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275 * @arg RCC_MSIRange_4MHz: MSI clock is around 4 MHz
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278 void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)
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280 uint32_t tmpreg = 0;
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282 /* Check the parameters */
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283 assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));
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285 tmpreg = RCC->ICSCR;
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287 /* Clear MSIRANGE[2:0] bits */
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288 tmpreg &= ~RCC_ICSCR_MSIRANGE;
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290 /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */
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291 tmpreg |= (uint32_t)RCC_MSIRange;
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293 /* Store the new value */
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294 RCC->ICSCR = tmpreg;
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298 * @brief Enables or disables the Internal Multi Speed oscillator (MSI).
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299 * @note MSI can not be stopped if it is used directly as system clock.
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300 * @param NewState: new state of the MSI.
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301 * This parameter can be: ENABLE or DISABLE.
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304 void RCC_MSICmd(FunctionalState NewState)
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306 /* Check the parameters */
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307 assert_param(IS_FUNCTIONAL_STATE(NewState));
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309 *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;
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313 * @brief Enables or disables the Internal High Speed oscillator (HSI).
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314 * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
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315 * @param NewState: new state of the HSI.
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316 * This parameter can be: ENABLE or DISABLE.
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319 void RCC_HSICmd(FunctionalState NewState)
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321 /* Check the parameters */
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322 assert_param(IS_FUNCTIONAL_STATE(NewState));
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324 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
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328 * @brief Configures the PLL clock source and multiplication factor.
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329 * @note This function must be used only when the PLL is disabled.
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330 * @param RCC_PLLSource: specifies the PLL entry clock source.
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331 * This parameter can be one of the following values:
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332 * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
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333 * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
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334 * @param RCC_PLLMul: specifies the PLL multiplication factor.
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335 * This parameter can be:
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336 * @arg RCC_PLLMul_3: PLL Clock entry multiplied by 3
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337 * @arg RCC_PLLMul_4: PLL Clock entry multiplied by 4
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338 * @arg RCC_PLLMul_6: PLL Clock entry multiplied by 6
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339 * @arg RCC_PLLMul_8: PLL Clock entry multiplied by 8
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340 * @arg RCC_PLLMul_12: PLL Clock entry multiplied by 12
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341 * @arg RCC_PLLMul_16: PLL Clock entry multiplied by 16
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342 * @arg RCC_PLLMul_24: PLL Clock entry multiplied by 24
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343 * @arg RCC_PLLMul_32: PLL Clock entry multiplied by 32
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344 * @arg RCC_PLLMul_48: PLL Clock entry multiplied by 48
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345 * @param RCC_PLLDiv: specifies the PLL division factor.
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346 * This parameter can be:
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347 * @arg RCC_PLLDiv_2: PLL Clock output divided by 2
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348 * @arg RCC_PLLDiv_3: PLL Clock output divided by 3
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349 * @arg RCC_PLLDiv_4: PLL Clock output divided by 4
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352 void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
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354 /* Check the parameters */
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355 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
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356 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
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357 assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));
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359 *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));
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363 * @brief Enables or disables the PLL.
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364 * @note The PLL can not be disabled if it is used as system clock.
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365 * @param NewState: new state of the PLL.
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366 * This parameter can be: ENABLE or DISABLE.
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369 void RCC_PLLCmd(FunctionalState NewState)
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371 /* Check the parameters */
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372 assert_param(IS_FUNCTIONAL_STATE(NewState));
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374 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
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378 * @brief Configures the system clock (SYSCLK).
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379 * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
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380 * This parameter can be one of the following values:
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381 * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock
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382 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
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383 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
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384 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
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387 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
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389 uint32_t tmpreg = 0;
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391 /* Check the parameters */
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392 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
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394 tmpreg = RCC->CFGR;
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396 /* Clear SW[1:0] bits */
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397 tmpreg &= ~RCC_CFGR_SW;
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399 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
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400 tmpreg |= RCC_SYSCLKSource;
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402 /* Store the new value */
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403 RCC->CFGR = tmpreg;
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407 * @brief Returns the clock source used as system clock.
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409 * @retval The clock source used as system clock. The returned value can be one
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410 * of the following values:
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411 * - 0x00: MSI used as system clock
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412 * - 0x04: HSI used as system clock
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413 * - 0x08: HSE used as system clock
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414 * - 0x0C: PLL used as system clock
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416 uint8_t RCC_GetSYSCLKSource(void)
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418 return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
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422 * @brief Configures the AHB clock (HCLK).
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423 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
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424 * the system clock (SYSCLK).
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425 * This parameter can be one of the following values:
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426 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
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427 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
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428 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
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429 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
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430 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
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431 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
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432 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
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433 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
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434 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
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437 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
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439 uint32_t tmpreg = 0;
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441 /* Check the parameters */
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442 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
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444 tmpreg = RCC->CFGR;
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446 /* Clear HPRE[3:0] bits */
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447 tmpreg &= ~RCC_CFGR_HPRE;
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449 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
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450 tmpreg |= RCC_SYSCLK;
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452 /* Store the new value */
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453 RCC->CFGR = tmpreg;
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457 * @brief Configures the Low Speed APB clock (PCLK1).
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458 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
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459 * the AHB clock (HCLK).
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460 * This parameter can be one of the following values:
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461 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
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462 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
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463 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
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464 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
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465 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
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468 void RCC_PCLK1Config(uint32_t RCC_HCLK)
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470 uint32_t tmpreg = 0;
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472 /* Check the parameters */
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473 assert_param(IS_RCC_PCLK(RCC_HCLK));
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475 tmpreg = RCC->CFGR;
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477 /* Clear PPRE1[2:0] bits */
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478 tmpreg &= ~RCC_CFGR_PPRE1;
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480 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
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481 tmpreg |= RCC_HCLK;
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483 /* Store the new value */
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484 RCC->CFGR = tmpreg;
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488 * @brief Configures the High Speed APB clock (PCLK2).
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489 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
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490 * the AHB clock (HCLK).
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491 * This parameter can be one of the following values:
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492 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
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493 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
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494 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
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495 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
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496 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
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499 void RCC_PCLK2Config(uint32_t RCC_HCLK)
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501 uint32_t tmpreg = 0;
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503 /* Check the parameters */
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504 assert_param(IS_RCC_PCLK(RCC_HCLK));
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506 tmpreg = RCC->CFGR;
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508 /* Clear PPRE2[2:0] bits */
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509 tmpreg &= ~RCC_CFGR_PPRE2;
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511 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
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512 tmpreg |= RCC_HCLK << 3;
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514 /* Store the new value */
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515 RCC->CFGR = tmpreg;
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519 * @brief Enables or disables the specified RCC interrupts.
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520 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
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521 * This parameter can be any combination of the following values:
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522 * @arg RCC_IT_LSIRDY: LSI ready interrupt
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523 * @arg RCC_IT_LSERDY: LSE ready interrupt
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524 * @arg RCC_IT_HSIRDY: HSI ready interrupt
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525 * @arg RCC_IT_HSERDY: HSE ready interrupt
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526 * @arg RCC_IT_PLLRDY: PLL ready interrupt
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527 * @arg RCC_IT_MSIRDY: MSI ready interrupt
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528 * @param NewState: new state of the specified RCC interrupts.
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529 * This parameter can be: ENABLE or DISABLE.
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532 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
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534 /* Check the parameters */
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535 assert_param(IS_RCC_IT(RCC_IT));
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536 assert_param(IS_FUNCTIONAL_STATE(NewState));
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538 if (NewState != DISABLE)
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540 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
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541 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
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545 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
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546 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
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551 * @brief Configures the External Low Speed oscillator (LSE).
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552 * @param RCC_LSE: specifies the new state of the LSE.
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553 * This parameter can be one of the following values:
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554 * @arg RCC_LSE_OFF: LSE oscillator OFF
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555 * @arg RCC_LSE_ON: LSE oscillator ON
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556 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
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559 void RCC_LSEConfig(uint8_t RCC_LSE)
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561 /* Check the parameters */
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562 assert_param(IS_RCC_LSE(RCC_LSE));
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564 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
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565 *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;
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567 /* Set the new LSE configuration -------------------------------------------*/
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568 *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE;
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572 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
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573 * @note LSI can not be disabled if the IWDG is running.
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574 * @param NewState: new state of the LSI.
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575 * This parameter can be: ENABLE or DISABLE.
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578 void RCC_LSICmd(FunctionalState NewState)
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580 /* Check the parameters */
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581 assert_param(IS_FUNCTIONAL_STATE(NewState));
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583 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
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587 * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).
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589 * - Once the RTC clock is selected it can't be changed unless the RTC is
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590 * reset using RCC_RTCResetCmd function.
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591 * - This RTC clock (RTCCLK) is used to clock the LCD (LCDCLK).
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592 * @param RCC_RTCCLKSource: specifies the RTC clock source.
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593 * This parameter can be one of the following values:
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594 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
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595 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
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596 * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
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597 * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
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598 * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
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599 * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
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602 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
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604 uint32_t tmpreg = 0;
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606 /* Check the parameters */
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607 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
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609 if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)
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611 /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
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614 /* Clear RTCPRE[1:0] bits */
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615 tmpreg &= ~RCC_CR_RTCPRE;
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617 /* Configure HSE division factor for RTC clock */
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618 tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);
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620 /* Store the new value */
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624 RCC->CSR &= ~RCC_CSR_RTCSEL;
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626 /* Select the RTC clock source */
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627 RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);
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631 * @brief Enables or disables the RTC clock.
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632 * @note This function must be used only after the RTC clock was selected using the
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633 * RCC_RTCCLKConfig function.
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634 * @param NewState: new state of the RTC clock.
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635 * This parameter can be: ENABLE or DISABLE.
\r
638 void RCC_RTCCLKCmd(FunctionalState NewState)
\r
640 /* Check the parameters */
\r
641 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
643 *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;
\r
647 * @brief Forces or releases the RTC peripheral reset.
\r
648 * @param NewState: new state of the RTC reset.
\r
649 * This parameter can be: ENABLE or DISABLE.
\r
652 void RCC_RTCResetCmd(FunctionalState NewState)
\r
654 /* Check the parameters */
\r
655 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
657 *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;
\r
661 * @brief Returns the frequencies of different on chip clocks.
\r
662 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
\r
663 * the clocks frequencies.
\r
666 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
\r
668 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;
\r
670 /* Get SYSCLK source -------------------------------------------------------*/
\r
671 tmp = RCC->CFGR & RCC_CFGR_SWS;
\r
675 case 0x00: /* MSI used as system clock */
\r
676 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
\r
677 RCC_Clocks->SYSCLK_Frequency = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));
\r
679 case 0x04: /* HSI used as system clock */
\r
680 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
\r
682 case 0x08: /* HSE used as system clock */
\r
683 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
\r
685 case 0x0C: /* PLL used as system clock */
\r
686 /* Get PLL clock source and multiplication factor ----------------------*/
\r
687 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
\r
688 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
\r
689 pllmul = PLLMulTable[(pllmul >> 18)];
\r
690 plldiv = (plldiv >> 22) + 1;
\r
692 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
\r
694 if (pllsource == 0x00)
\r
696 /* HSI oscillator clock selected as PLL clock entry */
\r
697 RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);
\r
701 /* HSE selected as PLL clock entry */
\r
702 RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);
\r
706 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
\r
709 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
\r
710 /* Get HCLK prescaler */
\r
711 tmp = RCC->CFGR & RCC_CFGR_HPRE;
\r
713 presc = APBAHBPrescTable[tmp];
\r
714 /* HCLK clock frequency */
\r
715 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
\r
717 /* Get PCLK1 prescaler */
\r
718 tmp = RCC->CFGR & RCC_CFGR_PPRE1;
\r
720 presc = APBAHBPrescTable[tmp];
\r
721 /* PCLK1 clock frequency */
\r
722 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\r
724 /* Get PCLK2 prescaler */
\r
725 tmp = RCC->CFGR & RCC_CFGR_PPRE2;
\r
727 presc = APBAHBPrescTable[tmp];
\r
728 /* PCLK2 clock frequency */
\r
729 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\r
733 * @brief Enables or disables the AHB peripheral clock.
\r
734 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
\r
735 * This parameter can be any combination of the following values:
\r
736 * @arg RCC_AHBPeriph_GPIOA
\r
737 * @arg RCC_AHBPeriph_GPIOB
\r
738 * @arg RCC_AHBPeriph_GPIOC
\r
739 * @arg RCC_AHBPeriph_GPIOD
\r
740 * @arg RCC_AHBPeriph_GPIOE
\r
741 * @arg RCC_AHBPeriph_GPIOH
\r
742 * @arg RCC_AHBPeriph_CRC
\r
743 * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
\r
744 * @arg RCC_AHBPeriph_DMA1
\r
745 * @param NewState: new state of the specified peripheral clock.
\r
746 * This parameter can be: ENABLE or DISABLE.
\r
749 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
\r
751 /* Check the parameters */
\r
752 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
\r
753 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
755 if (NewState != DISABLE)
\r
757 RCC->AHBENR |= RCC_AHBPeriph;
\r
761 RCC->AHBENR &= ~RCC_AHBPeriph;
\r
766 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
\r
767 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
\r
768 * This parameter can be any combination of the following values:
\r
769 * @arg RCC_APB2Periph_SYSCFG
\r
770 * @arg RCC_APB2Periph_TIM9
\r
771 * @arg RCC_APB2Periph_TIM10
\r
772 * @arg RCC_APB2Periph_TIM11
\r
773 * @arg RCC_APB2Periph_ADC1
\r
774 * @arg RCC_APB2Periph_SPI1
\r
775 * @arg RCC_APB2Periph_USART1
\r
776 * @param NewState: new state of the specified peripheral clock.
\r
777 * This parameter can be: ENABLE or DISABLE.
\r
780 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
\r
782 /* Check the parameters */
\r
783 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
\r
784 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
786 if (NewState != DISABLE)
\r
788 RCC->APB2ENR |= RCC_APB2Periph;
\r
792 RCC->APB2ENR &= ~RCC_APB2Periph;
\r
797 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
\r
798 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
\r
799 * This parameter can be any combination of the following values:
\r
800 * @arg RCC_APB1Periph_TIM2
\r
801 * @arg RCC_APB1Periph_TIM3
\r
802 * @arg RCC_APB1Periph_TIM4
\r
803 * @arg RCC_APB1Periph_TIM6
\r
804 * @arg RCC_APB1Periph_TIM7
\r
805 * @arg RCC_APB1Periph_LCD
\r
806 * @arg RCC_APB1Periph_WWDG
\r
807 * @arg RCC_APB1Periph_SPI2
\r
808 * @arg RCC_APB1Periph_USART2
\r
809 * @arg RCC_APB1Periph_USART3
\r
810 * @arg RCC_APB1Periph_I2C1
\r
811 * @arg RCC_APB1Periph_I2C2
\r
812 * @arg RCC_APB1Periph_USB
\r
813 * @arg RCC_APB1Periph_PWR
\r
814 * @arg RCC_APB1Periph_DAC
\r
815 * @arg RCC_APB1Periph_COMP
\r
816 * @param NewState: new state of the specified peripheral clock.
\r
817 * This parameter can be: ENABLE or DISABLE.
\r
820 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
\r
822 /* Check the parameters */
\r
823 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
\r
824 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
826 if (NewState != DISABLE)
\r
828 RCC->APB1ENR |= RCC_APB1Periph;
\r
832 RCC->APB1ENR &= ~RCC_APB1Periph;
\r
837 * @brief Forces or releases AHB peripheral reset.
\r
838 * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
\r
839 * This parameter can be any combination of the following values:
\r
840 * @arg RCC_AHBPeriph_GPIOA
\r
841 * @arg RCC_AHBPeriph_GPIOB
\r
842 * @arg RCC_AHBPeriph_GPIOC
\r
843 * @arg RCC_AHBPeriph_GPIOD
\r
844 * @arg RCC_AHBPeriph_GPIOE
\r
845 * @arg RCC_AHBPeriph_GPIOH
\r
846 * @arg RCC_AHBPeriph_CRC
\r
847 * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
\r
848 * @arg RCC_AHBPeriph_DMA1
\r
849 * @param NewState: new state of the specified peripheral reset.
\r
850 * This parameter can be: ENABLE or DISABLE.
\r
853 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
\r
855 /* Check the parameters */
\r
856 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
\r
857 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
859 if (NewState != DISABLE)
\r
861 RCC->AHBRSTR |= RCC_AHBPeriph;
\r
865 RCC->AHBRSTR &= ~RCC_AHBPeriph;
\r
870 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
\r
871 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
\r
872 * This parameter can be any combination of the following values:
\r
873 * @arg RCC_APB2Periph_SYSCFG
\r
874 * @arg RCC_APB2Periph_TIM9
\r
875 * @arg RCC_APB2Periph_TIM10
\r
876 * @arg RCC_APB2Periph_TIM11
\r
877 * @arg RCC_APB2Periph_ADC1
\r
878 * @arg RCC_APB2Periph_SPI1
\r
879 * @arg RCC_APB2Periph_USART1
\r
880 * @param NewState: new state of the specified peripheral reset.
\r
881 * This parameter can be: ENABLE or DISABLE.
\r
884 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
\r
886 /* Check the parameters */
\r
887 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
\r
888 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
890 if (NewState != DISABLE)
\r
892 RCC->APB2RSTR |= RCC_APB2Periph;
\r
896 RCC->APB2RSTR &= ~RCC_APB2Periph;
\r
901 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
\r
902 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
\r
903 * This parameter can be any combination of the following values:
\r
904 * @arg RCC_APB1Periph_TIM2
\r
905 * @arg RCC_APB1Periph_TIM3
\r
906 * @arg RCC_APB1Periph_TIM4
\r
907 * @arg RCC_APB1Periph_TIM6
\r
908 * @arg RCC_APB1Periph_TIM7
\r
909 * @arg RCC_APB1Periph_LCD
\r
910 * @arg RCC_APB1Periph_WWDG
\r
911 * @arg RCC_APB1Periph_SPI2
\r
912 * @arg RCC_APB1Periph_USART2
\r
913 * @arg RCC_APB1Periph_USART3
\r
914 * @arg RCC_APB1Periph_I2C1
\r
915 * @arg RCC_APB1Periph_I2C2
\r
916 * @arg RCC_APB1Periph_USB
\r
917 * @arg RCC_APB1Periph_PWR
\r
918 * @arg RCC_APB1Periph_DAC
\r
919 * @arg RCC_APB1Periph_COMP
\r
920 * @param NewState: new state of the specified peripheral clock.
\r
921 * This parameter can be: ENABLE or DISABLE.
\r
924 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
\r
926 /* Check the parameters */
\r
927 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
\r
928 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
930 if (NewState != DISABLE)
\r
932 RCC->APB1RSTR |= RCC_APB1Periph;
\r
936 RCC->APB1RSTR &= ~RCC_APB1Periph;
\r
941 * @brief Enables or disables the AHB peripheral clock during Low Power (SLEEP) mode.
\r
942 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
\r
943 * This parameter can be any combination of the following values:
\r
944 * @arg RCC_AHBPeriph_GPIOA
\r
945 * @arg RCC_AHBPeriph_GPIOB
\r
946 * @arg RCC_AHBPeriph_GPIOC
\r
947 * @arg RCC_AHBPeriph_GPIOD
\r
948 * @arg RCC_AHBPeriph_GPIOE
\r
949 * @arg RCC_AHBPeriph_GPIOH
\r
950 * @arg RCC_AHBPeriph_CRC
\r
951 * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
\r
952 * @arg RCC_AHBPeriph_SRAM
\r
953 * @arg RCC_AHBPeriph_DMA1
\r
954 * @param NewState: new state of the specified peripheral clock.
\r
955 * This parameter can be: ENABLE or DISABLE.
\r
958 void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
\r
960 /* Check the parameters */
\r
961 assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));
\r
962 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
964 if (NewState != DISABLE)
\r
966 RCC->AHBLPENR |= RCC_AHBPeriph;
\r
970 RCC->AHBLPENR &= ~RCC_AHBPeriph;
\r
975 * @brief Enables or disables the APB2 peripheral clock during Low Power (SLEEP) mode.
\r
976 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
\r
977 * This parameter can be any combination of the following values:
\r
978 * @arg RCC_APB2Periph_SYSCFG
\r
979 * @arg RCC_APB2Periph_TIM9
\r
980 * @arg RCC_APB2Periph_TIM10
\r
981 * @arg RCC_APB2Periph_TIM11
\r
982 * @arg RCC_APB2Periph_ADC1
\r
983 * @arg RCC_APB2Periph_SPI1
\r
984 * @arg RCC_APB2Periph_USART1
\r
985 * @param NewState: new state of the specified peripheral clock.
\r
986 * This parameter can be: ENABLE or DISABLE.
\r
989 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
\r
991 /* Check the parameters */
\r
992 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
\r
993 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
995 if (NewState != DISABLE)
\r
997 RCC->APB2LPENR |= RCC_APB2Periph;
\r
1001 RCC->APB2LPENR &= ~RCC_APB2Periph;
\r
1006 * @brief Enables or disables the APB1 peripheral clock during Low Power (SLEEP) mode.
\r
1007 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
\r
1008 * This parameter can be any combination of the following values:
\r
1009 * @arg RCC_APB1Periph_TIM2
\r
1010 * @arg RCC_APB1Periph_TIM3
\r
1011 * @arg RCC_APB1Periph_TIM4
\r
1012 * @arg RCC_APB1Periph_TIM6
\r
1013 * @arg RCC_APB1Periph_TIM7
\r
1014 * @arg RCC_APB1Periph_LCD
\r
1015 * @arg RCC_APB1Periph_WWDG
\r
1016 * @arg RCC_APB1Periph_SPI2
\r
1017 * @arg RCC_APB1Periph_USART2
\r
1018 * @arg RCC_APB1Periph_USART3
\r
1019 * @arg RCC_APB1Periph_I2C1
\r
1020 * @arg RCC_APB1Periph_I2C2
\r
1021 * @arg RCC_APB1Periph_USB
\r
1022 * @arg RCC_APB1Periph_PWR
\r
1023 * @arg RCC_APB1Periph_DAC
\r
1024 * @arg RCC_APB1Periph_COMP
\r
1025 * @param NewState: new state of the specified peripheral clock.
\r
1026 * This parameter can be: ENABLE or DISABLE.
\r
1029 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
\r
1031 /* Check the parameters */
\r
1032 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
\r
1033 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1035 if (NewState != DISABLE)
\r
1037 RCC->APB1LPENR |= RCC_APB1Periph;
\r
1041 RCC->APB1LPENR &= ~RCC_APB1Periph;
\r
1046 * @brief Enables or disables the Clock Security System.
\r
1047 * @param NewState: new state of the Clock Security System..
\r
1048 * This parameter can be: ENABLE or DISABLE.
\r
1051 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
\r
1053 /* Check the parameters */
\r
1054 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1056 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
\r
1060 * @brief Selects the clock source to output on MCO pin.
\r
1061 * @param RCC_MCOSource: specifies the clock source to output.
\r
1062 * This parameter can be one of the following values:
\r
1063 * @arg RCC_MCOSource_NoClock: No clock selected
\r
1064 * @arg RCC_MCOSource_SYSCLK: System clock selected
\r
1065 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected
\r
1066 * @arg RCC_MCOSource_MSI: MSI oscillator clock selected
\r
1067 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected
\r
1068 * @arg RCC_MCOSource_PLLCLK: PLL clock selected
\r
1069 * @arg RCC_MCOSource_LSI: LSI clock selected
\r
1070 * @arg RCC_MCOSource_LSE: LSE clock selected
\r
1071 * @param RCC_MCODiv: specifies the MCO prescaler.
\r
1072 * This parameter can be one of the following values:
\r
1073 * @arg RCC_MCODiv_1: no division applied to MCO clock
\r
1074 * @arg RCC_MCODiv_2: division by 2 applied to MCO clock
\r
1075 * @arg RCC_MCODiv_4: division by 4 applied to MCO clock
\r
1076 * @arg RCC_MCODiv_8: division by 8 applied to MCO clock
\r
1077 * @arg RCC_MCODiv_16: division by 16 applied to MCO clock
\r
1080 void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
\r
1082 /* Check the parameters */
\r
1083 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
\r
1084 assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));
\r
1086 /* Select MCO clock source and prescaler */
\r
1087 *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv;
\r
1091 * @brief Checks whether the specified RCC flag is set or not.
\r
1092 * @param RCC_FLAG: specifies the flag to check.
\r
1093 * This parameter can be one of the following values:
\r
1094 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
\r
1095 * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
\r
1096 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
\r
1097 * @arg RCC_FLAG_PLLRDY: PLL clock ready
\r
1098 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
\r
1099 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
\r
1100 * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
\r
1101 * @arg RCC_FLAG_PINRST: Pin reset
\r
1102 * @arg RCC_FLAG_PORRST: POR/PDR reset
\r
1103 * @arg RCC_FLAG_SFTRST: Software reset
\r
1104 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
\r
1105 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
\r
1106 * @arg RCC_FLAG_LPWRRST: Low Power reset
\r
1107 * @retval The new state of RCC_FLAG (SET or RESET).
\r
1109 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
\r
1112 uint32_t statusreg = 0;
\r
1113 FlagStatus bitstatus = RESET;
\r
1115 /* Check the parameters */
\r
1116 assert_param(IS_RCC_FLAG(RCC_FLAG));
\r
1118 /* Get the RCC register index */
\r
1119 tmp = RCC_FLAG >> 5;
\r
1121 if (tmp == 1) /* The flag to check is in CR register */
\r
1123 statusreg = RCC->CR;
\r
1125 else /* The flag to check is in CSR register (tmp == 2) */
\r
1127 statusreg = RCC->CSR;
\r
1130 /* Get the flag position */
\r
1131 tmp = RCC_FLAG & FLAG_MASK;
\r
1133 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
\r
1139 bitstatus = RESET;
\r
1141 /* Return the flag status */
\r
1146 * @brief Clears the RCC reset flags.
\r
1147 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
\r
1148 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
\r
1152 void RCC_ClearFlag(void)
\r
1154 /* Set RMVF bit to clear the reset flags */
\r
1155 RCC->CSR |= RCC_CSR_RMVF;
\r
1159 * @brief Checks whether the specified RCC interrupt has occurred or not.
\r
1160 * @param RCC_IT: specifies the RCC interrupt source to check.
\r
1161 * This parameter can be one of the following values:
\r
1162 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
1163 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
1164 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
1165 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
1166 * @arg RCC_IT_PLLRDY: PLL ready interrupt
\r
1167 * @arg RCC_IT_MSIRDY: MSI ready interrupt
\r
1168 * @arg RCC_IT_CSS: Clock Security System interrupt
\r
1169 * @retval The new state of RCC_IT (SET or RESET).
\r
1171 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
\r
1173 ITStatus bitstatus = RESET;
\r
1174 /* Check the parameters */
\r
1175 assert_param(IS_RCC_GET_IT(RCC_IT));
\r
1177 /* Check the status of the specified RCC interrupt */
\r
1178 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
\r
1184 bitstatus = RESET;
\r
1186 /* Return the RCC_IT status */
\r
1191 * @brief Clears the RCC's interrupt pending bits.
\r
1192 * @param RCC_IT: specifies the interrupt pending bit to clear.
\r
1193 * This parameter can be any combination of the following values:
\r
1194 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
1195 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
1196 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
1197 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
1198 * @arg RCC_IT_PLLRDY: PLL ready interrupt
\r
1199 * @arg RCC_IT_MSIRDY: MSI ready interrupt
\r
1200 * @arg RCC_IT_CSS: Clock Security System interrupt
\r
1203 void RCC_ClearITPendingBit(uint8_t RCC_IT)
\r
1205 /* Check the parameters */
\r
1206 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
\r
1208 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
\r
1210 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
\r
1225 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r