2 ******************************************************************************
\r
3 * @file system_stm32l1xx.c
\r
4 * @author MCD Application Team
\r
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
\r
8 ******************************************************************************
\r
10 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
\r
11 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
\r
12 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
\r
13 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
\r
14 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
\r
15 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
\r
17 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
\r
18 ******************************************************************************
\r
21 /** @addtogroup CMSIS
\r
25 /** @addtogroup stm32l1xx_system
\r
29 /** @addtogroup STM32L1xx_System_Private_Includes
\r
33 #include "stm32l1xx.h"
\r
39 /** @addtogroup STM32L1xx_System_Private_TypesDefinitions
\r
47 /** @addtogroup STM32L1xx_System_Private_Defines
\r
51 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
\r
52 frequency (after reset the MSI is used as SYSCLK source)
\r
56 1. After each device reset the MSI is used as System clock source.
\r
58 2. Please make sure that the selected System clock doesn't exceed your device's
\r
61 3. If none of the define below is enabled, the MSI (2MHz default) is used as
\r
62 System clock source.
\r
64 4. The System clock configuration functions provided within this file assume that:
\r
65 - For Ultra Low Power Medium Mensity devices an external 8MHz crystal is
\r
66 used to drive the System clock.
\r
67 If you are using different crystal you have to adapt those functions accordingly.
\r
70 /* #define SYSCLK_FREQ_MSI */
\r
72 #ifndef SYSCLK_FREQ_MSI
\r
73 /* #define SYSCLK_FREQ_HSI HSI_VALUE */
\r
74 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
\r
75 /* #define SYSCLK_FREQ_4MHz 4000000 */
\r
76 /* #define SYSCLK_FREQ_8MHz 8000000 */
\r
77 /* #define SYSCLK_FREQ_16MHz 16000000 */
\r
78 #define SYSCLK_FREQ_32MHz 32000000
\r
80 /* #define SYSCLK_FREQ_MSI_64KHz 64000 */
\r
81 /* #define SYSCLK_FREQ_MSI_128KHz 128000 */
\r
82 /* #define SYSCLK_FREQ_MSI_256KHz 256000 */
\r
83 /* #define SYSCLK_FREQ_MSI_512KHz 512000 */
\r
84 /* #define SYSCLK_FREQ_MSI_1MHz 1000000 */
\r
85 /* #define SYSCLK_FREQ_MSI_2MHz 2000000 */
\r
86 /* #define SYSCLK_FREQ_MSI_4MHz 4000000 */
\r
93 /** @addtogroup STM32L1xx_System_Private_Macros
\r
101 /** @addtogroup STM32L1xx_System_Private_Variables
\r
105 /*******************************************************************************
\r
106 * Clock Definitions
\r
107 *******************************************************************************/
\r
108 #ifndef SYSCLK_FREQ_MSI
\r
109 #ifdef SYSCLK_FREQ_HSI
\r
110 uint32_t SystemCoreClock = SYSCLK_FREQ_HSI; /*!< System Clock Frequency (Core Clock) */
\r
111 #elif defined SYSCLK_FREQ_HSE
\r
112 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
\r
113 #elif defined SYSCLK_FREQ_4MHz
\r
114 uint32_t SystemCoreClock = SYSCLK_FREQ_4MHz; /*!< System Clock Frequency (Core Clock) */
\r
115 #elif defined SYSCLK_FREQ_8MHz
\r
116 uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz; /*!< System Clock Frequency (Core Clock) */
\r
117 #elif defined SYSCLK_FREQ_16MHz
\r
118 uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz; /*!< System Clock Frequency (Core Clock) */
\r
119 #elif defined SYSCLK_FREQ_32MHz
\r
120 uint32_t SystemCoreClock = SYSCLK_FREQ_32MHz; /*!< System Clock Frequency (Core Clock) */
\r
121 #else /*!< MSI Selected as System Clock source */
\r
122 uint32_t SystemCoreClock = MSI_VALUE; /*!< System Clock Frequency (Core Clock) */
\r
125 #ifdef SYSCLK_FREQ_MSI_64KHz
\r
126 uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_64KHz; /*!< System Clock Frequency (Core Clock) */
\r
127 #elif defined SYSCLK_FREQ_MSI_128KHz
\r
128 uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_128KHz; /*!< System Clock Frequency (Core Clock) */
\r
129 #elif defined SYSCLK_FREQ_MSI_256KHz
\r
130 uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_256KHz; /*!< System Clock Frequency (Core Clock) */
\r
131 #elif defined SYSCLK_FREQ_MSI_512KHz
\r
132 uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_512KHz; /*!< System Clock Frequency (Core Clock) */
\r
133 #elif defined SYSCLK_FREQ_MSI_1MHz
\r
134 uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_1MHz; /*!< System Clock Frequency (Core Clock) */
\r
135 #elif defined SYSCLK_FREQ_MSI_2MHz
\r
136 uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_2MHz; /*!< System Clock Frequency (Core Clock) */
\r
137 #elif defined SYSCLK_FREQ_MSI_4MHz
\r
138 uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_4MHz; /*!< System Clock Frequency (Core Clock) */
\r
140 uint32_t SystemCoreClock = MSI_VALUE; /*!< System Clock Frequency (Core Clock) */
\r
144 __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
\r
145 __I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};
\r
146 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
\r
152 /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
\r
156 static void SetSysClock(void);
\r
158 #ifdef SYSCLK_FREQ_HSI
\r
159 static void SetSysClockToHSI(void);
\r
160 #elif defined SYSCLK_FREQ_HSE
\r
161 static void SetSysClockToHSE(void);
\r
162 #elif defined SYSCLK_FREQ_4MHz
\r
163 static void SetSysClockTo4(void);
\r
164 #elif defined SYSCLK_FREQ_8MHz
\r
165 static void SetSysClockTo8(void);
\r
166 #elif defined SYSCLK_FREQ_16MHz
\r
167 static void SetSysClockTo16(void);
\r
168 #elif defined SYSCLK_FREQ_32MHz
\r
169 static void SetSysClockTo32(void);
\r
171 static void SetSysClockToMSI(void);
\r
178 /** @addtogroup STM32L1xx_System_Private_Functions
\r
183 * @brief Setup the microcontroller system
\r
184 * Initialize the Embedded Flash Interface, the PLL and update the
\r
185 * SystemCoreClock variable
\r
186 * @note This function should be used only after reset.
\r
190 void SystemInit (void)
\r
192 /*!< Set MSION bit */
\r
193 RCC->CR |= (uint32_t)0x00000100;
\r
195 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
\r
196 RCC->CFGR &= (uint32_t)0x88FFC00C;
\r
198 /*!< Reset HSION, HSEON, CSSON and PLLON bits */
\r
199 RCC->CR &= (uint32_t)0xEEFEFFFE;
\r
201 /*!< Reset HSEBYP bit */
\r
202 RCC->CR &= (uint32_t)0xFFFBFFFF;
\r
204 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
\r
205 RCC->CFGR &= (uint32_t)0xFF02FFFF;
\r
207 /*!< Disable all interrupts */
\r
208 RCC->CIR = 0x00000000;
\r
210 /*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
\r
211 /*!< Configure the Flash Latency cycles and enable prefetch buffer */
\r
217 * @brief Update SystemCoreClock according to Clock Register Values
\r
222 void SystemCoreClockUpdate (void)
\r
224 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
\r
226 /* Get SYSCLK source -------------------------------------------------------*/
\r
227 tmp = RCC->CFGR & RCC_CFGR_SWS;
\r
231 case 0x00: /* MSI used as system clock */
\r
232 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
\r
233 SystemCoreClock = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));
\r
235 case 0x04: /* HSI used as system clock */
\r
236 SystemCoreClock = HSI_VALUE;
\r
238 case 0x08: /* HSE used as system clock */
\r
239 SystemCoreClock = HSE_VALUE;
\r
241 case 0x0C: /* PLL used as system clock */
\r
242 /* Get PLL clock source and multiplication factor ----------------------*/
\r
243 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
\r
244 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
\r
245 pllmul = PLLMulTable[(pllmul >> 18)];
\r
246 plldiv = (plldiv >> 22) + 1;
\r
248 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
\r
250 if (pllsource == 0x00)
\r
252 /* HSI oscillator clock selected as PLL clock entry */
\r
253 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
\r
257 /* HSE selected as PLL clock entry */
\r
258 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
\r
262 SystemCoreClock = MSI_VALUE;
\r
265 /* Compute HCLK clock frequency --------------------------------------------*/
\r
266 /* Get HCLK prescaler */
\r
267 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
\r
268 /* HCLK clock frequency */
\r
269 SystemCoreClock >>= tmp;
\r
273 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
\r
277 static void SetSysClock(void)
\r
279 #ifdef SYSCLK_FREQ_HSI
\r
280 SetSysClockToHSI();
\r
281 #elif defined SYSCLK_FREQ_HSE
\r
282 SetSysClockToHSE();
\r
283 #elif defined SYSCLK_FREQ_4MHz
\r
285 #elif defined SYSCLK_FREQ_8MHz
\r
287 #elif defined SYSCLK_FREQ_16MHz
\r
289 #elif defined SYSCLK_FREQ_32MHz
\r
292 SetSysClockToMSI();
\r
295 /* If none of the define above is enabled, the MSI (2MHz default) is used as
\r
296 System clock source (default after reset) */
\r
299 #ifdef SYSCLK_FREQ_HSI
\r
301 * @brief Selects HSI as System clock source and configure HCLK, PCLK2
\r
302 * and PCLK1 prescalers.
\r
303 * @note This function should be used only after reset.
\r
307 static void SetSysClockToHSI(void)
\r
309 __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
\r
311 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
313 RCC->CR |= ((uint32_t)RCC_CR_HSION);
\r
315 /* Wait till HSI is ready and if Time out is reached exit */
\r
318 HSIStatus = RCC->CR & RCC_CR_HSIRDY;
\r
320 } while((HSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
322 if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
\r
324 HSIStatus = (uint32_t)0x01;
\r
328 HSIStatus = (uint32_t)0x00;
\r
331 if (HSIStatus == (uint32_t)0x01)
\r
333 /* Enable 64-bit access */
\r
334 FLASH->ACR |= FLASH_ACR_ACC64;
\r
336 /* Enable Prefetch Buffer */
\r
337 FLASH->ACR |= FLASH_ACR_PRFTEN;
\r
339 /* Flash 1 wait state */
\r
340 FLASH->ACR |= FLASH_ACR_LATENCY;
\r
342 /* Enable the PWR APB1 Clock */
\r
343 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
\r
345 /* Select the Voltage Range 1 (1.8V) */
\r
346 PWR->CR = PWR_CR_VOS_0;
\r
348 /* Wait Until the Voltage Regulator is ready */
\r
349 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
\r
353 /* HCLK = SYSCLK */
\r
354 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
357 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
360 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
\r
362 /* Select HSI as system clock source */
\r
363 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
364 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
\r
366 /* Wait till HSI is used as system clock source */
\r
367 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
\r
373 /* If HSI fails to start-up, the application will have wrong clock
\r
374 configuration. User can add here some code to deal with this error */
\r
378 #elif defined SYSCLK_FREQ_HSE
\r
380 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
\r
381 * and PCLK1 prescalers.
\r
382 * @note This function should be used only after reset.
\r
386 static void SetSysClockToHSE(void)
\r
388 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
390 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
392 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
394 /* Wait till HSE is ready and if Time out is reached exit */
\r
397 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
399 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
401 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
403 HSEStatus = (uint32_t)0x01;
\r
407 HSEStatus = (uint32_t)0x00;
\r
410 if (HSEStatus == (uint32_t)0x01)
\r
412 /* Flash 0 wait state */
\r
413 FLASH->ACR &= ~FLASH_ACR_LATENCY;
\r
415 /* Disable Prefetch Buffer */
\r
416 FLASH->ACR &= ~FLASH_ACR_PRFTEN;
\r
418 /* Disable 64-bit access */
\r
419 FLASH->ACR &= ~FLASH_ACR_ACC64;
\r
421 /* Enable the PWR APB1 Clock */
\r
422 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
\r
424 /* Select the Voltage Range 2 (1.5V) */
\r
425 PWR->CR = PWR_CR_VOS_1;
\r
427 /* Wait Until the Voltage Regulator is ready */
\r
428 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
\r
432 /* HCLK = SYSCLK */
\r
433 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
436 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
439 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
\r
441 /* Select HSE as system clock source */
\r
442 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
443 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
\r
445 /* Wait till HSE is used as system clock source */
\r
446 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
452 /* If HSE fails to start-up, the application will have wrong clock
\r
453 configuration. User can add here some code to deal with this error */
\r
456 #elif defined SYSCLK_FREQ_4MHz
\r
458 * @brief Sets System clock frequency to 4MHz and configure HCLK, PCLK2
\r
459 * and PCLK1 prescalers.
\r
460 * @note This function should be used only after reset.
\r
464 static void SetSysClockTo4(void)
\r
466 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
468 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
470 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
472 /* Wait till HSE is ready and if Time out is reached exit */
\r
475 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
477 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
479 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
481 HSEStatus = (uint32_t)0x01;
\r
485 HSEStatus = (uint32_t)0x00;
\r
488 if (HSEStatus == (uint32_t)0x01)
\r
490 /* Flash 0 wait state */
\r
491 FLASH->ACR &= ~FLASH_ACR_LATENCY;
\r
493 /* Disable Prefetch Buffer */
\r
494 FLASH->ACR &= ~FLASH_ACR_PRFTEN;
\r
496 /* Disable 64-bit access */
\r
497 FLASH->ACR &= ~FLASH_ACR_ACC64;
\r
499 /* Enable the PWR APB1 Clock */
\r
500 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
\r
502 /* Select the Voltage Range 2 (1.5V) */
\r
503 PWR->CR = PWR_CR_VOS_1;
\r
505 /* Wait Until the Voltage Regulator is ready */
\r
506 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
\r
510 /* HCLK = SYSCLK */
\r
511 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;
\r
514 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
517 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
\r
519 /* Select HSE as system clock source */
\r
520 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
521 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
\r
523 /* Wait till HSE is used as system clock source */
\r
524 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
530 /* If HSE fails to start-up, the application will have wrong clock
\r
531 configuration. User can add here some code to deal with this error */
\r
535 #elif defined SYSCLK_FREQ_8MHz
\r
537 * @brief Sets System clock frequency to 8MHz and configure HCLK, PCLK2
\r
538 * and PCLK1 prescalers.
\r
539 * @note This function should be used only after reset.
\r
543 static void SetSysClockTo8(void)
\r
545 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
547 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
549 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
551 /* Wait till HSE is ready and if Time out is reached exit */
\r
554 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
556 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
558 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
560 HSEStatus = (uint32_t)0x01;
\r
564 HSEStatus = (uint32_t)0x00;
\r
567 if (HSEStatus == (uint32_t)0x01)
\r
569 /* Flash 0 wait state */
\r
570 FLASH->ACR &= ~FLASH_ACR_LATENCY;
\r
572 /* Disable Prefetch Buffer */
\r
573 FLASH->ACR &= ~FLASH_ACR_PRFTEN;
\r
575 /* Disable 64-bit access */
\r
576 FLASH->ACR &= ~FLASH_ACR_ACC64;
\r
578 /* Enable the PWR APB1 Clock */
\r
579 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
\r
581 /* Select the Voltage Range 2 (1.5V) */
\r
582 PWR->CR = PWR_CR_VOS_1;
\r
584 /* Wait Until the Voltage Regulator is ready */
\r
585 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
\r
589 /* HCLK = SYSCLK */
\r
590 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
593 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
596 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
\r
598 /* Select HSE as system clock source */
\r
599 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
600 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
\r
602 /* Wait till HSE is used as system clock source */
\r
603 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
609 /* If HSE fails to start-up, the application will have wrong clock
\r
610 configuration. User can add here some code to deal with this error */
\r
614 #elif defined SYSCLK_FREQ_16MHz
\r
616 * @brief Sets System clock frequency to 16MHz and configure HCLK, PCLK2
\r
617 * and PCLK1 prescalers.
\r
618 * @note This function should be used only after reset.
\r
622 static void SetSysClockTo16(void)
\r
624 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
626 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
628 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
630 /* Wait till HSE is ready and if Time out is reached exit */
\r
633 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
635 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
637 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
639 HSEStatus = (uint32_t)0x01;
\r
643 HSEStatus = (uint32_t)0x00;
\r
646 if (HSEStatus == (uint32_t)0x01)
\r
648 /* Enable 64-bit access */
\r
649 FLASH->ACR |= FLASH_ACR_ACC64;
\r
651 /* Enable Prefetch Buffer */
\r
652 FLASH->ACR |= FLASH_ACR_PRFTEN;
\r
654 /* Flash 1 wait state */
\r
655 FLASH->ACR |= FLASH_ACR_LATENCY;
\r
657 /* Enable the PWR APB1 Clock */
\r
658 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
\r
660 /* Select the Voltage Range 2 (1.5V) */
\r
661 PWR->CR = PWR_CR_VOS_1;
\r
663 /* Wait Until the Voltage Regulator is ready */
\r
664 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
\r
668 /* HCLK = SYSCLK */
\r
669 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;
\r
672 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
675 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
\r
677 /* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */
\r
678 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
\r
680 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
\r
683 RCC->CR |= RCC_CR_PLLON;
\r
685 /* Wait till PLL is ready */
\r
686 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
690 /* Select PLL as system clock source */
\r
691 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
692 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
694 /* Wait till PLL is used as system clock source */
\r
695 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)
\r
701 /* If HSE fails to start-up, the application will have wrong clock
\r
702 configuration. User can add here some code to deal with this error */
\r
706 #elif defined SYSCLK_FREQ_32MHz
\r
708 * @brief Sets System clock frequency to 32MHz and configure HCLK, PCLK2
\r
709 * and PCLK1 prescalers.
\r
710 * @note This function should be used only after reset.
\r
714 static void SetSysClockTo32(void)
\r
716 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
718 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
720 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
722 /* Wait till HSE is ready and if Time out is reached exit */
\r
725 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
727 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
729 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
731 HSEStatus = (uint32_t)0x01;
\r
735 HSEStatus = (uint32_t)0x00;
\r
738 if (HSEStatus == (uint32_t)0x01)
\r
740 /* Enable 64-bit access */
\r
741 FLASH->ACR |= FLASH_ACR_ACC64;
\r
743 /* Enable Prefetch Buffer */
\r
744 FLASH->ACR |= FLASH_ACR_PRFTEN;
\r
746 /* Flash 1 wait state */
\r
747 FLASH->ACR |= FLASH_ACR_LATENCY;
\r
749 /* Enable the PWR APB1 Clock */
\r
750 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
\r
752 /* Select the Voltage Range 1 (1.8V) */
\r
753 PWR->CR = PWR_CR_VOS_0;
\r
755 /* Wait Until the Voltage Regulator is ready */
\r
756 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
\r
760 /* HCLK = SYSCLK */
\r
761 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
764 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
767 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
\r
769 /* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */
\r
770 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
\r
772 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
\r
775 RCC->CR |= RCC_CR_PLLON;
\r
777 /* Wait till PLL is ready */
\r
778 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
782 /* Select PLL as system clock source */
\r
783 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
784 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
786 /* Wait till PLL is used as system clock source */
\r
787 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)
\r
793 /* If HSE fails to start-up, the application will have wrong clock
\r
794 configuration. User can add here some code to deal with this error */
\r
800 * @brief Selects MSI as System clock source and configure HCLK, PCLK2
\r
801 * and PCLK1 prescalers.
\r
802 * @note This function should be used only after reset.
\r
806 static void SetSysClockToMSI(void)
\r
808 __IO uint32_t StartUpCounter = 0, MSIStatus = 0;
\r
810 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
812 RCC->CR |= ((uint32_t)RCC_CR_MSION);
\r
814 /* Wait till MSI is ready and if Time out is reached exit */
\r
817 MSIStatus = RCC->CR & RCC_CR_MSIRDY;
\r
819 } while((MSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\r
821 if ((RCC->CR & RCC_CR_MSIRDY) != RESET)
\r
823 MSIStatus = (uint32_t)0x01;
\r
827 MSIStatus = (uint32_t)0x00;
\r
830 if (MSIStatus == (uint32_t)0x01)
\r
832 #ifdef SYSCLK_FREQ_MSI
\r
833 #ifdef SYSCLK_FREQ_MSI_4MHz
\r
834 /* Enable 64-bit access */
\r
835 FLASH->ACR |= FLASH_ACR_ACC64;
\r
837 /* Enable Prefetch Buffer */
\r
838 FLASH->ACR |= FLASH_ACR_PRFTEN;
\r
840 /* Flash 1 wait state */
\r
841 FLASH->ACR |= FLASH_ACR_LATENCY;
\r
843 /* Flash 0 wait state */
\r
844 FLASH->ACR &= ~FLASH_ACR_LATENCY;
\r
846 /* Disable Prefetch Buffer */
\r
847 FLASH->ACR &= ~FLASH_ACR_PRFTEN;
\r
849 /* Disable 64-bit access */
\r
850 FLASH->ACR &= ~FLASH_ACR_ACC64;
\r
853 /* Enable the PWR APB1 Clock */
\r
854 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
\r
856 /* Select the Voltage Range 3 (1.2V) */
\r
857 PWR->CR = PWR_CR_VOS;
\r
859 /* Wait Until the Voltage Regulator is ready */
\r
860 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
\r
864 /* HCLK = SYSCLK */
\r
865 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
868 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
871 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
\r
873 #ifdef SYSCLK_FREQ_MSI
\r
874 #ifdef SYSCLK_FREQ_MSI_64KHz
\r
875 /* Set MSI clock range */
\r
876 RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
\r
877 RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_64KHz;
\r
878 #elif defined SYSCLK_FREQ_MSI_128KHz
\r
879 /* Set MSI clock range */
\r
880 RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
\r
881 RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_128KHz;
\r
882 #elif defined SYSCLK_FREQ_MSI_256KHz
\r
883 /* Set MSI clock range */
\r
884 RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
\r
885 RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_256KHz;
\r
886 #elif defined SYSCLK_FREQ_MSI_512KHz
\r
887 /* Set MSI clock range */
\r
888 RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
\r
889 RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_512KHz;
\r
890 #elif defined SYSCLK_FREQ_MSI_1MHz
\r
891 /* Set MSI clock range */
\r
892 RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
\r
893 RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_1MHz;
\r
894 #elif defined SYSCLK_FREQ_MSI_2MHz
\r
895 /* Set MSI clock range */
\r
896 RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
\r
897 RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_2MHz;
\r
898 #elif defined SYSCLK_FREQ_MSI_4MHz
\r
899 /* Set MSI clock range */
\r
900 RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
\r
901 RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_4MHz;
\r
905 /* Select MSI as system clock source */
\r
906 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
907 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_MSI;
\r
909 /* Wait till MSI is used as system clock source */
\r
910 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x00)
\r
916 /* If MSI fails to start-up, the application will have wrong clock
\r
917 configuration. User can add here some code to deal with this error */
\r
934 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r