1 /** ###################################################################
\r
2 ** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
\r
4 ** Project : RTOSDemo
\r
5 ** Processor : MC9S12DP256BCPV
\r
6 ** Beantype : MC9S12DP256_112
\r
7 ** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283
\r
8 ** Compiler : Metrowerks HC12 C Compiler
\r
9 ** Date/Time : 16/06/2005, 19:18
\r
11 ** This bean "MC9S12DP256_112" implements properties, methods,
\r
12 ** and events of the CPU.
\r
16 ** EnableInt - void Cpu_EnableInt(void);
\r
17 ** DisableInt - void Cpu_DisableInt(void);
\r
19 ** (c) Copyright UNIS, spol. s r.o. 1997-2002
\r
20 ** UNIS, spol. s r.o.
\r
24 ** http : www.processorexpert.com
\r
25 ** mail : info@processorexpert.com
\r
26 ** ###################################################################*/
\r
30 #include "TickTimer.h"
\r
33 extern void near _EntryPoint(void); /* Startup routine */
\r
34 extern void near vPortTickInterrupt( void );
\r
35 extern void near vPortYield( void );
\r
36 extern void near vCOM0_ISR( void );
\r
38 typedef void (*near tIsrFunc)(void);
\r
39 const tIsrFunc _vect[] @0xFF80 = { /* Interrupt table */
\r
40 Cpu_Interrupt, /* 0 Default (unused) interrupt */
\r
41 Cpu_Interrupt, /* 1 Default (unused) interrupt */
\r
42 Cpu_Interrupt, /* 2 Default (unused) interrupt */
\r
43 Cpu_Interrupt, /* 3 Default (unused) interrupt */
\r
44 Cpu_Interrupt, /* 4 Default (unused) interrupt */
\r
45 Cpu_Interrupt, /* 5 Default (unused) interrupt */
\r
46 Cpu_Interrupt, /* 6 Default (unused) interrupt */
\r
47 Cpu_Interrupt, /* 7 Default (unused) interrupt */
\r
48 Cpu_Interrupt, /* 8 Default (unused) interrupt */
\r
49 Cpu_Interrupt, /* 9 Default (unused) interrupt */
\r
50 Cpu_Interrupt, /* 10 Default (unused) interrupt */
\r
51 Cpu_Interrupt, /* 11 Default (unused) interrupt */
\r
52 Cpu_Interrupt, /* 12 Default (unused) interrupt */
\r
53 Cpu_Interrupt, /* 13 Default (unused) interrupt */
\r
54 Cpu_Interrupt, /* 14 Default (unused) interrupt */
\r
55 Cpu_Interrupt, /* 15 Default (unused) interrupt */
\r
56 Cpu_Interrupt, /* 16 Default (unused) interrupt */
\r
57 Cpu_Interrupt, /* 17 Default (unused) interrupt */
\r
58 Cpu_Interrupt, /* 18 Default (unused) interrupt */
\r
59 Cpu_Interrupt, /* 19 Default (unused) interrupt */
\r
60 Cpu_Interrupt, /* 20 Default (unused) interrupt */
\r
61 Cpu_Interrupt, /* 21 Default (unused) interrupt */
\r
62 Cpu_Interrupt, /* 22 Default (unused) interrupt */
\r
63 Cpu_Interrupt, /* 23 Default (unused) interrupt */
\r
64 Cpu_Interrupt, /* 24 Default (unused) interrupt */
\r
65 Cpu_Interrupt, /* 25 Default (unused) interrupt */
\r
66 Cpu_Interrupt, /* 26 Default (unused) interrupt */
\r
67 Cpu_Interrupt, /* 27 Default (unused) interrupt */
\r
68 Cpu_Interrupt, /* 28 Default (unused) interrupt */
\r
69 Cpu_Interrupt, /* 29 Default (unused) interrupt */
\r
70 Cpu_Interrupt, /* 30 Default (unused) interrupt */
\r
71 Cpu_Interrupt, /* 31 Default (unused) interrupt */
\r
72 Cpu_Interrupt, /* 32 Default (unused) interrupt */
\r
73 Cpu_Interrupt, /* 33 Default (unused) interrupt */
\r
74 Cpu_Interrupt, /* 34 Default (unused) interrupt */
\r
75 Cpu_Interrupt, /* 35 Default (unused) interrupt */
\r
76 Cpu_Interrupt, /* 36 Default (unused) interrupt */
\r
77 Cpu_Interrupt, /* 37 Default (unused) interrupt */
\r
78 Cpu_Interrupt, /* 38 Default (unused) interrupt */
\r
79 Cpu_Interrupt, /* 39 Default (unused) interrupt */
\r
80 Cpu_Interrupt, /* 40 Default (unused) interrupt */
\r
81 Cpu_Interrupt, /* 41 Default (unused) interrupt */
\r
82 Cpu_Interrupt, /* 42 Default (unused) interrupt */
\r
84 Cpu_Interrupt, /* 44 Default (unused) interrupt */
\r
85 Cpu_Interrupt, /* 45 Default (unused) interrupt */
\r
86 Cpu_Interrupt, /* 46 Default (unused) interrupt */
\r
87 Cpu_Interrupt, /* 47 Default (unused) interrupt */
\r
88 Cpu_Interrupt, /* 48 Default (unused) interrupt */
\r
89 Cpu_Interrupt, /* 49 Default (unused) interrupt */
\r
90 Cpu_Interrupt, /* 50 Default (unused) interrupt */
\r
91 Cpu_Interrupt, /* 51 Default (unused) interrupt */
\r
92 Cpu_Interrupt, /* 52 Default (unused) interrupt */
\r
93 Cpu_Interrupt, /* 53 Default (unused) interrupt */
\r
94 Cpu_Interrupt, /* 54 Default (unused) interrupt */
\r
96 Cpu_Interrupt, /* 56 Default (unused) interrupt */
\r
97 Cpu_Interrupt, /* 57 Default (unused) interrupt */
\r
98 Cpu_Interrupt, /* 58 Default (unused) interrupt */
\r
99 vPortYield, /* 59 Default (unused) interrupt */
\r
100 Cpu_Interrupt, /* 60 Default (unused) interrupt */
\r
101 Cpu_Interrupt, /* 61 Default (unused) interrupt */
\r
102 Cpu_Interrupt, /* 62 Default (unused) interrupt */
\r
103 _EntryPoint /* Reset vector */
\r
106 ** ###################################################################
\r
108 ** This file was created by UNIS Processor Expert 03.33 for
\r
109 ** the Motorola HCS12 series of microcontrollers.
\r
111 ** ###################################################################
\r