1 /** ###################################################################
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2 ** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
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4 ** Project : RTOSDemo
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5 ** Processor : MC9S12DP256BCPV
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6 ** Beantype : MC9S12DP256_112
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7 ** Version : Bean 01.148, Driver 01.09, CPU db: 2.87.283
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8 ** Compiler : Metrowerks HC12 C Compiler
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9 ** Date/Time : 18/06/2005, 16:21
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11 ** This bean "MC9S12DP256_112" implements properties, methods,
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12 ** and events of the CPU.
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16 ** EnableInt - void Cpu_EnableInt(void);
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17 ** DisableInt - void Cpu_DisableInt(void);
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19 ** (c) Copyright UNIS, spol. s r.o. 1997-2002
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20 ** UNIS, spol. s r.o.
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24 ** http : www.processorexpert.com
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25 ** mail : info@processorexpert.com
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26 ** ###################################################################*/
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30 #include "TickTimer.h"
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33 #include "PE_Types.h"
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34 #include "PE_Error.h"
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35 #include "PE_Const.h"
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37 #include "PE_Timer.h"
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41 #define CGM_DELAY 3071UL
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44 /* Global variables */
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45 volatile byte CCR_reg; /* Current CCR reegister */
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46 byte CpuMode = HIGH_SPEED; /* Current speed mode */
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50 ** ===================================================================
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51 ** Method : Cpu_Interrupt (bean MC9S12DP256_112)
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54 ** This method is internal. It is used by Processor Expert
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56 ** ===================================================================
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58 #pragma CODE_SEG __NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */
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60 __interrupt void Cpu_Interrupt(void)
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64 #pragma CODE_SEG DEFAULT /* Change code section to DEFAULT. */
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67 ** ===================================================================
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68 ** Method : Cpu_DisableInt (bean MC9S12DP256_112)
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71 ** Disable maskable interrupts
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72 ** Parameters : None
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73 ** Returns : Nothing
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74 ** ===================================================================
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77 void Cpu_DisableInt(void)
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79 ** This method is implemented as macro in the header module. **
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83 ** ===================================================================
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84 ** Method : Cpu_EnableInt (bean MC9S12DP256_112)
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87 ** Enable maskable interrupts
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88 ** Parameters : None
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89 ** Returns : Nothing
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90 ** ===================================================================
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93 void Cpu_EnableInt(void)
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95 ** This method is implemented as macro in the header module. **
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99 ** ===================================================================
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100 ** Method : _EntryPoint (bean MC9S12DP256_112)
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103 ** This method is internal. It is used by Processor Expert
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105 ** ===================================================================
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107 extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */
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108 #define INITRG_ADR 0x0011 /* Register map position register */
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111 void _EntryPoint(void)
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113 /*** ### MC9S12DP256_112 "Cpu" init code ... ***/
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114 /*** PE initialization code after reset ***/
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115 /* Initialization of the registers INITRG, INITRM, INITEE is done to protect them to be written accidentally later by the application */
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116 *(byte*)INITRG_ADR = 0; /* Set the register map position */
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117 asm nop; /* nop instruction */
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118 INITRM=1; /* Set the RAM map position */
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119 INITEE=1; /* Set the EEPROM map position */
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120 /* MISC: ??=0,??=0,??=0,??=0,EXSTR1=0,EXSTR0=0,ROMHM=0,ROMON=1 */
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122 /* System clock initialization */
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124 CLKSEL_PLLSEL = 0; /* Select clock source from XTAL */
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125 PLLCTL_PLLON = 0; /* Disable the PLL */
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126 SYNR = 24; /* Set the multiplier register */
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127 REFDV = 15; /* Set the divider register */
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129 PLLCTL_PLLON = 1; /* Enable the PLL */
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130 while(!CRGFLG_LOCK); /* Wait */
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131 CLKSEL_PLLSEL = 1; /* Select clock source from PLL */
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132 /*** End of PE initialization code after reset ***/
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134 __asm jmp _Startup; /* Jump to C startup code */
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138 ** ===================================================================
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139 ** Method : PE_low_level_init (bean MC9S12DP256_112)
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142 ** This method is internal. It is used by Processor Expert
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144 ** ===================================================================
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146 void PE_low_level_init(void)
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148 /* Common initialization of the CPU registers */
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149 /* TSCR1: TEN=0,TSWAI=0,TSFRZ=1 */
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150 output( TSCR1, input( TSCR1 ) & ~192 | 32 );
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151 /* TCTL2: OM0=0,OL0=0 */
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152 output( TCTL2, input( TCTL2 ) & ~3 );
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153 /* TCTL1: OM7=0,OL7=0 */
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154 output( TCTL1, input( TCTL1 ) & ~192 );
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156 output( TIE, input( TIE ) & ~1 );
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158 output( TTOV, input( TTOV ) & ~1 );
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159 /* TSCR2: TOI=0,TCRE=1 */
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160 output( TSCR2, input( TSCR2 ) & ~128 | 8 );
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161 /* TIOS: IOS7=1,IOS0=1 */
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162 output( TIOS, input( TIOS ) | 129 );
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163 /* PWMCTL: PSWAI=0,PFRZ=0 */
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164 output( PWMCTL, input( PWMCTL ) & ~12 );
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165 /* PWMSDN: PWMIF=0,PWMIE=0,PWMRSTRT=0,PWMLVL=0,??=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */
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166 output( PWMSDN, 0 );
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167 /* ICSYS: SH37=0,SH26=0,SH15=0,SH04=0,TFMOD=0,PACMX=0,BUFEN=0,LATQ=0 */
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168 output( ICSYS, 0 );
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169 /* MCCTL: MODMC=1 */
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170 output( MCCTL, input( MCCTL ) | 64 );
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171 /* ### MC9S12DP256_112 "Cpu" init code ... */
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172 /* ### TimerInt "TickTimer" init code ... */
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174 /* ### ByteIO "Byte1" init code ... */
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175 PORTB = 255; /* Prepare value for output */
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176 DDRB = 255; /* Set direction to output */
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177 /* ### Asynchro serial "COM0" init code ... */
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182 /* Common peripheral initialization - ENABLE */
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184 output( TSCR1, input( TSCR1 ) | 128 );
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185 INTCR_IRQEN = 0; /* Disable the IRQ interrupt. IRQ interrupt is enabled after CPU reset by default. */
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186 __DI(); /* Disable interrupts */
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192 ** ###################################################################
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194 ** This file was created by UNIS Processor Expert 03.33 for
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195 ** the Motorola HCS12 series of microcontrollers.
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197 ** ###################################################################
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