1 /** ###################################################################
\r
2 ** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
\r
3 ** Filename : IO_Map.C
\r
4 ** Project : RTOSDemo
\r
5 ** Processor : MC9S12C32CFU
\r
7 ** Version : Driver 01.01
\r
8 ** Compiler : Metrowerks HC12 C Compiler
\r
9 ** Date/Time : 10/05/2005, 11:11
\r
11 ** This bean "IO_Map" implements an IO devices mapping.
\r
15 ** No public methods
\r
17 ** (c) Copyright UNIS, spol. s r.o. 1997-2002
\r
18 ** UNIS, spol. s r.o.
\r
22 ** http : www.processorexpert.com
\r
23 ** mail : info@processorexpert.com
\r
24 ** ###################################################################*/
\r
25 /* Based on CPU DB MC9S12C32_80, version 2.87.264 */
\r
26 #include "PE_types.h"
\r
29 volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register */
\r
30 volatile ATDDIENSTR _ATDDIEN; /* ATD Input Enable Mask Register */
\r
31 volatile ATDSTAT0STR _ATDSTAT0; /* A/D Status Register 0 */
\r
32 volatile ATDSTAT1STR _ATDSTAT1; /* A/D Status Register 1 */
\r
33 volatile BDMCCRSTR _BDMCCR; /* BDM CCR Holding Register */
\r
34 volatile BDMINRSTR _BDMINR; /* BDM Internal Register Position Register */
\r
35 volatile BDMSTSSTR _BDMSTS; /* BDM Status Register */
\r
36 volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register */
\r
37 volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register */
\r
38 volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register */
\r
39 volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register */
\r
40 volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register */
\r
41 volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register */
\r
42 volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0 */
\r
43 volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1 */
\r
44 volatile CANBTR0STR _CANBTR0; /* MSCAN Bus Timing Register 0 */
\r
45 volatile CANBTR1STR _CANBTR1; /* MSCAN Bus Timing Register 1 */
\r
46 volatile CANCTL0STR _CANCTL0; /* MSCAN Control 0 Register */
\r
47 volatile CANCTL1STR _CANCTL1; /* MSCAN Control 1 Register */
\r
48 volatile CANIDACSTR _CANIDAC; /* MSCAN Identifier Acceptance Control Register */
\r
49 volatile CANIDAR0STR _CANIDAR0; /* MSCAN Identifier Acceptance Register 0 */
\r
50 volatile CANIDAR1STR _CANIDAR1; /* MSCAN Identifier Acceptance Register 1 */
\r
51 volatile CANIDAR2STR _CANIDAR2; /* MSCAN Identifier Acceptance Register 2 */
\r
52 volatile CANIDAR3STR _CANIDAR3; /* MSCAN Identifier Acceptance Register 3 */
\r
53 volatile CANIDAR4STR _CANIDAR4; /* MSCAN Identifier Acceptance Register 4 */
\r
54 volatile CANIDAR5STR _CANIDAR5; /* MSCAN Identifier Acceptance Register 5 */
\r
55 volatile CANIDAR6STR _CANIDAR6; /* MSCAN Identifier Acceptance Register 6 */
\r
56 volatile CANIDAR7STR _CANIDAR7; /* MSCAN Identifier Acceptance Register 7 */
\r
57 volatile CANIDMR0STR _CANIDMR0; /* MSCAN Identifier Mask Register 0 */
\r
58 volatile CANIDMR1STR _CANIDMR1; /* MSCAN Identifier Mask Register 1 */
\r
59 volatile CANIDMR2STR _CANIDMR2; /* MSCAN Identifier Mask Register 2 */
\r
60 volatile CANIDMR3STR _CANIDMR3; /* MSCAN Identifier Mask Register 3 */
\r
61 volatile CANIDMR4STR _CANIDMR4; /* MSCAN Identifier Mask Register 4 */
\r
62 volatile CANIDMR5STR _CANIDMR5; /* MSCAN Identifier Mask Register 5 */
\r
63 volatile CANIDMR6STR _CANIDMR6; /* MSCAN Identifier Mask Register 6 */
\r
64 volatile CANIDMR7STR _CANIDMR7; /* MSCAN Identifier Mask Register 7 */
\r
65 volatile CANRFLGSTR _CANRFLG; /* MSCAN Receiver Flag Register */
\r
66 volatile CANRIERSTR _CANRIER; /* MSCAN Receiver Interrupt Enable Register */
\r
67 volatile CANRXDLRSTR _CANRXDLR; /* MSCAN Receive Data Length Register */
\r
68 volatile CANRXDSR0STR _CANRXDSR0; /* MSCAN Receive Data Segment Register 0 */
\r
69 volatile CANRXDSR1STR _CANRXDSR1; /* MSCAN Receive Data Segment Register 1 */
\r
70 volatile CANRXDSR2STR _CANRXDSR2; /* MSCAN Receive Data Segment Register 2 */
\r
71 volatile CANRXDSR3STR _CANRXDSR3; /* MSCAN Receive Data Segment Register 3 */
\r
72 volatile CANRXDSR4STR _CANRXDSR4; /* MSCAN Receive Data Segment Register 4 */
\r
73 volatile CANRXDSR5STR _CANRXDSR5; /* MSCAN Receive Data Segment Register 5 */
\r
74 volatile CANRXDSR6STR _CANRXDSR6; /* MSCAN Receive Data Segment Register 6 */
\r
75 volatile CANRXDSR7STR _CANRXDSR7; /* MSCAN Receive Data Segment Register 7 */
\r
76 volatile CANRXERRSTR _CANRXERR; /* MSCAN Receive Error Counter Register */
\r
77 volatile CANRXIDR0STR _CANRXIDR0; /* MSCAN Receive Identifier Register 0 */
\r
78 volatile CANRXIDR1STR _CANRXIDR1; /* MSCAN Receive Identifier Register 1 */
\r
79 volatile CANRXIDR2STR _CANRXIDR2; /* MSCAN Receive Identifier Register 2 */
\r
80 volatile CANRXIDR3STR _CANRXIDR3; /* MSCAN Receive Identifier Register 3 */
\r
81 volatile CANTAAKSTR _CANTAAK; /* MSCAN Transmitter Message Abort Control */
\r
82 volatile CANTARQSTR _CANTARQ; /* MSCAN Transmitter Message Abort Request */
\r
83 volatile CANTBSELSTR _CANTBSEL; /* MSCAN Transmit Buffer Selection */
\r
84 volatile CANTFLGSTR _CANTFLG; /* MSCAN Transmitter Flag Register */
\r
85 volatile CANTIERSTR _CANTIER; /* MSCAN Transmitter Interrupt Enable Register */
\r
86 volatile CANTXDLRSTR _CANTXDLR; /* MSCAN Transmit Data Length Register */
\r
87 volatile CANTXDSR0STR _CANTXDSR0; /* MSCAN Transmit Data Segment Register 0 */
\r
88 volatile CANTXDSR1STR _CANTXDSR1; /* MSCAN Transmit Data Segment Register 1 */
\r
89 volatile CANTXDSR2STR _CANTXDSR2; /* MSCAN Transmit Data Segment Register 2 */
\r
90 volatile CANTXDSR3STR _CANTXDSR3; /* MSCAN Transmit Data Segment Register 3 */
\r
91 volatile CANTXDSR4STR _CANTXDSR4; /* MSCAN Transmit Data Segment Register 4 */
\r
92 volatile CANTXDSR5STR _CANTXDSR5; /* MSCAN Transmit Data Segment Register 5 */
\r
93 volatile CANTXDSR6STR _CANTXDSR6; /* MSCAN Transmit Data Segment Register 6 */
\r
94 volatile CANTXDSR7STR _CANTXDSR7; /* MSCAN Transmit Data Segment Register 7 */
\r
95 volatile CANTXERRSTR _CANTXERR; /* MSCAN Transmit Error Counter Register */
\r
96 volatile CANTXIDR0STR _CANTXIDR0; /* MSCAN Transmit Identifier Register 0 */
\r
97 volatile CANTXIDR1STR _CANTXIDR1; /* MSCAN Transmit Identifier Register 1 */
\r
98 volatile CANTXIDR2STR _CANTXIDR2; /* MSCAN Transmit Identifier Register 2 */
\r
99 volatile CANTXIDR3STR _CANTXIDR3; /* MSCAN Transmit Identifier Register 3 */
\r
100 volatile CANTXTBPRSTR _CANTXTBPR; /* MSCAN Transmit Buffer Priority */
\r
101 volatile CFORCSTR _CFORC; /* Timer Compare Force Register */
\r
102 volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register */
\r
103 volatile COPCTLSTR _COPCTL; /* CRG COP Control Register */
\r
104 volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register */
\r
105 volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register */
\r
106 volatile CTCTLSTR _CTCTL; /* CRG Test Control Register */
\r
107 volatile CTFLGSTR _CTFLG; /* CRG Test Flags Register */
\r
108 volatile DDRADSTR _DDRAD; /* Port AD Data Direction Register */
\r
109 volatile DDRESTR _DDRE; /* Port E Data Direction Register */
\r
110 volatile DDRJSTR _DDRJ; /* Port J Data Direction Register */
\r
111 volatile DDRKSTR _DDRK; /* Port K Data Direction Register */
\r
112 volatile DDRMSTR _DDRM; /* Port M Data Direction Register */
\r
113 volatile DDRPSTR _DDRP; /* Port P Data Direction Register */
\r
114 volatile DDRSSTR _DDRS; /* Port S Data Direction Register */
\r
115 volatile DDRTSTR _DDRT; /* Port T Data Direction Register */
\r
116 volatile EBICTLSTR _EBICTL; /* External Bus Interface Control */
\r
117 volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register */
\r
118 volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register */
\r
119 volatile FCNFGSTR _FCNFG; /* Flash Configuration Register */
\r
120 volatile FPROTSTR _FPROT; /* Flash Protection Register */
\r
121 volatile FSECSTR _FSEC; /* Flash Security Register */
\r
122 volatile FSTATSTR _FSTAT; /* Flash Status Register */
\r
123 volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt */
\r
124 volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register */
\r
125 volatile INITRGSTR _INITRG; /* Initialization of Internal Register Position Register */
\r
126 volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register */
\r
127 volatile INTCRSTR _INTCR; /* Interrupt Control Register */
\r
128 volatile ITCRSTR _ITCR; /* Interrupt Test Control Register */
\r
129 volatile ITESTSTR _ITEST; /* Interrupt Test Register */
\r
130 volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero */
\r
131 volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One */
\r
132 volatile MISCSTR _MISC; /* Miscellaneous Mapping Control Register */
\r
133 volatile MODESTR _MODE; /* Mode Register */
\r
134 volatile MODRRSTR _MODRR; /* Module Routing Register */
\r
135 volatile MTST0STR _MTST0; /* MTST0 */
\r
136 volatile MTST1STR _MTST1; /* MTST1 */
\r
137 volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register */
\r
138 volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register */
\r
139 volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register */
\r
140 volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register */
\r
141 volatile PARTIDHSTR _PARTIDH; /* Part ID Register High */
\r
142 volatile PARTIDLSTR _PARTIDL; /* Part ID Register Low */
\r
143 volatile PEARSTR _PEAR; /* Port E Assignment Register */
\r
144 volatile PERADSTR _PERAD; /* Port AD Pull Device Enable Register */
\r
145 volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register */
\r
146 volatile PERMSTR _PERM; /* Port M Pull Device Enable Register */
\r
147 volatile PERPSTR _PERP; /* Port P Pull Device Enable Register */
\r
148 volatile PERSSTR _PERS; /* Port S Pull Device Enable Register */
\r
149 volatile PERTSTR _PERT; /* Port T Pull Device Enable Register */
\r
150 volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register */
\r
151 volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register */
\r
152 volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register */
\r
153 volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register */
\r
154 volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register */
\r
155 volatile PORTAD0STR _PORTAD0; /* Port AD0 Register */
\r
156 volatile PORTESTR _PORTE; /* Port E Register */
\r
157 volatile PORTKSTR _PORTK; /* Port K Data Register */
\r
158 volatile PPAGESTR _PPAGE; /* Page Index Register */
\r
159 volatile PPSADSTR _PPSAD; /* Port AD Polarity Select Register */
\r
160 volatile PPSJSTR _PPSJ; /* PortJP Polarity Select Register */
\r
161 volatile PPSMSTR _PPSM; /* Port M Polarity Select Register */
\r
162 volatile PPSPSTR _PPSP; /* Port P Polarity Select Register */
\r
163 volatile PPSSSTR _PPSS; /* Port S Polarity Select Register */
\r
164 volatile PPSTSTR _PPST; /* Port T Polarity Select Register */
\r
165 volatile PTADSTR _PTAD; /* Port AD I/O Register */
\r
166 volatile PTIADSTR _PTIAD; /* Port AD Input Register */
\r
167 volatile PTIJSTR _PTIJ; /* Port J Input Register */
\r
168 volatile PTIMSTR _PTIM; /* Port M Input */
\r
169 volatile PTIPSTR _PTIP; /* Port P Input */
\r
170 volatile PTISSTR _PTIS; /* Port S Input */
\r
171 volatile PTITSTR _PTIT; /* Port T Input */
\r
172 volatile PTJSTR _PTJ; /* Port J I/O Register */
\r
173 volatile PTMSTR _PTM; /* Port M I/O Register */
\r
174 volatile PTPSTR _PTP; /* Port P I/O Register */
\r
175 volatile PTSSTR _PTS; /* Port S I/O Register */
\r
176 volatile PTTSTR _PTT; /* Port T I/O Register */
\r
177 volatile PUCRSTR _PUCR; /* Pull-Up Control Register */
\r
178 volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register */
\r
179 volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register */
\r
180 volatile PWMCTLSTR _PWMCTL; /* PWM Control Register */
\r
181 volatile PWMESTR _PWME; /* PWM Enable Register */
\r
182 volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register */
\r
183 volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register */
\r
184 volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register */
\r
185 volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register */
\r
186 volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register */
\r
187 volatile RDRADSTR _RDRAD; /* Port AD Reduced Drive Register */
\r
188 volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines */
\r
189 volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register */
\r
190 volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register */
\r
191 volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register */
\r
192 volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register */
\r
193 volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register */
\r
194 volatile REFDVSTR _REFDV; /* CRG Reference Divider Register */
\r
195 volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register */
\r
196 volatile SCICR1STR _SCICR1; /* SCI Control Register 1 */
\r
197 volatile SCICR2STR _SCICR2; /* SCI Control Register 2 */
\r
198 volatile SCIDRHSTR _SCIDRH; /* SCI Data Register High */
\r
199 volatile SCIDRLSTR _SCIDRL; /* SCI Data Register Low */
\r
200 volatile SCISR1STR _SCISR1; /* SCI Status Register 1 */
\r
201 volatile SCISR2STR _SCISR2; /* SCI Status Register 2 */
\r
202 volatile SPIBRSTR _SPIBR; /* SPI Baud Rate Register */
\r
203 volatile SPICR1STR _SPICR1; /* SPI Control Register */
\r
204 volatile SPICR2STR _SPICR2; /* SPI Control Register 2 */
\r
205 volatile SPIDRSTR _SPIDR; /* SPI Data Register */
\r
206 volatile SPISRSTR _SPISR; /* SPI Status Register */
\r
207 volatile SYNRSTR _SYNR; /* CRG Synthesizer Register */
\r
208 volatile TCTL1STR _TCTL1; /* Timer Control Register 1 */
\r
209 volatile TCTL2STR _TCTL2; /* Timer Control Register 2 */
\r
210 volatile TCTL3STR _TCTL3; /* Timer Control Register 3 */
\r
211 volatile TCTL4STR _TCTL4; /* Timer Control Register 4 */
\r
212 volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1 */
\r
213 volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2 */
\r
214 volatile TIESTR _TIE; /* Timer Interrupt Enable Register */
\r
215 volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select */
\r
216 volatile TSCR1STR _TSCR1; /* Timer System Control Register1 */
\r
217 volatile TSCR2STR _TSCR2; /* Timer System Control Register 2 */
\r
218 volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register */
\r
219 volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register */
\r
220 volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register */
\r
221 volatile ATDCTL23STR _ATDCTL23; /* ATD Control Register 23 */
\r
222 volatile ATDCTL45STR _ATDCTL45; /* ATD Control Register 45 */
\r
223 volatile ATDDR0STR _ATDDR0; /* A/D Conversion Result Register 0 */
\r
224 volatile ATDDR1STR _ATDDR1; /* A/D Conversion Result Register 1 */
\r
225 volatile ATDDR2STR _ATDDR2; /* A/D Conversion Result Register 2 */
\r
226 volatile ATDDR3STR _ATDDR3; /* A/D Conversion Result Register 3 */
\r
227 volatile ATDDR4STR _ATDDR4; /* A/D Conversion Result Register 4 */
\r
228 volatile ATDDR5STR _ATDDR5; /* A/D Conversion Result Register 5 */
\r
229 volatile ATDDR6STR _ATDDR6; /* A/D Conversion Result Register 6 */
\r
230 volatile ATDDR7STR _ATDDR7; /* A/D Conversion Result Register 7 */
\r
231 volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register */
\r
232 volatile PACNTSTR _PACNT; /* Pulse Accumulators Count Register */
\r
233 volatile PORTABSTR _PORTAB; /* Port AB Register */
\r
234 volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register */
\r
235 volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register */
\r
236 volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register */
\r
237 volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register */
\r
238 volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register */
\r
239 volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register */
\r
240 volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register */
\r
241 volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register */
\r
242 volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register */
\r
243 volatile SCIBDSTR _SCIBD; /* SCI Baud Rate Register */
\r
244 volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0 */
\r
245 volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1 */
\r
246 volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2 */
\r
247 volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3 */
\r
248 volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4 */
\r
249 volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5 */
\r
250 volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6 */
\r
251 volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7 */
\r
252 volatile TCNTSTR _TCNT; /* Timer Count Register */
\r
254 ** ###################################################################
\r
256 ** This file was created by UNIS Processor Expert 03.33 for
\r
257 ** the Motorola HCS12 series of microcontrollers.
\r
259 ** ###################################################################
\r
projects / freertos / blob