1 /** ###################################################################
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2 ** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
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3 ** Filename : IO_Map.H
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4 ** Project : RTOSDemo
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5 ** Processor : MC9S12C32CFU
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7 ** Version : Driver 01.01
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8 ** Compiler : Metrowerks HC12 C Compiler
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9 ** Date/Time : 10/05/2005, 11:11
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11 ** This bean "IO_Map" implements an IO devices mapping.
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15 ** No public methods
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17 ** (c) Copyright UNIS, spol. s r.o. 1997-2002
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18 ** UNIS, spol. s r.o.
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22 ** http : www.processorexpert.com
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23 ** mail : info@processorexpert.com
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24 ** ###################################################################*/
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26 /* Linker pragmas */
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27 #pragma LINK_INFO DERIVATIVE "MC9S12C32"
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28 #pragma LINK_INFO OSCFREQUENCY "16000000"
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31 #define REG_BASE 0x0000 /* Base address for the I/O register block */
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33 /* Based on CPU DB MC9S12C32_80, version 2.87.264 (RegistersPrg V1.027) */
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34 #ifndef _MC9S12C32_80_H
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35 #define _MC9S12C32_80_H
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37 #include "PE_Types.h"
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39 #pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */
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41 /*********************************************/
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43 /* PE I/O map format */
\r
45 /*********************************************/
\r
47 /*** PORTAB - Port AB Register; 0x00000000 ***/
\r
50 /* Overlapped registers: */
\r
52 /*** PORTA - Port A Register; 0x00000000 ***/
\r
56 byte BIT0 :1; /* Port A Bit 0 */
\r
57 byte BIT1 :1; /* Port A Bit 1 */
\r
58 byte BIT2 :1; /* Port A Bit 2 */
\r
59 byte BIT3 :1; /* Port A Bit 3 */
\r
60 byte BIT4 :1; /* Port A Bit 4 */
\r
61 byte BIT5 :1; /* Port A Bit 5 */
\r
62 byte BIT6 :1; /* Port A Bit 6 */
\r
63 byte BIT7 :1; /* Port A Bit 7 */
\r
69 #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte
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70 #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0
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71 #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1
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72 #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2
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73 #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3
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74 #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4
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75 #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5
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76 #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6
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77 #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7
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78 #define PORTA_BIT _PORTAB.Overlap_STR.PORTASTR.MergedBits.grpBIT
\r
80 /*** PORTB - Port B Register; 0x00000001 ***/
\r
84 byte BIT0 :1; /* Port B Bit 0 */
\r
85 byte BIT1 :1; /* Port B Bit 1 */
\r
86 byte BIT2 :1; /* Port B Bit 2 */
\r
87 byte BIT3 :1; /* Port B Bit 3 */
\r
88 byte BIT4 :1; /* Port B Bit 4 */
\r
89 byte BIT5 :1; /* Port B Bit 5 */
\r
90 byte BIT6 :1; /* Port B Bit 6 */
\r
91 byte BIT7 :1; /* Port B Bit 7 */
\r
97 #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte
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98 #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0
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99 #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1
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100 #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2
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101 #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3
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102 #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4
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103 #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5
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104 #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6
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105 #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7
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106 #define PORTB_BIT _PORTAB.Overlap_STR.PORTBSTR.MergedBits.grpBIT
\r
111 word BIT0 :1; /* Port AB Bit 0 */
\r
112 word BIT1 :1; /* Port AB Bit 1 */
\r
113 word BIT2 :1; /* Port AB Bit 2 */
\r
114 word BIT3 :1; /* Port AB Bit 3 */
\r
115 word BIT4 :1; /* Port AB Bit 4 */
\r
116 word BIT5 :1; /* Port AB Bit 5 */
\r
117 word BIT6 :1; /* Port AB Bit 6 */
\r
118 word BIT7 :1; /* Port AB Bit 7 */
\r
119 word BIT8 :1; /* Port AB Bit 8 */
\r
120 word BIT9 :1; /* Port AB Bit 9 */
\r
121 word BIT10 :1; /* Port AB Bit 10 */
\r
122 word BIT11 :1; /* Port AB Bit 11 */
\r
123 word BIT12 :1; /* Port AB Bit 12 */
\r
124 word BIT13 :1; /* Port AB Bit 13 */
\r
125 word BIT14 :1; /* Port AB Bit 14 */
\r
126 word BIT15 :1; /* Port AB Bit 15 */
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132 extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);
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133 #define PORTAB _PORTAB.Word
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134 #define PORTAB_BIT0 _PORTAB.Bits.BIT0
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135 #define PORTAB_BIT1 _PORTAB.Bits.BIT1
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136 #define PORTAB_BIT2 _PORTAB.Bits.BIT2
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137 #define PORTAB_BIT3 _PORTAB.Bits.BIT3
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138 #define PORTAB_BIT4 _PORTAB.Bits.BIT4
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139 #define PORTAB_BIT5 _PORTAB.Bits.BIT5
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140 #define PORTAB_BIT6 _PORTAB.Bits.BIT6
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141 #define PORTAB_BIT7 _PORTAB.Bits.BIT7
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142 #define PORTAB_BIT8 _PORTAB.Bits.BIT8
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143 #define PORTAB_BIT9 _PORTAB.Bits.BIT9
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144 #define PORTAB_BIT10 _PORTAB.Bits.BIT10
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145 #define PORTAB_BIT11 _PORTAB.Bits.BIT11
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146 #define PORTAB_BIT12 _PORTAB.Bits.BIT12
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147 #define PORTAB_BIT13 _PORTAB.Bits.BIT13
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148 #define PORTAB_BIT14 _PORTAB.Bits.BIT14
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149 #define PORTAB_BIT15 _PORTAB.Bits.BIT15
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150 #define PORTAB_BIT _PORTAB.MergedBits.grpBIT
\r
153 /*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/
\r
156 /* Overlapped registers: */
\r
158 /*** DDRA - Port A Data Direction Register; 0x00000002 ***/
\r
162 byte BIT0 :1; /* Data Direction Port A Bit 0 */
\r
163 byte BIT1 :1; /* Data Direction Port A Bit 1 */
\r
164 byte BIT2 :1; /* Data Direction Port A Bit 2 */
\r
165 byte BIT3 :1; /* Data Direction Port A Bit 3 */
\r
166 byte BIT4 :1; /* Data Direction Port A Bit 4 */
\r
167 byte BIT5 :1; /* Data Direction Port A Bit 5 */
\r
168 byte BIT6 :1; /* Data Direction Port A Bit 6 */
\r
169 byte BIT7 :1; /* Data Direction Port A Bit 7 */
\r
175 #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte
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176 #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0
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177 #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1
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178 #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2
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179 #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3
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180 #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4
\r
181 #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5
\r
182 #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6
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183 #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7
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184 #define DDRA_BIT _DDRAB.Overlap_STR.DDRASTR.MergedBits.grpBIT
\r
186 /*** DDRB - Port B Data Direction Register; 0x00000003 ***/
\r
190 byte BIT0 :1; /* Data Direction Port B Bit 0 */
\r
191 byte BIT1 :1; /* Data Direction Port B Bit 1 */
\r
192 byte BIT2 :1; /* Data Direction Port B Bit 2 */
\r
193 byte BIT3 :1; /* Data Direction Port B Bit 3 */
\r
194 byte BIT4 :1; /* Data Direction Port B Bit 4 */
\r
195 byte BIT5 :1; /* Data Direction Port B Bit 5 */
\r
196 byte BIT6 :1; /* Data Direction Port B Bit 6 */
\r
197 byte BIT7 :1; /* Data Direction Port B Bit 7 */
\r
203 #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte
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204 #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0
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205 #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1
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206 #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2
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207 #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3
\r
208 #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4
\r
209 #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5
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210 #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6
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211 #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7
\r
212 #define DDRB_BIT _DDRAB.Overlap_STR.DDRBSTR.MergedBits.grpBIT
\r
217 word BIT0 :1; /* Data Direction Port B Bit 0 */
\r
218 word BIT1 :1; /* Data Direction Port B Bit 1 */
\r
219 word BIT2 :1; /* Data Direction Port B Bit 2 */
\r
220 word BIT3 :1; /* Data Direction Port B Bit 3 */
\r
221 word BIT4 :1; /* Data Direction Port B Bit 4 */
\r
222 word BIT5 :1; /* Data Direction Port B Bit 5 */
\r
223 word BIT6 :1; /* Data Direction Port B Bit 6 */
\r
224 word BIT7 :1; /* Data Direction Port B Bit 7 */
\r
225 word BIT8 :1; /* Data Direction Port A Bit 8 */
\r
226 word BIT9 :1; /* Data Direction Port A Bit 9 */
\r
227 word BIT10 :1; /* Data Direction Port A Bit 10 */
\r
228 word BIT11 :1; /* Data Direction Port A Bit 11 */
\r
229 word BIT12 :1; /* Data Direction Port A Bit 12 */
\r
230 word BIT13 :1; /* Data Direction Port A Bit 13 */
\r
231 word BIT14 :1; /* Data Direction Port A Bit 14 */
\r
232 word BIT15 :1; /* Data Direction Port A Bit 15 */
\r
238 extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);
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239 #define DDRAB _DDRAB.Word
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240 #define DDRAB_BIT0 _DDRAB.Bits.BIT0
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241 #define DDRAB_BIT1 _DDRAB.Bits.BIT1
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242 #define DDRAB_BIT2 _DDRAB.Bits.BIT2
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243 #define DDRAB_BIT3 _DDRAB.Bits.BIT3
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244 #define DDRAB_BIT4 _DDRAB.Bits.BIT4
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245 #define DDRAB_BIT5 _DDRAB.Bits.BIT5
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246 #define DDRAB_BIT6 _DDRAB.Bits.BIT6
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247 #define DDRAB_BIT7 _DDRAB.Bits.BIT7
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248 #define DDRAB_BIT8 _DDRAB.Bits.BIT8
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249 #define DDRAB_BIT9 _DDRAB.Bits.BIT9
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250 #define DDRAB_BIT10 _DDRAB.Bits.BIT10
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251 #define DDRAB_BIT11 _DDRAB.Bits.BIT11
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252 #define DDRAB_BIT12 _DDRAB.Bits.BIT12
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253 #define DDRAB_BIT13 _DDRAB.Bits.BIT13
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254 #define DDRAB_BIT14 _DDRAB.Bits.BIT14
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255 #define DDRAB_BIT15 _DDRAB.Bits.BIT15
\r
256 #define DDRAB_BIT _DDRAB.MergedBits.grpBIT
\r
259 /*** TCNT - Timer Count Register; 0x00000044 ***/
\r
262 /* Overlapped registers: */
\r
264 /*** TCNTHi - Timer Count Register High; 0x00000044 ***/
\r
268 byte BIT15 :1; /* Timer Count Register Bit 15 */
\r
269 byte BIT14 :1; /* Timer Count Register Bit 14 */
\r
270 byte BIT13 :1; /* Timer Count Register Bit 13 */
\r
271 byte BIT12 :1; /* Timer Count Register Bit 12 */
\r
272 byte BIT11 :1; /* Timer Count Register Bit 11 */
\r
273 byte BIT10 :1; /* Timer Count Register Bit 10 */
\r
274 byte BIT9 :1; /* Timer Count Register Bit 9 */
\r
275 byte BIT8 :1; /* Timer Count Register Bit 8 */
\r
278 #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte
\r
279 #define TCNTHi_BIT15 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT15
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280 #define TCNTHi_BIT14 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT14
\r
281 #define TCNTHi_BIT13 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT13
\r
282 #define TCNTHi_BIT12 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT12
\r
283 #define TCNTHi_BIT11 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT11
\r
284 #define TCNTHi_BIT10 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT10
\r
285 #define TCNTHi_BIT9 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT9
\r
286 #define TCNTHi_BIT8 _TCNT.Overlap_STR.TCNTHiSTR.Bits.BIT8
\r
288 /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/
\r
292 byte BIT0 :1; /* Timer Count Register Bit 0 */
\r
293 byte BIT1 :1; /* Timer Count Register Bit 1 */
\r
294 byte BIT2 :1; /* Timer Count Register Bit 2 */
\r
295 byte BIT3 :1; /* Timer Count Register Bit 3 */
\r
296 byte BIT4 :1; /* Timer Count Bit Register 4 */
\r
297 byte BIT5 :1; /* Timer Count Bit Register 5 */
\r
298 byte BIT6 :1; /* Timer Count Bit Register 6 */
\r
299 byte BIT7 :1; /* Timer Count Bit Register 7 */
\r
305 #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte
\r
306 #define TCNTLo_BIT0 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT0
\r
307 #define TCNTLo_BIT1 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT1
\r
308 #define TCNTLo_BIT2 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT2
\r
309 #define TCNTLo_BIT3 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT3
\r
310 #define TCNTLo_BIT4 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT4
\r
311 #define TCNTLo_BIT5 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT5
\r
312 #define TCNTLo_BIT6 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT6
\r
313 #define TCNTLo_BIT7 _TCNT.Overlap_STR.TCNTLoSTR.Bits.BIT7
\r
314 #define TCNTLo_BIT _TCNT.Overlap_STR.TCNTLoSTR.MergedBits.grpBIT
\r
322 extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);
\r
323 #define TCNT _TCNT.Word
\r
324 #define TCNT_BIT _TCNT.MergedBits.grpBIT
\r
327 /*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/
\r
330 /* Overlapped registers: */
\r
332 /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/
\r
336 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 0 Bit 8 */
\r
337 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 0 Bit 9 */
\r
338 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 0 Bit 10 */
\r
339 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 0 Bit 11 */
\r
340 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 0 Bit 12 */
\r
341 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 0 Bit 13 */
\r
342 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 0 Bit 14 */
\r
343 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 0 Bit 15 */
\r
349 #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte
\r
350 #define TC0Hi_BIT8 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT8
\r
351 #define TC0Hi_BIT9 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT9
\r
352 #define TC0Hi_BIT10 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT10
\r
353 #define TC0Hi_BIT11 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT11
\r
354 #define TC0Hi_BIT12 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT12
\r
355 #define TC0Hi_BIT13 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT13
\r
356 #define TC0Hi_BIT14 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT14
\r
357 #define TC0Hi_BIT15 _TC0.Overlap_STR.TC0HiSTR.Bits.BIT15
\r
358 #define TC0Hi_BIT_8 _TC0.Overlap_STR.TC0HiSTR.MergedBits.grpBIT_8
\r
359 #define TC0Hi_BIT TC0Hi_BIT_8
\r
361 /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/
\r
365 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 0 Bit 0 */
\r
366 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 0 Bit 1 */
\r
367 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 0 Bit 2 */
\r
368 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 0 Bit 3 */
\r
369 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 0 Bit 4 */
\r
370 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 0 Bit 5 */
\r
371 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 0 Bit 6 */
\r
372 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 0 Bit 7 */
\r
378 #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte
\r
379 #define TC0Lo_BIT0 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT0
\r
380 #define TC0Lo_BIT1 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT1
\r
381 #define TC0Lo_BIT2 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT2
\r
382 #define TC0Lo_BIT3 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT3
\r
383 #define TC0Lo_BIT4 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT4
\r
384 #define TC0Lo_BIT5 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT5
\r
385 #define TC0Lo_BIT6 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT6
\r
386 #define TC0Lo_BIT7 _TC0.Overlap_STR.TC0LoSTR.Bits.BIT7
\r
387 #define TC0Lo_BIT _TC0.Overlap_STR.TC0LoSTR.MergedBits.grpBIT
\r
395 extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050);
\r
396 #define TC0 _TC0.Word
\r
397 #define TC0_BIT _TC0.MergedBits.grpBIT
\r
400 /*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/
\r
403 /* Overlapped registers: */
\r
405 /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/
\r
409 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 1 Bit 8 */
\r
410 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 1 Bit 9 */
\r
411 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 1 Bit 10 */
\r
412 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 1 Bit 11 */
\r
413 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 1 Bit 12 */
\r
414 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 1 Bit 13 */
\r
415 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 1 Bit 14 */
\r
416 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 1 Bit 15 */
\r
422 #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte
\r
423 #define TC1Hi_BIT8 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT8
\r
424 #define TC1Hi_BIT9 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT9
\r
425 #define TC1Hi_BIT10 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT10
\r
426 #define TC1Hi_BIT11 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT11
\r
427 #define TC1Hi_BIT12 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT12
\r
428 #define TC1Hi_BIT13 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT13
\r
429 #define TC1Hi_BIT14 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT14
\r
430 #define TC1Hi_BIT15 _TC1.Overlap_STR.TC1HiSTR.Bits.BIT15
\r
431 #define TC1Hi_BIT_8 _TC1.Overlap_STR.TC1HiSTR.MergedBits.grpBIT_8
\r
432 #define TC1Hi_BIT TC1Hi_BIT_8
\r
434 /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/
\r
438 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 1 Bit 0 */
\r
439 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 1 Bit 1 */
\r
440 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 1 Bit 2 */
\r
441 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 1 Bit 3 */
\r
442 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 1 Bit 4 */
\r
443 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 1 Bit 5 */
\r
444 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 1 Bit 6 */
\r
445 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 1 Bit 7 */
\r
451 #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte
\r
452 #define TC1Lo_BIT0 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT0
\r
453 #define TC1Lo_BIT1 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT1
\r
454 #define TC1Lo_BIT2 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT2
\r
455 #define TC1Lo_BIT3 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT3
\r
456 #define TC1Lo_BIT4 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT4
\r
457 #define TC1Lo_BIT5 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT5
\r
458 #define TC1Lo_BIT6 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT6
\r
459 #define TC1Lo_BIT7 _TC1.Overlap_STR.TC1LoSTR.Bits.BIT7
\r
460 #define TC1Lo_BIT _TC1.Overlap_STR.TC1LoSTR.MergedBits.grpBIT
\r
468 extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052);
\r
469 #define TC1 _TC1.Word
\r
470 #define TC1_BIT _TC1.MergedBits.grpBIT
\r
473 /*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/
\r
476 /* Overlapped registers: */
\r
478 /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/
\r
482 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 2 Bit 8 */
\r
483 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 2 Bit 9 */
\r
484 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 2 Bit 10 */
\r
485 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 2 Bit 11 */
\r
486 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 2 Bit 12 */
\r
487 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 2 Bit 13 */
\r
488 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 2 Bit 14 */
\r
489 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 2 Bit 15 */
\r
495 #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte
\r
496 #define TC2Hi_BIT8 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT8
\r
497 #define TC2Hi_BIT9 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT9
\r
498 #define TC2Hi_BIT10 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT10
\r
499 #define TC2Hi_BIT11 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT11
\r
500 #define TC2Hi_BIT12 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT12
\r
501 #define TC2Hi_BIT13 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT13
\r
502 #define TC2Hi_BIT14 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT14
\r
503 #define TC2Hi_BIT15 _TC2.Overlap_STR.TC2HiSTR.Bits.BIT15
\r
504 #define TC2Hi_BIT_8 _TC2.Overlap_STR.TC2HiSTR.MergedBits.grpBIT_8
\r
505 #define TC2Hi_BIT TC2Hi_BIT_8
\r
507 /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/
\r
511 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 2 Bit 0 */
\r
512 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 2 Bit 1 */
\r
513 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 2 Bit 2 */
\r
514 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 2 Bit 3 */
\r
515 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 2 Bit 4 */
\r
516 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 2 Bit 5 */
\r
517 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 2 Bit 6 */
\r
518 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 2 Bit 7 */
\r
524 #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte
\r
525 #define TC2Lo_BIT0 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT0
\r
526 #define TC2Lo_BIT1 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT1
\r
527 #define TC2Lo_BIT2 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT2
\r
528 #define TC2Lo_BIT3 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT3
\r
529 #define TC2Lo_BIT4 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT4
\r
530 #define TC2Lo_BIT5 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT5
\r
531 #define TC2Lo_BIT6 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT6
\r
532 #define TC2Lo_BIT7 _TC2.Overlap_STR.TC2LoSTR.Bits.BIT7
\r
533 #define TC2Lo_BIT _TC2.Overlap_STR.TC2LoSTR.MergedBits.grpBIT
\r
541 extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054);
\r
542 #define TC2 _TC2.Word
\r
543 #define TC2_BIT _TC2.MergedBits.grpBIT
\r
546 /*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/
\r
549 /* Overlapped registers: */
\r
551 /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/
\r
555 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 3 Bit 8 */
\r
556 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 3 Bit 9 */
\r
557 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 3 Bit 10 */
\r
558 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 3 Bit 11 */
\r
559 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 3 Bit 12 */
\r
560 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 3 Bit 13 */
\r
561 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 3 Bit 14 */
\r
562 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 3 Bit 15 */
\r
568 #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte
\r
569 #define TC3Hi_BIT8 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT8
\r
570 #define TC3Hi_BIT9 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT9
\r
571 #define TC3Hi_BIT10 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT10
\r
572 #define TC3Hi_BIT11 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT11
\r
573 #define TC3Hi_BIT12 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT12
\r
574 #define TC3Hi_BIT13 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT13
\r
575 #define TC3Hi_BIT14 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT14
\r
576 #define TC3Hi_BIT15 _TC3.Overlap_STR.TC3HiSTR.Bits.BIT15
\r
577 #define TC3Hi_BIT_8 _TC3.Overlap_STR.TC3HiSTR.MergedBits.grpBIT_8
\r
578 #define TC3Hi_BIT TC3Hi_BIT_8
\r
580 /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/
\r
584 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 3 Bit 0 */
\r
585 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 3 Bit 1 */
\r
586 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 3 Bit 2 */
\r
587 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 3 Bit 3 */
\r
588 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 3 Bit 4 */
\r
589 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 3 Bit 5 */
\r
590 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 3 Bit 6 */
\r
591 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 3 Bit 7 */
\r
597 #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte
\r
598 #define TC3Lo_BIT0 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT0
\r
599 #define TC3Lo_BIT1 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT1
\r
600 #define TC3Lo_BIT2 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT2
\r
601 #define TC3Lo_BIT3 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT3
\r
602 #define TC3Lo_BIT4 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT4
\r
603 #define TC3Lo_BIT5 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT5
\r
604 #define TC3Lo_BIT6 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT6
\r
605 #define TC3Lo_BIT7 _TC3.Overlap_STR.TC3LoSTR.Bits.BIT7
\r
606 #define TC3Lo_BIT _TC3.Overlap_STR.TC3LoSTR.MergedBits.grpBIT
\r
614 extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056);
\r
615 #define TC3 _TC3.Word
\r
616 #define TC3_BIT _TC3.MergedBits.grpBIT
\r
619 /*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/
\r
622 /* Overlapped registers: */
\r
624 /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/
\r
628 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 4 Bit 8 */
\r
629 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 4 Bit 9 */
\r
630 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 4 Bit 10 */
\r
631 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 4 Bit 11 */
\r
632 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 4 Bit 12 */
\r
633 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 4 Bit 13 */
\r
634 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 4 Bit 14 */
\r
635 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 4 Bit 15 */
\r
641 #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte
\r
642 #define TC4Hi_BIT8 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT8
\r
643 #define TC4Hi_BIT9 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT9
\r
644 #define TC4Hi_BIT10 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT10
\r
645 #define TC4Hi_BIT11 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT11
\r
646 #define TC4Hi_BIT12 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT12
\r
647 #define TC4Hi_BIT13 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT13
\r
648 #define TC4Hi_BIT14 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT14
\r
649 #define TC4Hi_BIT15 _TC4.Overlap_STR.TC4HiSTR.Bits.BIT15
\r
650 #define TC4Hi_BIT_8 _TC4.Overlap_STR.TC4HiSTR.MergedBits.grpBIT_8
\r
651 #define TC4Hi_BIT TC4Hi_BIT_8
\r
653 /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/
\r
657 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 4 Bit 0 */
\r
658 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 4 Bit 1 */
\r
659 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 4 Bit 2 */
\r
660 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 4 Bit 3 */
\r
661 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 4 Bit 4 */
\r
662 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 4 Bit 5 */
\r
663 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 4 Bit 6 */
\r
664 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 4 Bit 7 */
\r
670 #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte
\r
671 #define TC4Lo_BIT0 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT0
\r
672 #define TC4Lo_BIT1 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT1
\r
673 #define TC4Lo_BIT2 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT2
\r
674 #define TC4Lo_BIT3 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT3
\r
675 #define TC4Lo_BIT4 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT4
\r
676 #define TC4Lo_BIT5 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT5
\r
677 #define TC4Lo_BIT6 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT6
\r
678 #define TC4Lo_BIT7 _TC4.Overlap_STR.TC4LoSTR.Bits.BIT7
\r
679 #define TC4Lo_BIT _TC4.Overlap_STR.TC4LoSTR.MergedBits.grpBIT
\r
687 extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058);
\r
688 #define TC4 _TC4.Word
\r
689 #define TC4_BIT _TC4.MergedBits.grpBIT
\r
692 /*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/
\r
695 /* Overlapped registers: */
\r
697 /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/
\r
701 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 5 Bit 8 */
\r
702 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 5 Bit 9 */
\r
703 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 5 Bit 10 */
\r
704 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 5 Bit 11 */
\r
705 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 5 Bit 12 */
\r
706 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 5 Bit 13 */
\r
707 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 5 Bit 14 */
\r
708 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 5 Bit 15 */
\r
714 #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte
\r
715 #define TC5Hi_BIT8 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT8
\r
716 #define TC5Hi_BIT9 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT9
\r
717 #define TC5Hi_BIT10 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT10
\r
718 #define TC5Hi_BIT11 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT11
\r
719 #define TC5Hi_BIT12 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT12
\r
720 #define TC5Hi_BIT13 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT13
\r
721 #define TC5Hi_BIT14 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT14
\r
722 #define TC5Hi_BIT15 _TC5.Overlap_STR.TC5HiSTR.Bits.BIT15
\r
723 #define TC5Hi_BIT_8 _TC5.Overlap_STR.TC5HiSTR.MergedBits.grpBIT_8
\r
724 #define TC5Hi_BIT TC5Hi_BIT_8
\r
726 /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/
\r
730 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 5 Bit 0 */
\r
731 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 5 Bit 1 */
\r
732 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 5 Bit 2 */
\r
733 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 5 Bit 3 */
\r
734 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 5 Bit 4 */
\r
735 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 5 Bit 5 */
\r
736 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 5 Bit 6 */
\r
737 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 5 Bit 7 */
\r
743 #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte
\r
744 #define TC5Lo_BIT0 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT0
\r
745 #define TC5Lo_BIT1 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT1
\r
746 #define TC5Lo_BIT2 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT2
\r
747 #define TC5Lo_BIT3 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT3
\r
748 #define TC5Lo_BIT4 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT4
\r
749 #define TC5Lo_BIT5 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT5
\r
750 #define TC5Lo_BIT6 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT6
\r
751 #define TC5Lo_BIT7 _TC5.Overlap_STR.TC5LoSTR.Bits.BIT7
\r
752 #define TC5Lo_BIT _TC5.Overlap_STR.TC5LoSTR.MergedBits.grpBIT
\r
760 extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);
\r
761 #define TC5 _TC5.Word
\r
762 #define TC5_BIT _TC5.MergedBits.grpBIT
\r
765 /*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/
\r
768 /* Overlapped registers: */
\r
770 /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/
\r
774 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 6 Bit 8 */
\r
775 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 6 Bit 9 */
\r
776 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 6 Bit 10 */
\r
777 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 6 Bit 11 */
\r
778 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 6 Bit 12 */
\r
779 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 6 Bit 13 */
\r
780 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 6 Bit 14 */
\r
781 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 6 Bit 15 */
\r
787 #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte
\r
788 #define TC6Hi_BIT8 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT8
\r
789 #define TC6Hi_BIT9 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT9
\r
790 #define TC6Hi_BIT10 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT10
\r
791 #define TC6Hi_BIT11 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT11
\r
792 #define TC6Hi_BIT12 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT12
\r
793 #define TC6Hi_BIT13 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT13
\r
794 #define TC6Hi_BIT14 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT14
\r
795 #define TC6Hi_BIT15 _TC6.Overlap_STR.TC6HiSTR.Bits.BIT15
\r
796 #define TC6Hi_BIT_8 _TC6.Overlap_STR.TC6HiSTR.MergedBits.grpBIT_8
\r
797 #define TC6Hi_BIT TC6Hi_BIT_8
\r
799 /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/
\r
803 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 6 Bit 0 */
\r
804 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 6 Bit 1 */
\r
805 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 6 Bit 2 */
\r
806 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 6 Bit 3 */
\r
807 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 6 Bit 4 */
\r
808 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 6 Bit 5 */
\r
809 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 6 Bit 6 */
\r
810 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 6 Bit 7 */
\r
816 #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte
\r
817 #define TC6Lo_BIT0 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT0
\r
818 #define TC6Lo_BIT1 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT1
\r
819 #define TC6Lo_BIT2 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT2
\r
820 #define TC6Lo_BIT3 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT3
\r
821 #define TC6Lo_BIT4 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT4
\r
822 #define TC6Lo_BIT5 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT5
\r
823 #define TC6Lo_BIT6 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT6
\r
824 #define TC6Lo_BIT7 _TC6.Overlap_STR.TC6LoSTR.Bits.BIT7
\r
825 #define TC6Lo_BIT _TC6.Overlap_STR.TC6LoSTR.MergedBits.grpBIT
\r
833 extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);
\r
834 #define TC6 _TC6.Word
\r
835 #define TC6_BIT _TC6.MergedBits.grpBIT
\r
838 /*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/
\r
841 /* Overlapped registers: */
\r
843 /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/
\r
847 byte BIT8 :1; /* Timer Input Capture/Output Compare Register 7 Bit 8 */
\r
848 byte BIT9 :1; /* Timer Input Capture/Output Compare Register 7 Bit 9 */
\r
849 byte BIT10 :1; /* Timer Input Capture/Output Compare Register 7 Bit 10 */
\r
850 byte BIT11 :1; /* Timer Input Capture/Output Compare Register 7 Bit 11 */
\r
851 byte BIT12 :1; /* Timer Input Capture/Output Compare Register 7 Bit 12 */
\r
852 byte BIT13 :1; /* Timer Input Capture/Output Compare Register 7 Bit 13 */
\r
853 byte BIT14 :1; /* Timer Input Capture/Output Compare Register 7 Bit 14 */
\r
854 byte BIT15 :1; /* Timer Input Capture/Output Compare Register 7 Bit 15 */
\r
860 #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte
\r
861 #define TC7Hi_BIT8 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT8
\r
862 #define TC7Hi_BIT9 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT9
\r
863 #define TC7Hi_BIT10 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT10
\r
864 #define TC7Hi_BIT11 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT11
\r
865 #define TC7Hi_BIT12 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT12
\r
866 #define TC7Hi_BIT13 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT13
\r
867 #define TC7Hi_BIT14 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT14
\r
868 #define TC7Hi_BIT15 _TC7.Overlap_STR.TC7HiSTR.Bits.BIT15
\r
869 #define TC7Hi_BIT_8 _TC7.Overlap_STR.TC7HiSTR.MergedBits.grpBIT_8
\r
870 #define TC7Hi_BIT TC7Hi_BIT_8
\r
872 /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/
\r
876 byte BIT0 :1; /* Timer Input Capture/Output Compare Register 7 Bit 0 */
\r
877 byte BIT1 :1; /* Timer Input Capture/Output Compare Register 7 Bit 1 */
\r
878 byte BIT2 :1; /* Timer Input Capture/Output Compare Register 7 Bit 2 */
\r
879 byte BIT3 :1; /* Timer Input Capture/Output Compare Register 7 Bit 3 */
\r
880 byte BIT4 :1; /* Timer Input Capture/Output Compare Register 7 Bit 4 */
\r
881 byte BIT5 :1; /* Timer Input Capture/Output Compare Register 7 Bit 5 */
\r
882 byte BIT6 :1; /* Timer Input Capture/Output Compare Register 7 Bit 6 */
\r
883 byte BIT7 :1; /* Timer Input Capture/Output Compare Register 7 Bit 7 */
\r
889 #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte
\r
890 #define TC7Lo_BIT0 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT0
\r
891 #define TC7Lo_BIT1 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT1
\r
892 #define TC7Lo_BIT2 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT2
\r
893 #define TC7Lo_BIT3 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT3
\r
894 #define TC7Lo_BIT4 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT4
\r
895 #define TC7Lo_BIT5 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT5
\r
896 #define TC7Lo_BIT6 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT6
\r
897 #define TC7Lo_BIT7 _TC7.Overlap_STR.TC7LoSTR.Bits.BIT7
\r
898 #define TC7Lo_BIT _TC7.Overlap_STR.TC7LoSTR.MergedBits.grpBIT
\r
906 extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);
\r
907 #define TC7 _TC7.Word
\r
908 #define TC7_BIT _TC7.MergedBits.grpBIT
\r
911 /*** PACNT - Pulse Accumulators Count Register; 0x00000062 ***/
\r
918 extern volatile PACNTSTR _PACNT @(REG_BASE + 0x00000062);
\r
919 #define PACNT _PACNT.Word
\r
920 #define PACNT_BIT _PACNT.MergedBits.grpBIT
\r
923 /*** ATDCTL23 - ATD Control Register 23; 0x00000082 ***/
\r
926 /* Overlapped registers: */
\r
928 /*** ATDCTL2 - ATD Control Register 2; 0x00000082 ***/
\r
932 byte ASCIF :1; /* ATD Sequence Complete Interrupt Flag */
\r
933 byte ASCIE :1; /* ATD Sequence Complete Interrupt Enable */
\r
934 byte ETRIGE :1; /* External Trigger Mode enable */
\r
935 byte ETRIGP :1; /* External Trigger Polarity */
\r
936 byte ETRIGLE :1; /* External Trigger Level/Edge control */
\r
937 byte AWAI :1; /* ATD Wait Mode */
\r
938 byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */
\r
939 byte ADPU :1; /* ATD Disable / Power Down */
\r
942 #define ATDCTL2 _ATDCTL23.Overlap_STR.ATDCTL2STR.Byte
\r
943 #define ATDCTL2_ASCIF _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIF
\r
944 #define ATDCTL2_ASCIE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ASCIE
\r
945 #define ATDCTL2_ETRIGE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGE
\r
946 #define ATDCTL2_ETRIGP _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGP
\r
947 #define ATDCTL2_ETRIGLE _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ETRIGLE
\r
948 #define ATDCTL2_AWAI _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AWAI
\r
949 #define ATDCTL2_AFFC _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.AFFC
\r
950 #define ATDCTL2_ADPU _ATDCTL23.Overlap_STR.ATDCTL2STR.Bits.ADPU
\r
952 /*** ATDCTL3 - ATD Control Register 3; 0x00000083 ***/
\r
956 byte FRZ0 :1; /* Background Debug Freeze Enable */
\r
957 byte FRZ1 :1; /* Background Debug Freeze Enable */
\r
958 byte FIFO :1; /* Result Register FIFO Mode */
\r
959 byte S1C :1; /* Conversion Sequence Length 1 */
\r
960 byte S2C :1; /* Conversion Sequence Length 2 */
\r
961 byte S4C :1; /* Conversion Sequence Length 4 */
\r
962 byte S8C :1; /* Conversion Sequence Length 8 */
\r
975 #define ATDCTL3 _ATDCTL23.Overlap_STR.ATDCTL3STR.Byte
\r
976 #define ATDCTL3_FRZ0 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ0
\r
977 #define ATDCTL3_FRZ1 _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FRZ1
\r
978 #define ATDCTL3_FIFO _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.FIFO
\r
979 #define ATDCTL3_S1C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S1C
\r
980 #define ATDCTL3_S2C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S2C
\r
981 #define ATDCTL3_S4C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S4C
\r
982 #define ATDCTL3_S8C _ATDCTL23.Overlap_STR.ATDCTL3STR.Bits.S8C
\r
983 #define ATDCTL3_FRZ _ATDCTL23.Overlap_STR.ATDCTL3STR.MergedBits.grpFRZ
\r
988 word FRZ0 :1; /* Background Debug Freeze Enable */
\r
989 word FRZ1 :1; /* Background Debug Freeze Enable */
\r
990 word FIFO :1; /* Result Register FIFO Mode */
\r
991 word S1C :1; /* Conversion Sequence Length 1 */
\r
992 word S2C :1; /* Conversion Sequence Length 2 */
\r
993 word S4C :1; /* Conversion Sequence Length 4 */
\r
994 word S8C :1; /* Conversion Sequence Length 8 */
\r
996 word ASCIF :1; /* ATD Sequence Complete Interrupt Flag */
\r
997 word ASCIE :1; /* ATD Sequence Complete Interrupt Enable */
\r
998 word ETRIGE :1; /* External Trigger Mode enable */
\r
999 word ETRIGP :1; /* External Trigger Polarity */
\r
1000 word ETRIGLE :1; /* External Trigger Level/Edge control */
\r
1001 word AWAI :1; /* ATD Wait Mode */
\r
1002 word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */
\r
1003 word ADPU :1; /* ATD Disable / Power Down */
\r
1023 extern volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082);
\r
1024 #define ATDCTL23 _ATDCTL23.Word
\r
1025 #define ATDCTL23_FRZ0 _ATDCTL23.Bits.FRZ0
\r
1026 #define ATDCTL23_FRZ1 _ATDCTL23.Bits.FRZ1
\r
1027 #define ATDCTL23_FIFO _ATDCTL23.Bits.FIFO
\r
1028 #define ATDCTL23_S1C _ATDCTL23.Bits.S1C
\r
1029 #define ATDCTL23_S2C _ATDCTL23.Bits.S2C
\r
1030 #define ATDCTL23_S4C _ATDCTL23.Bits.S4C
\r
1031 #define ATDCTL23_S8C _ATDCTL23.Bits.S8C
\r
1032 #define ATDCTL23_ASCIF _ATDCTL23.Bits.ASCIF
\r
1033 #define ATDCTL23_ASCIE _ATDCTL23.Bits.ASCIE
\r
1034 #define ATDCTL23_ETRIGE _ATDCTL23.Bits.ETRIGE
\r
1035 #define ATDCTL23_ETRIGP _ATDCTL23.Bits.ETRIGP
\r
1036 #define ATDCTL23_ETRIGLE _ATDCTL23.Bits.ETRIGLE
\r
1037 #define ATDCTL23_AWAI _ATDCTL23.Bits.AWAI
\r
1038 #define ATDCTL23_AFFC _ATDCTL23.Bits.AFFC
\r
1039 #define ATDCTL23_ADPU _ATDCTL23.Bits.ADPU
\r
1040 #define ATDCTL23_FRZ _ATDCTL23.MergedBits.grpFRZ
\r
1043 /*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***/
\r
1046 /* Overlapped registers: */
\r
1048 /*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***/
\r
1052 byte PRS0 :1; /* ATD Clock Prescaler 0 */
\r
1053 byte PRS1 :1; /* ATD Clock Prescaler 1 */
\r
1054 byte PRS2 :1; /* ATD Clock Prescaler 2 */
\r
1055 byte PRS3 :1; /* ATD Clock Prescaler 3 */
\r
1056 byte PRS4 :1; /* ATD Clock Prescaler 4 */
\r
1057 byte SMP0 :1; /* Sample Time Select 0 */
\r
1058 byte SMP1 :1; /* Sample Time Select 1 */
\r
1059 byte SRES8 :1; /* A/D Resolution Select */
\r
1064 byte grpSRES_8 :1;
\r
1067 #define ATDCTL4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Byte
\r
1068 #define ATDCTL4_PRS0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS0
\r
1069 #define ATDCTL4_PRS1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS1
\r
1070 #define ATDCTL4_PRS2 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS2
\r
1071 #define ATDCTL4_PRS3 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS3
\r
1072 #define ATDCTL4_PRS4 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.PRS4
\r
1073 #define ATDCTL4_SMP0 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP0
\r
1074 #define ATDCTL4_SMP1 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SMP1
\r
1075 #define ATDCTL4_SRES8 _ATDCTL45.Overlap_STR.ATDCTL4STR.Bits.SRES8
\r
1076 #define ATDCTL4_PRS _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpPRS
\r
1077 #define ATDCTL4_SMP _ATDCTL45.Overlap_STR.ATDCTL4STR.MergedBits.grpSMP
\r
1079 /*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***/
\r
1083 byte CA :1; /* Analog Input Channel Select Code A */
\r
1084 byte CB :1; /* Analog Input Channel Select Code B */
\r
1085 byte CC :1; /* Analog Input Channel Select Code C */
\r
1087 byte MULT :1; /* Multi-Channel Sample Mode */
\r
1088 byte SCAN :1; /* Continuous Conversion Sequence Mode */
\r
1089 byte DSGN :1; /* Signed/Unsigned Result Data Mode */
\r
1090 byte DJM :1; /* Result Register Data Justification Mode */
\r
1093 #define ATDCTL5 _ATDCTL45.Overlap_STR.ATDCTL5STR.Byte
\r
1094 #define ATDCTL5_CA _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CA
\r
1095 #define ATDCTL5_CB _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CB
\r
1096 #define ATDCTL5_CC _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.CC
\r
1097 #define ATDCTL5_MULT _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.MULT
\r
1098 #define ATDCTL5_SCAN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.SCAN
\r
1099 #define ATDCTL5_DSGN _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DSGN
\r
1100 #define ATDCTL5_DJM _ATDCTL45.Overlap_STR.ATDCTL5STR.Bits.DJM
\r
1105 word CA :1; /* Analog Input Channel Select Code A */
\r
1106 word CB :1; /* Analog Input Channel Select Code B */
\r
1107 word CC :1; /* Analog Input Channel Select Code C */
\r
1109 word MULT :1; /* Multi-Channel Sample Mode */
\r
1110 word SCAN :1; /* Continuous Conversion Sequence Mode */
\r
1111 word DSGN :1; /* Signed/Unsigned Result Data Mode */
\r
1112 word DJM :1; /* Result Register Data Justification Mode */
\r
1113 word PRS0 :1; /* ATD Clock Prescaler 0 */
\r
1114 word PRS1 :1; /* ATD Clock Prescaler 1 */
\r
1115 word PRS2 :1; /* ATD Clock Prescaler 2 */
\r
1116 word PRS3 :1; /* ATD Clock Prescaler 3 */
\r
1117 word PRS4 :1; /* ATD Clock Prescaler 4 */
\r
1118 word SMP0 :1; /* Sample Time Select 0 */
\r
1119 word SMP1 :1; /* Sample Time Select 1 */
\r
1120 word SRES8 :1; /* A/D Resolution Select */
\r
1133 word grpSRES_8 :1;
\r
1136 extern volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084);
\r
1137 #define ATDCTL45 _ATDCTL45.Word
\r
1138 #define ATDCTL45_CA _ATDCTL45.Bits.CA
\r
1139 #define ATDCTL45_CB _ATDCTL45.Bits.CB
\r
1140 #define ATDCTL45_CC _ATDCTL45.Bits.CC
\r
1141 #define ATDCTL45_MULT _ATDCTL45.Bits.MULT
\r
1142 #define ATDCTL45_SCAN _ATDCTL45.Bits.SCAN
\r
1143 #define ATDCTL45_DSGN _ATDCTL45.Bits.DSGN
\r
1144 #define ATDCTL45_DJM _ATDCTL45.Bits.DJM
\r
1145 #define ATDCTL45_PRS0 _ATDCTL45.Bits.PRS0
\r
1146 #define ATDCTL45_PRS1 _ATDCTL45.Bits.PRS1
\r
1147 #define ATDCTL45_PRS2 _ATDCTL45.Bits.PRS2
\r
1148 #define ATDCTL45_PRS3 _ATDCTL45.Bits.PRS3
\r
1149 #define ATDCTL45_PRS4 _ATDCTL45.Bits.PRS4
\r
1150 #define ATDCTL45_SMP0 _ATDCTL45.Bits.SMP0
\r
1151 #define ATDCTL45_SMP1 _ATDCTL45.Bits.SMP1
\r
1152 #define ATDCTL45_SRES8 _ATDCTL45.Bits.SRES8
\r
1153 #define ATDCTL45_PRS _ATDCTL45.MergedBits.grpPRS
\r
1154 #define ATDCTL45_SMP _ATDCTL45.MergedBits.grpSMP
\r
1157 /*** ATDDR0 - A/D Conversion Result Register 0; 0x00000090 ***/
\r
1160 /* Overlapped registers: */
\r
1162 /*** ATDDR0H - A/D Conversion Result Register 0 High; 0x00000090 ***/
\r
1166 byte BIT8 :1; /* Bit 8 */
\r
1167 byte BIT9 :1; /* Bit 9 */
\r
1168 byte BIT10 :1; /* Bit 10 */
\r
1169 byte BIT11 :1; /* Bit 11 */
\r
1170 byte BIT12 :1; /* Bit 12 */
\r
1171 byte BIT13 :1; /* Bit 13 */
\r
1172 byte BIT14 :1; /* Bit 14 */
\r
1173 byte BIT15 :1; /* Bit 15 */
\r
1179 #define ATDDR0H _ATDDR0.Overlap_STR.ATDDR0HSTR.Byte
\r
1180 #define ATDDR0H_BIT8 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT8
\r
1181 #define ATDDR0H_BIT9 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT9
\r
1182 #define ATDDR0H_BIT10 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT10
\r
1183 #define ATDDR0H_BIT11 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT11
\r
1184 #define ATDDR0H_BIT12 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT12
\r
1185 #define ATDDR0H_BIT13 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT13
\r
1186 #define ATDDR0H_BIT14 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT14
\r
1187 #define ATDDR0H_BIT15 _ATDDR0.Overlap_STR.ATDDR0HSTR.Bits.BIT15
\r
1188 #define ATDDR0H_BIT_8 _ATDDR0.Overlap_STR.ATDDR0HSTR.MergedBits.grpBIT_8
\r
1189 #define ATDDR0H_BIT ATDDR0H_BIT_8
\r
1191 /*** ATDDR0L - A/D Conversion Result Register 0 Low; 0x00000091 ***/
\r
1201 byte BIT6 :1; /* Bit 6 */
\r
1202 byte BIT7 :1; /* Bit 7 */
\r
1214 #define ATDDR0L _ATDDR0.Overlap_STR.ATDDR0LSTR.Byte
\r
1215 #define ATDDR0L_BIT6 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT6
\r
1216 #define ATDDR0L_BIT7 _ATDDR0.Overlap_STR.ATDDR0LSTR.Bits.BIT7
\r
1217 #define ATDDR0L_BIT_6 _ATDDR0.Overlap_STR.ATDDR0LSTR.MergedBits.grpBIT_6
\r
1218 #define ATDDR0L_BIT ATDDR0L_BIT_6
\r
1229 word BIT6 :1; /* Bit 6 */
\r
1230 word BIT7 :1; /* Bit 7 */
\r
1231 word BIT8 :1; /* Bit 8 */
\r
1232 word BIT9 :1; /* Bit 9 */
\r
1233 word BIT10 :1; /* Bit 10 */
\r
1234 word BIT11 :1; /* Bit 11 */
\r
1235 word BIT12 :1; /* Bit 12 */
\r
1236 word BIT13 :1; /* Bit 13 */
\r
1237 word BIT14 :1; /* Bit 14 */
\r
1238 word BIT15 :1; /* Bit 15 */
\r
1247 word grpBIT_6 :10;
\r
1250 extern volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090);
\r
1251 #define ATDDR0 _ATDDR0.Word
\r
1252 #define ATDDR0_BIT6 _ATDDR0.Bits.BIT6
\r
1253 #define ATDDR0_BIT7 _ATDDR0.Bits.BIT7
\r
1254 #define ATDDR0_BIT8 _ATDDR0.Bits.BIT8
\r
1255 #define ATDDR0_BIT9 _ATDDR0.Bits.BIT9
\r
1256 #define ATDDR0_BIT10 _ATDDR0.Bits.BIT10
\r
1257 #define ATDDR0_BIT11 _ATDDR0.Bits.BIT11
\r
1258 #define ATDDR0_BIT12 _ATDDR0.Bits.BIT12
\r
1259 #define ATDDR0_BIT13 _ATDDR0.Bits.BIT13
\r
1260 #define ATDDR0_BIT14 _ATDDR0.Bits.BIT14
\r
1261 #define ATDDR0_BIT15 _ATDDR0.Bits.BIT15
\r
1262 #define ATDDR0_BIT_6 _ATDDR0.MergedBits.grpBIT_6
\r
1263 #define ATDDR0_BIT ATDDR0_BIT_6
\r
1266 /*** ATDDR1 - A/D Conversion Result Register 1; 0x00000092 ***/
\r
1269 /* Overlapped registers: */
\r
1271 /*** ATDDR1H - A/D Conversion Result Register 1 High; 0x00000092 ***/
\r
1275 byte BIT8 :1; /* Bit 8 */
\r
1276 byte BIT9 :1; /* Bit 9 */
\r
1277 byte BIT10 :1; /* Bit 10 */
\r
1278 byte BIT11 :1; /* Bit 11 */
\r
1279 byte BIT12 :1; /* Bit 12 */
\r
1280 byte BIT13 :1; /* Bit 13 */
\r
1281 byte BIT14 :1; /* Bit 14 */
\r
1282 byte BIT15 :1; /* Bit 15 */
\r
1288 #define ATDDR1H _ATDDR1.Overlap_STR.ATDDR1HSTR.Byte
\r
1289 #define ATDDR1H_BIT8 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT8
\r
1290 #define ATDDR1H_BIT9 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT9
\r
1291 #define ATDDR1H_BIT10 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT10
\r
1292 #define ATDDR1H_BIT11 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT11
\r
1293 #define ATDDR1H_BIT12 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT12
\r
1294 #define ATDDR1H_BIT13 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT13
\r
1295 #define ATDDR1H_BIT14 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT14
\r
1296 #define ATDDR1H_BIT15 _ATDDR1.Overlap_STR.ATDDR1HSTR.Bits.BIT15
\r
1297 #define ATDDR1H_BIT_8 _ATDDR1.Overlap_STR.ATDDR1HSTR.MergedBits.grpBIT_8
\r
1298 #define ATDDR1H_BIT ATDDR1H_BIT_8
\r
1300 /*** ATDDR1L - A/D Conversion Result Register 1 Low; 0x00000093 ***/
\r
1310 byte BIT6 :1; /* Bit 6 */
\r
1311 byte BIT7 :1; /* Bit 7 */
\r
1323 #define ATDDR1L _ATDDR1.Overlap_STR.ATDDR1LSTR.Byte
\r
1324 #define ATDDR1L_BIT6 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT6
\r
1325 #define ATDDR1L_BIT7 _ATDDR1.Overlap_STR.ATDDR1LSTR.Bits.BIT7
\r
1326 #define ATDDR1L_BIT_6 _ATDDR1.Overlap_STR.ATDDR1LSTR.MergedBits.grpBIT_6
\r
1327 #define ATDDR1L_BIT ATDDR1L_BIT_6
\r
1338 word BIT6 :1; /* Bit 6 */
\r
1339 word BIT7 :1; /* Bit 7 */
\r
1340 word BIT8 :1; /* Bit 8 */
\r
1341 word BIT9 :1; /* Bit 9 */
\r
1342 word BIT10 :1; /* Bit 10 */
\r
1343 word BIT11 :1; /* Bit 11 */
\r
1344 word BIT12 :1; /* Bit 12 */
\r
1345 word BIT13 :1; /* Bit 13 */
\r
1346 word BIT14 :1; /* Bit 14 */
\r
1347 word BIT15 :1; /* Bit 15 */
\r
1356 word grpBIT_6 :10;
\r
1359 extern volatile ATDDR1STR _ATDDR1 @(REG_BASE + 0x00000092);
\r
1360 #define ATDDR1 _ATDDR1.Word
\r
1361 #define ATDDR1_BIT6 _ATDDR1.Bits.BIT6
\r
1362 #define ATDDR1_BIT7 _ATDDR1.Bits.BIT7
\r
1363 #define ATDDR1_BIT8 _ATDDR1.Bits.BIT8
\r
1364 #define ATDDR1_BIT9 _ATDDR1.Bits.BIT9
\r
1365 #define ATDDR1_BIT10 _ATDDR1.Bits.BIT10
\r
1366 #define ATDDR1_BIT11 _ATDDR1.Bits.BIT11
\r
1367 #define ATDDR1_BIT12 _ATDDR1.Bits.BIT12
\r
1368 #define ATDDR1_BIT13 _ATDDR1.Bits.BIT13
\r
1369 #define ATDDR1_BIT14 _ATDDR1.Bits.BIT14
\r
1370 #define ATDDR1_BIT15 _ATDDR1.Bits.BIT15
\r
1371 #define ATDDR1_BIT_6 _ATDDR1.MergedBits.grpBIT_6
\r
1372 #define ATDDR1_BIT ATDDR1_BIT_6
\r
1375 /*** ATDDR2 - A/D Conversion Result Register 2; 0x00000094 ***/
\r
1378 /* Overlapped registers: */
\r
1380 /*** ATDDR2H - A/D Conversion Result Register 2 High; 0x00000094 ***/
\r
1384 byte BIT8 :1; /* Bit 8 */
\r
1385 byte BIT9 :1; /* Bit 9 */
\r
1386 byte BIT10 :1; /* Bit 10 */
\r
1387 byte BIT11 :1; /* Bit 11 */
\r
1388 byte BIT12 :1; /* Bit 12 */
\r
1389 byte BIT13 :1; /* Bit 13 */
\r
1390 byte BIT14 :1; /* Bit 14 */
\r
1391 byte BIT15 :1; /* Bit 15 */
\r
1397 #define ATDDR2H _ATDDR2.Overlap_STR.ATDDR2HSTR.Byte
\r
1398 #define ATDDR2H_BIT8 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT8
\r
1399 #define ATDDR2H_BIT9 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT9
\r
1400 #define ATDDR2H_BIT10 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT10
\r
1401 #define ATDDR2H_BIT11 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT11
\r
1402 #define ATDDR2H_BIT12 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT12
\r
1403 #define ATDDR2H_BIT13 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT13
\r
1404 #define ATDDR2H_BIT14 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT14
\r
1405 #define ATDDR2H_BIT15 _ATDDR2.Overlap_STR.ATDDR2HSTR.Bits.BIT15
\r
1406 #define ATDDR2H_BIT_8 _ATDDR2.Overlap_STR.ATDDR2HSTR.MergedBits.grpBIT_8
\r
1407 #define ATDDR2H_BIT ATDDR2H_BIT_8
\r
1409 /*** ATDDR2L - A/D Conversion Result Register 2 Low; 0x00000095 ***/
\r
1419 byte BIT6 :1; /* Bit 6 */
\r
1420 byte BIT7 :1; /* Bit 7 */
\r
1432 #define ATDDR2L _ATDDR2.Overlap_STR.ATDDR2LSTR.Byte
\r
1433 #define ATDDR2L_BIT6 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT6
\r
1434 #define ATDDR2L_BIT7 _ATDDR2.Overlap_STR.ATDDR2LSTR.Bits.BIT7
\r
1435 #define ATDDR2L_BIT_6 _ATDDR2.Overlap_STR.ATDDR2LSTR.MergedBits.grpBIT_6
\r
1436 #define ATDDR2L_BIT ATDDR2L_BIT_6
\r
1447 word BIT6 :1; /* Bit 6 */
\r
1448 word BIT7 :1; /* Bit 7 */
\r
1449 word BIT8 :1; /* Bit 8 */
\r
1450 word BIT9 :1; /* Bit 9 */
\r
1451 word BIT10 :1; /* Bit 10 */
\r
1452 word BIT11 :1; /* Bit 11 */
\r
1453 word BIT12 :1; /* Bit 12 */
\r
1454 word BIT13 :1; /* Bit 13 */
\r
1455 word BIT14 :1; /* Bit 14 */
\r
1456 word BIT15 :1; /* Bit 15 */
\r
1465 word grpBIT_6 :10;
\r
1468 extern volatile ATDDR2STR _ATDDR2 @(REG_BASE + 0x00000094);
\r
1469 #define ATDDR2 _ATDDR2.Word
\r
1470 #define ATDDR2_BIT6 _ATDDR2.Bits.BIT6
\r
1471 #define ATDDR2_BIT7 _ATDDR2.Bits.BIT7
\r
1472 #define ATDDR2_BIT8 _ATDDR2.Bits.BIT8
\r
1473 #define ATDDR2_BIT9 _ATDDR2.Bits.BIT9
\r
1474 #define ATDDR2_BIT10 _ATDDR2.Bits.BIT10
\r
1475 #define ATDDR2_BIT11 _ATDDR2.Bits.BIT11
\r
1476 #define ATDDR2_BIT12 _ATDDR2.Bits.BIT12
\r
1477 #define ATDDR2_BIT13 _ATDDR2.Bits.BIT13
\r
1478 #define ATDDR2_BIT14 _ATDDR2.Bits.BIT14
\r
1479 #define ATDDR2_BIT15 _ATDDR2.Bits.BIT15
\r
1480 #define ATDDR2_BIT_6 _ATDDR2.MergedBits.grpBIT_6
\r
1481 #define ATDDR2_BIT ATDDR2_BIT_6
\r
1484 /*** ATDDR3 - A/D Conversion Result Register 3; 0x00000096 ***/
\r
1487 /* Overlapped registers: */
\r
1489 /*** ATDDR3H - A/D Conversion Result Register 3 High; 0x00000096 ***/
\r
1493 byte BIT8 :1; /* Bit 8 */
\r
1494 byte BIT9 :1; /* Bit 9 */
\r
1495 byte BIT10 :1; /* Bit 10 */
\r
1496 byte BIT11 :1; /* Bit 11 */
\r
1497 byte BIT12 :1; /* Bit 12 */
\r
1498 byte BIT13 :1; /* Bit 13 */
\r
1499 byte BIT14 :1; /* Bit 14 */
\r
1500 byte BIT15 :1; /* Bit 15 */
\r
1506 #define ATDDR3H _ATDDR3.Overlap_STR.ATDDR3HSTR.Byte
\r
1507 #define ATDDR3H_BIT8 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT8
\r
1508 #define ATDDR3H_BIT9 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT9
\r
1509 #define ATDDR3H_BIT10 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT10
\r
1510 #define ATDDR3H_BIT11 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT11
\r
1511 #define ATDDR3H_BIT12 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT12
\r
1512 #define ATDDR3H_BIT13 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT13
\r
1513 #define ATDDR3H_BIT14 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT14
\r
1514 #define ATDDR3H_BIT15 _ATDDR3.Overlap_STR.ATDDR3HSTR.Bits.BIT15
\r
1515 #define ATDDR3H_BIT_8 _ATDDR3.Overlap_STR.ATDDR3HSTR.MergedBits.grpBIT_8
\r
1516 #define ATDDR3H_BIT ATDDR3H_BIT_8
\r
1518 /*** ATDDR3L - A/D Conversion Result Register 3 Low; 0x00000097 ***/
\r
1528 byte BIT6 :1; /* Bit 6 */
\r
1529 byte BIT7 :1; /* Bit 7 */
\r
1541 #define ATDDR3L _ATDDR3.Overlap_STR.ATDDR3LSTR.Byte
\r
1542 #define ATDDR3L_BIT6 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT6
\r
1543 #define ATDDR3L_BIT7 _ATDDR3.Overlap_STR.ATDDR3LSTR.Bits.BIT7
\r
1544 #define ATDDR3L_BIT_6 _ATDDR3.Overlap_STR.ATDDR3LSTR.MergedBits.grpBIT_6
\r
1545 #define ATDDR3L_BIT ATDDR3L_BIT_6
\r
1556 word BIT6 :1; /* Bit 6 */
\r
1557 word BIT7 :1; /* Bit 7 */
\r
1558 word BIT8 :1; /* Bit 8 */
\r
1559 word BIT9 :1; /* Bit 9 */
\r
1560 word BIT10 :1; /* Bit 10 */
\r
1561 word BIT11 :1; /* Bit 11 */
\r
1562 word BIT12 :1; /* Bit 12 */
\r
1563 word BIT13 :1; /* Bit 13 */
\r
1564 word BIT14 :1; /* Bit 14 */
\r
1565 word BIT15 :1; /* Bit 15 */
\r
1574 word grpBIT_6 :10;
\r
1577 extern volatile ATDDR3STR _ATDDR3 @(REG_BASE + 0x00000096);
\r
1578 #define ATDDR3 _ATDDR3.Word
\r
1579 #define ATDDR3_BIT6 _ATDDR3.Bits.BIT6
\r
1580 #define ATDDR3_BIT7 _ATDDR3.Bits.BIT7
\r
1581 #define ATDDR3_BIT8 _ATDDR3.Bits.BIT8
\r
1582 #define ATDDR3_BIT9 _ATDDR3.Bits.BIT9
\r
1583 #define ATDDR3_BIT10 _ATDDR3.Bits.BIT10
\r
1584 #define ATDDR3_BIT11 _ATDDR3.Bits.BIT11
\r
1585 #define ATDDR3_BIT12 _ATDDR3.Bits.BIT12
\r
1586 #define ATDDR3_BIT13 _ATDDR3.Bits.BIT13
\r
1587 #define ATDDR3_BIT14 _ATDDR3.Bits.BIT14
\r
1588 #define ATDDR3_BIT15 _ATDDR3.Bits.BIT15
\r
1589 #define ATDDR3_BIT_6 _ATDDR3.MergedBits.grpBIT_6
\r
1590 #define ATDDR3_BIT ATDDR3_BIT_6
\r
1593 /*** ATDDR4 - A/D Conversion Result Register 4; 0x00000098 ***/
\r
1596 /* Overlapped registers: */
\r
1598 /*** ATDDR4H - A/D Conversion Result Register 4 High; 0x00000098 ***/
\r
1602 byte BIT8 :1; /* Bit 8 */
\r
1603 byte BIT9 :1; /* Bit 9 */
\r
1604 byte BIT10 :1; /* Bit 10 */
\r
1605 byte BIT11 :1; /* Bit 11 */
\r
1606 byte BIT12 :1; /* Bit 12 */
\r
1607 byte BIT13 :1; /* Bit 13 */
\r
1608 byte BIT14 :1; /* Bit 14 */
\r
1609 byte BIT15 :1; /* Bit 15 */
\r
1615 #define ATDDR4H _ATDDR4.Overlap_STR.ATDDR4HSTR.Byte
\r
1616 #define ATDDR4H_BIT8 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT8
\r
1617 #define ATDDR4H_BIT9 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT9
\r
1618 #define ATDDR4H_BIT10 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT10
\r
1619 #define ATDDR4H_BIT11 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT11
\r
1620 #define ATDDR4H_BIT12 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT12
\r
1621 #define ATDDR4H_BIT13 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT13
\r
1622 #define ATDDR4H_BIT14 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT14
\r
1623 #define ATDDR4H_BIT15 _ATDDR4.Overlap_STR.ATDDR4HSTR.Bits.BIT15
\r
1624 #define ATDDR4H_BIT_8 _ATDDR4.Overlap_STR.ATDDR4HSTR.MergedBits.grpBIT_8
\r
1625 #define ATDDR4H_BIT ATDDR4H_BIT_8
\r
1627 /*** ATDDR4L - A/D Conversion Result Register 4 Low; 0x00000099 ***/
\r
1637 byte BIT6 :1; /* Bit 6 */
\r
1638 byte BIT7 :1; /* Bit 7 */
\r
1650 #define ATDDR4L _ATDDR4.Overlap_STR.ATDDR4LSTR.Byte
\r
1651 #define ATDDR4L_BIT6 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT6
\r
1652 #define ATDDR4L_BIT7 _ATDDR4.Overlap_STR.ATDDR4LSTR.Bits.BIT7
\r
1653 #define ATDDR4L_BIT_6 _ATDDR4.Overlap_STR.ATDDR4LSTR.MergedBits.grpBIT_6
\r
1654 #define ATDDR4L_BIT ATDDR4L_BIT_6
\r
1665 word BIT6 :1; /* Bit 6 */
\r
1666 word BIT7 :1; /* Bit 7 */
\r
1667 word BIT8 :1; /* Bit 8 */
\r
1668 word BIT9 :1; /* Bit 9 */
\r
1669 word BIT10 :1; /* Bit 10 */
\r
1670 word BIT11 :1; /* Bit 11 */
\r
1671 word BIT12 :1; /* Bit 12 */
\r
1672 word BIT13 :1; /* Bit 13 */
\r
1673 word BIT14 :1; /* Bit 14 */
\r
1674 word BIT15 :1; /* Bit 15 */
\r
1683 word grpBIT_6 :10;
\r
1686 extern volatile ATDDR4STR _ATDDR4 @(REG_BASE + 0x00000098);
\r
1687 #define ATDDR4 _ATDDR4.Word
\r
1688 #define ATDDR4_BIT6 _ATDDR4.Bits.BIT6
\r
1689 #define ATDDR4_BIT7 _ATDDR4.Bits.BIT7
\r
1690 #define ATDDR4_BIT8 _ATDDR4.Bits.BIT8
\r
1691 #define ATDDR4_BIT9 _ATDDR4.Bits.BIT9
\r
1692 #define ATDDR4_BIT10 _ATDDR4.Bits.BIT10
\r
1693 #define ATDDR4_BIT11 _ATDDR4.Bits.BIT11
\r
1694 #define ATDDR4_BIT12 _ATDDR4.Bits.BIT12
\r
1695 #define ATDDR4_BIT13 _ATDDR4.Bits.BIT13
\r
1696 #define ATDDR4_BIT14 _ATDDR4.Bits.BIT14
\r
1697 #define ATDDR4_BIT15 _ATDDR4.Bits.BIT15
\r
1698 #define ATDDR4_BIT_6 _ATDDR4.MergedBits.grpBIT_6
\r
1699 #define ATDDR4_BIT ATDDR4_BIT_6
\r
1702 /*** ATDDR5 - A/D Conversion Result Register 5; 0x0000009A ***/
\r
1705 /* Overlapped registers: */
\r
1707 /*** ATDDR5H - A/D Conversion Result Register 5 High; 0x0000009A ***/
\r
1711 byte BIT8 :1; /* Bit 8 */
\r
1712 byte BIT9 :1; /* Bit 9 */
\r
1713 byte BIT10 :1; /* Bit 10 */
\r
1714 byte BIT11 :1; /* Bit 11 */
\r
1715 byte BIT12 :1; /* Bit 12 */
\r
1716 byte BIT13 :1; /* Bit 13 */
\r
1717 byte BIT14 :1; /* Bit 14 */
\r
1718 byte BIT15 :1; /* Bit 15 */
\r
1724 #define ATDDR5H _ATDDR5.Overlap_STR.ATDDR5HSTR.Byte
\r
1725 #define ATDDR5H_BIT8 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT8
\r
1726 #define ATDDR5H_BIT9 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT9
\r
1727 #define ATDDR5H_BIT10 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT10
\r
1728 #define ATDDR5H_BIT11 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT11
\r
1729 #define ATDDR5H_BIT12 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT12
\r
1730 #define ATDDR5H_BIT13 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT13
\r
1731 #define ATDDR5H_BIT14 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT14
\r
1732 #define ATDDR5H_BIT15 _ATDDR5.Overlap_STR.ATDDR5HSTR.Bits.BIT15
\r
1733 #define ATDDR5H_BIT_8 _ATDDR5.Overlap_STR.ATDDR5HSTR.MergedBits.grpBIT_8
\r
1734 #define ATDDR5H_BIT ATDDR5H_BIT_8
\r
1736 /*** ATDDR5L - A/D Conversion Result Register 5 Low; 0x0000009B ***/
\r
1746 byte BIT6 :1; /* Bit 6 */
\r
1747 byte BIT7 :1; /* Bit 7 */
\r
1759 #define ATDDR5L _ATDDR5.Overlap_STR.ATDDR5LSTR.Byte
\r
1760 #define ATDDR5L_BIT6 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT6
\r
1761 #define ATDDR5L_BIT7 _ATDDR5.Overlap_STR.ATDDR5LSTR.Bits.BIT7
\r
1762 #define ATDDR5L_BIT_6 _ATDDR5.Overlap_STR.ATDDR5LSTR.MergedBits.grpBIT_6
\r
1763 #define ATDDR5L_BIT ATDDR5L_BIT_6
\r
1774 word BIT6 :1; /* Bit 6 */
\r
1775 word BIT7 :1; /* Bit 7 */
\r
1776 word BIT8 :1; /* Bit 8 */
\r
1777 word BIT9 :1; /* Bit 9 */
\r
1778 word BIT10 :1; /* Bit 10 */
\r
1779 word BIT11 :1; /* Bit 11 */
\r
1780 word BIT12 :1; /* Bit 12 */
\r
1781 word BIT13 :1; /* Bit 13 */
\r
1782 word BIT14 :1; /* Bit 14 */
\r
1783 word BIT15 :1; /* Bit 15 */
\r
1792 word grpBIT_6 :10;
\r
1795 extern volatile ATDDR5STR _ATDDR5 @(REG_BASE + 0x0000009A);
\r
1796 #define ATDDR5 _ATDDR5.Word
\r
1797 #define ATDDR5_BIT6 _ATDDR5.Bits.BIT6
\r
1798 #define ATDDR5_BIT7 _ATDDR5.Bits.BIT7
\r
1799 #define ATDDR5_BIT8 _ATDDR5.Bits.BIT8
\r
1800 #define ATDDR5_BIT9 _ATDDR5.Bits.BIT9
\r
1801 #define ATDDR5_BIT10 _ATDDR5.Bits.BIT10
\r
1802 #define ATDDR5_BIT11 _ATDDR5.Bits.BIT11
\r
1803 #define ATDDR5_BIT12 _ATDDR5.Bits.BIT12
\r
1804 #define ATDDR5_BIT13 _ATDDR5.Bits.BIT13
\r
1805 #define ATDDR5_BIT14 _ATDDR5.Bits.BIT14
\r
1806 #define ATDDR5_BIT15 _ATDDR5.Bits.BIT15
\r
1807 #define ATDDR5_BIT_6 _ATDDR5.MergedBits.grpBIT_6
\r
1808 #define ATDDR5_BIT ATDDR5_BIT_6
\r
1811 /*** ATDDR6 - A/D Conversion Result Register 6; 0x0000009C ***/
\r
1814 /* Overlapped registers: */
\r
1816 /*** ATDDR6H - A/D Conversion Result Register 6 High; 0x0000009C ***/
\r
1820 byte BIT8 :1; /* Bit 8 */
\r
1821 byte BIT9 :1; /* Bit 9 */
\r
1822 byte BIT10 :1; /* Bit 10 */
\r
1823 byte BIT11 :1; /* Bit 11 */
\r
1824 byte BIT12 :1; /* Bit 12 */
\r
1825 byte BIT13 :1; /* Bit 13 */
\r
1826 byte BIT14 :1; /* Bit 14 */
\r
1827 byte BIT15 :1; /* Bit 15 */
\r
1833 #define ATDDR6H _ATDDR6.Overlap_STR.ATDDR6HSTR.Byte
\r
1834 #define ATDDR6H_BIT8 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT8
\r
1835 #define ATDDR6H_BIT9 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT9
\r
1836 #define ATDDR6H_BIT10 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT10
\r
1837 #define ATDDR6H_BIT11 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT11
\r
1838 #define ATDDR6H_BIT12 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT12
\r
1839 #define ATDDR6H_BIT13 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT13
\r
1840 #define ATDDR6H_BIT14 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT14
\r
1841 #define ATDDR6H_BIT15 _ATDDR6.Overlap_STR.ATDDR6HSTR.Bits.BIT15
\r
1842 #define ATDDR6H_BIT_8 _ATDDR6.Overlap_STR.ATDDR6HSTR.MergedBits.grpBIT_8
\r
1843 #define ATDDR6H_BIT ATDDR6H_BIT_8
\r
1845 /*** ATDDR6L - A/D Conversion Result Register 6 Low; 0x0000009D ***/
\r
1855 byte BIT6 :1; /* Bit 6 */
\r
1856 byte BIT7 :1; /* Bit 7 */
\r
1868 #define ATDDR6L _ATDDR6.Overlap_STR.ATDDR6LSTR.Byte
\r
1869 #define ATDDR6L_BIT6 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT6
\r
1870 #define ATDDR6L_BIT7 _ATDDR6.Overlap_STR.ATDDR6LSTR.Bits.BIT7
\r
1871 #define ATDDR6L_BIT_6 _ATDDR6.Overlap_STR.ATDDR6LSTR.MergedBits.grpBIT_6
\r
1872 #define ATDDR6L_BIT ATDDR6L_BIT_6
\r
1883 word BIT6 :1; /* Bit 6 */
\r
1884 word BIT7 :1; /* Bit 7 */
\r
1885 word BIT8 :1; /* Bit 8 */
\r
1886 word BIT9 :1; /* Bit 9 */
\r
1887 word BIT10 :1; /* Bit 10 */
\r
1888 word BIT11 :1; /* Bit 11 */
\r
1889 word BIT12 :1; /* Bit 12 */
\r
1890 word BIT13 :1; /* Bit 13 */
\r
1891 word BIT14 :1; /* Bit 14 */
\r
1892 word BIT15 :1; /* Bit 15 */
\r
1901 word grpBIT_6 :10;
\r
1904 extern volatile ATDDR6STR _ATDDR6 @(REG_BASE + 0x0000009C);
\r
1905 #define ATDDR6 _ATDDR6.Word
\r
1906 #define ATDDR6_BIT6 _ATDDR6.Bits.BIT6
\r
1907 #define ATDDR6_BIT7 _ATDDR6.Bits.BIT7
\r
1908 #define ATDDR6_BIT8 _ATDDR6.Bits.BIT8
\r
1909 #define ATDDR6_BIT9 _ATDDR6.Bits.BIT9
\r
1910 #define ATDDR6_BIT10 _ATDDR6.Bits.BIT10
\r
1911 #define ATDDR6_BIT11 _ATDDR6.Bits.BIT11
\r
1912 #define ATDDR6_BIT12 _ATDDR6.Bits.BIT12
\r
1913 #define ATDDR6_BIT13 _ATDDR6.Bits.BIT13
\r
1914 #define ATDDR6_BIT14 _ATDDR6.Bits.BIT14
\r
1915 #define ATDDR6_BIT15 _ATDDR6.Bits.BIT15
\r
1916 #define ATDDR6_BIT_6 _ATDDR6.MergedBits.grpBIT_6
\r
1917 #define ATDDR6_BIT ATDDR6_BIT_6
\r
1920 /*** ATDDR7 - A/D Conversion Result Register 7; 0x0000009E ***/
\r
1923 /* Overlapped registers: */
\r
1925 /*** ATDDR7H - A/D Conversion Result Register 7 High; 0x0000009E ***/
\r
1929 byte BIT8 :1; /* Bit 8 */
\r
1930 byte BIT9 :1; /* Bit 9 */
\r
1931 byte BIT10 :1; /* Bit 10 */
\r
1932 byte BIT11 :1; /* Bit 11 */
\r
1933 byte BIT12 :1; /* Bit 12 */
\r
1934 byte BIT13 :1; /* Bit 13 */
\r
1935 byte BIT14 :1; /* Bit 14 */
\r
1936 byte BIT15 :1; /* Bit 15 */
\r
1942 #define ATDDR7H _ATDDR7.Overlap_STR.ATDDR7HSTR.Byte
\r
1943 #define ATDDR7H_BIT8 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT8
\r
1944 #define ATDDR7H_BIT9 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT9
\r
1945 #define ATDDR7H_BIT10 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT10
\r
1946 #define ATDDR7H_BIT11 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT11
\r
1947 #define ATDDR7H_BIT12 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT12
\r
1948 #define ATDDR7H_BIT13 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT13
\r
1949 #define ATDDR7H_BIT14 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT14
\r
1950 #define ATDDR7H_BIT15 _ATDDR7.Overlap_STR.ATDDR7HSTR.Bits.BIT15
\r
1951 #define ATDDR7H_BIT_8 _ATDDR7.Overlap_STR.ATDDR7HSTR.MergedBits.grpBIT_8
\r
1952 #define ATDDR7H_BIT ATDDR7H_BIT_8
\r
1954 /*** ATDDR7L - A/D Conversion Result Register 7 Low; 0x0000009F ***/
\r
1964 byte BIT6 :1; /* Bit 6 */
\r
1965 byte BIT7 :1; /* Bit 7 */
\r
1977 #define ATDDR7L _ATDDR7.Overlap_STR.ATDDR7LSTR.Byte
\r
1978 #define ATDDR7L_BIT6 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT6
\r
1979 #define ATDDR7L_BIT7 _ATDDR7.Overlap_STR.ATDDR7LSTR.Bits.BIT7
\r
1980 #define ATDDR7L_BIT_6 _ATDDR7.Overlap_STR.ATDDR7LSTR.MergedBits.grpBIT_6
\r
1981 #define ATDDR7L_BIT ATDDR7L_BIT_6
\r
1992 word BIT6 :1; /* Bit 6 */
\r
1993 word BIT7 :1; /* Bit 7 */
\r
1994 word BIT8 :1; /* Bit 8 */
\r
1995 word BIT9 :1; /* Bit 9 */
\r
1996 word BIT10 :1; /* Bit 10 */
\r
1997 word BIT11 :1; /* Bit 11 */
\r
1998 word BIT12 :1; /* Bit 12 */
\r
1999 word BIT13 :1; /* Bit 13 */
\r
2000 word BIT14 :1; /* Bit 14 */
\r
2001 word BIT15 :1; /* Bit 15 */
\r
2010 word grpBIT_6 :10;
\r
2013 extern volatile ATDDR7STR _ATDDR7 @(REG_BASE + 0x0000009E);
\r
2014 #define ATDDR7 _ATDDR7.Word
\r
2015 #define ATDDR7_BIT6 _ATDDR7.Bits.BIT6
\r
2016 #define ATDDR7_BIT7 _ATDDR7.Bits.BIT7
\r
2017 #define ATDDR7_BIT8 _ATDDR7.Bits.BIT8
\r
2018 #define ATDDR7_BIT9 _ATDDR7.Bits.BIT9
\r
2019 #define ATDDR7_BIT10 _ATDDR7.Bits.BIT10
\r
2020 #define ATDDR7_BIT11 _ATDDR7.Bits.BIT11
\r
2021 #define ATDDR7_BIT12 _ATDDR7.Bits.BIT12
\r
2022 #define ATDDR7_BIT13 _ATDDR7.Bits.BIT13
\r
2023 #define ATDDR7_BIT14 _ATDDR7.Bits.BIT14
\r
2024 #define ATDDR7_BIT15 _ATDDR7.Bits.BIT15
\r
2025 #define ATDDR7_BIT_6 _ATDDR7.MergedBits.grpBIT_6
\r
2026 #define ATDDR7_BIT ATDDR7_BIT_6
\r
2029 /*** SCIBD - SCI Baud Rate Register; 0x000000C8 ***/
\r
2032 /* Overlapped registers: */
\r
2034 /*** SCIBDH - SCI Baud Rate Register High; 0x000000C8 ***/
\r
2038 byte SBR8 :1; /* SCI baud rate Bit 8 */
\r
2039 byte SBR9 :1; /* SCI baud rate Bit 9 */
\r
2040 byte SBR10 :1; /* SCI baud rate Bit 10 */
\r
2041 byte SBR11 :1; /* SCI baud rate Bit 11 */
\r
2042 byte SBR12 :1; /* SCI baud rate Bit 12 */
\r
2054 #define SCIBDH _SCIBD.Overlap_STR.SCIBDHSTR.Byte
\r
2055 #define SCIBDH_SBR8 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR8
\r
2056 #define SCIBDH_SBR9 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR9
\r
2057 #define SCIBDH_SBR10 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR10
\r
2058 #define SCIBDH_SBR11 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR11
\r
2059 #define SCIBDH_SBR12 _SCIBD.Overlap_STR.SCIBDHSTR.Bits.SBR12
\r
2060 #define SCIBDH_SBR_8 _SCIBD.Overlap_STR.SCIBDHSTR.MergedBits.grpSBR_8
\r
2061 #define SCIBDH_SBR SCIBDH_SBR_8
\r
2063 /*** SCIBDL - SCI Baud Rate Register Low; 0x000000C9 ***/
\r
2067 byte SBR0 :1; /* SCI baud rate Bit 0 */
\r
2068 byte SBR1 :1; /* SCI baud rate Bit 1 */
\r
2069 byte SBR2 :1; /* SCI baud rate Bit 2 */
\r
2070 byte SBR3 :1; /* SCI baud rate Bit 3 */
\r
2071 byte SBR4 :1; /* SCI baud rate Bit 4 */
\r
2072 byte SBR5 :1; /* SCI baud rate Bit 5 */
\r
2073 byte SBR6 :1; /* SCI baud rate Bit 6 */
\r
2074 byte SBR7 :1; /* SCI baud rate Bit 7 */
\r
2080 #define SCIBDL _SCIBD.Overlap_STR.SCIBDLSTR.Byte
\r
2081 #define SCIBDL_SBR0 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR0
\r
2082 #define SCIBDL_SBR1 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR1
\r
2083 #define SCIBDL_SBR2 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR2
\r
2084 #define SCIBDL_SBR3 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR3
\r
2085 #define SCIBDL_SBR4 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR4
\r
2086 #define SCIBDL_SBR5 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR5
\r
2087 #define SCIBDL_SBR6 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR6
\r
2088 #define SCIBDL_SBR7 _SCIBD.Overlap_STR.SCIBDLSTR.Bits.SBR7
\r
2089 #define SCIBDL_SBR _SCIBD.Overlap_STR.SCIBDLSTR.MergedBits.grpSBR
\r
2094 word SBR0 :1; /* SCI baud rate Bit 0 */
\r
2095 word SBR1 :1; /* SCI baud rate Bit 1 */
\r
2096 word SBR2 :1; /* SCI baud rate Bit 2 */
\r
2097 word SBR3 :1; /* SCI baud rate Bit 3 */
\r
2098 word SBR4 :1; /* SCI baud rate Bit 4 */
\r
2099 word SBR5 :1; /* SCI baud rate Bit 5 */
\r
2100 word SBR6 :1; /* SCI baud rate Bit 6 */
\r
2101 word SBR7 :1; /* SCI baud rate Bit 7 */
\r
2102 word SBR8 :1; /* SCI baud rate Bit 8 */
\r
2103 word SBR9 :1; /* SCI baud rate Bit 9 */
\r
2104 word SBR10 :1; /* SCI baud rate Bit 10 */
\r
2105 word SBR11 :1; /* SCI baud rate Bit 11 */
\r
2106 word SBR12 :1; /* SCI baud rate Bit 12 */
\r
2118 extern volatile SCIBDSTR _SCIBD @(REG_BASE + 0x000000C8);
\r
2119 #define SCIBD _SCIBD.Word
\r
2120 #define SCIBD_SBR0 _SCIBD.Bits.SBR0
\r
2121 #define SCIBD_SBR1 _SCIBD.Bits.SBR1
\r
2122 #define SCIBD_SBR2 _SCIBD.Bits.SBR2
\r
2123 #define SCIBD_SBR3 _SCIBD.Bits.SBR3
\r
2124 #define SCIBD_SBR4 _SCIBD.Bits.SBR4
\r
2125 #define SCIBD_SBR5 _SCIBD.Bits.SBR5
\r
2126 #define SCIBD_SBR6 _SCIBD.Bits.SBR6
\r
2127 #define SCIBD_SBR7 _SCIBD.Bits.SBR7
\r
2128 #define SCIBD_SBR8 _SCIBD.Bits.SBR8
\r
2129 #define SCIBD_SBR9 _SCIBD.Bits.SBR9
\r
2130 #define SCIBD_SBR10 _SCIBD.Bits.SBR10
\r
2131 #define SCIBD_SBR11 _SCIBD.Bits.SBR11
\r
2132 #define SCIBD_SBR12 _SCIBD.Bits.SBR12
\r
2133 #define SCIBD_SBR _SCIBD.MergedBits.grpSBR
\r
2136 /*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000EC ***/
\r
2139 /* Overlapped registers: */
\r
2141 /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000EC ***/
\r
2148 #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte
\r
2149 #define PWMCNT0_BIT _PWMCNT01.Overlap_STR.PWMCNT0STR.MergedBits.grpBIT
\r
2151 /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000ED ***/
\r
2158 #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte
\r
2159 #define PWMCNT1_BIT _PWMCNT01.Overlap_STR.PWMCNT1STR.MergedBits.grpBIT
\r
2167 extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000EC);
\r
2168 #define PWMCNT01 _PWMCNT01.Word
\r
2169 #define PWMCNT01_BIT _PWMCNT01.MergedBits.grpBIT
\r
2172 /*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000EE ***/
\r
2175 /* Overlapped registers: */
\r
2177 /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000EE ***/
\r
2184 #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte
\r
2185 #define PWMCNT2_BIT _PWMCNT23.Overlap_STR.PWMCNT2STR.MergedBits.grpBIT
\r
2187 /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000EF ***/
\r
2194 #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte
\r
2195 #define PWMCNT3_BIT _PWMCNT23.Overlap_STR.PWMCNT3STR.MergedBits.grpBIT
\r
2203 extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000EE);
\r
2204 #define PWMCNT23 _PWMCNT23.Word
\r
2205 #define PWMCNT23_BIT _PWMCNT23.MergedBits.grpBIT
\r
2208 /*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000F0 ***/
\r
2211 /* Overlapped registers: */
\r
2213 /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000F0 ***/
\r
2220 #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte
\r
2221 #define PWMCNT4_BIT _PWMCNT45.Overlap_STR.PWMCNT4STR.MergedBits.grpBIT
\r
2223 /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000F1 ***/
\r
2230 #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte
\r
2231 #define PWMCNT5_BIT _PWMCNT45.Overlap_STR.PWMCNT5STR.MergedBits.grpBIT
\r
2239 extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000F0);
\r
2240 #define PWMCNT45 _PWMCNT45.Word
\r
2241 #define PWMCNT45_BIT _PWMCNT45.MergedBits.grpBIT
\r
2244 /*** PWMPER01 - PWM Channel Period 01 Register; 0x000000F2 ***/
\r
2247 /* Overlapped registers: */
\r
2249 /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000F2 ***/
\r
2256 #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte
\r
2257 #define PWMPER0_BIT _PWMPER01.Overlap_STR.PWMPER0STR.MergedBits.grpBIT
\r
2259 /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000F3 ***/
\r
2266 #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte
\r
2267 #define PWMPER1_BIT _PWMPER01.Overlap_STR.PWMPER1STR.MergedBits.grpBIT
\r
2275 extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000F2);
\r
2276 #define PWMPER01 _PWMPER01.Word
\r
2277 #define PWMPER01_BIT _PWMPER01.MergedBits.grpBIT
\r
2280 /*** PWMPER23 - PWM Channel Period 23 Register; 0x000000F4 ***/
\r
2283 /* Overlapped registers: */
\r
2285 /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000F4 ***/
\r
2292 #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte
\r
2293 #define PWMPER2_BIT _PWMPER23.Overlap_STR.PWMPER2STR.MergedBits.grpBIT
\r
2295 /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000F5 ***/
\r
2302 #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte
\r
2303 #define PWMPER3_BIT _PWMPER23.Overlap_STR.PWMPER3STR.MergedBits.grpBIT
\r
2311 extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000F4);
\r
2312 #define PWMPER23 _PWMPER23.Word
\r
2313 #define PWMPER23_BIT _PWMPER23.MergedBits.grpBIT
\r
2316 /*** PWMPER45 - PWM Channel Period 45 Register; 0x000000F6 ***/
\r
2319 /* Overlapped registers: */
\r
2321 /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000F6 ***/
\r
2328 #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte
\r
2329 #define PWMPER4_BIT _PWMPER45.Overlap_STR.PWMPER4STR.MergedBits.grpBIT
\r
2331 /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000F7 ***/
\r
2338 #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte
\r
2339 #define PWMPER5_BIT _PWMPER45.Overlap_STR.PWMPER5STR.MergedBits.grpBIT
\r
2347 extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000F6);
\r
2348 #define PWMPER45 _PWMPER45.Word
\r
2349 #define PWMPER45_BIT _PWMPER45.MergedBits.grpBIT
\r
2352 /*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000F8 ***/
\r
2355 /* Overlapped registers: */
\r
2357 /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000F8 ***/
\r
2364 #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte
\r
2365 #define PWMDTY0_BIT _PWMDTY01.Overlap_STR.PWMDTY0STR.MergedBits.grpBIT
\r
2367 /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000F9 ***/
\r
2374 #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte
\r
2375 #define PWMDTY1_BIT _PWMDTY01.Overlap_STR.PWMDTY1STR.MergedBits.grpBIT
\r
2383 extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000F8);
\r
2384 #define PWMDTY01 _PWMDTY01.Word
\r
2385 #define PWMDTY01_BIT _PWMDTY01.MergedBits.grpBIT
\r
2388 /*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000FA ***/
\r
2391 /* Overlapped registers: */
\r
2393 /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000FA ***/
\r
2400 #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte
\r
2401 #define PWMDTY2_BIT _PWMDTY23.Overlap_STR.PWMDTY2STR.MergedBits.grpBIT
\r
2403 /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000FB ***/
\r
2410 #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte
\r
2411 #define PWMDTY3_BIT _PWMDTY23.Overlap_STR.PWMDTY3STR.MergedBits.grpBIT
\r
2419 extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000FA);
\r
2420 #define PWMDTY23 _PWMDTY23.Word
\r
2421 #define PWMDTY23_BIT _PWMDTY23.MergedBits.grpBIT
\r
2424 /*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000FC ***/
\r
2427 /* Overlapped registers: */
\r
2429 /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000FC ***/
\r
2436 #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte
\r
2437 #define PWMDTY4_BIT _PWMDTY45.Overlap_STR.PWMDTY4STR.MergedBits.grpBIT
\r
2439 /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000FD ***/
\r
2446 #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte
\r
2447 #define PWMDTY5_BIT _PWMDTY45.Overlap_STR.PWMDTY5STR.MergedBits.grpBIT
\r
2455 extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000FC);
\r
2456 #define PWMDTY45 _PWMDTY45.Word
\r
2457 #define PWMDTY45_BIT _PWMDTY45.MergedBits.grpBIT
\r
2460 /*** PORTE - Port E Register; 0x00000008 ***/
\r
2464 byte BIT0 :1; /* Port E Bit 0 */
\r
2465 byte BIT1 :1; /* Port E Bit 1 */
\r
2466 byte BIT2 :1; /* Port E Bit 2 */
\r
2467 byte BIT3 :1; /* Port E Bit 3 */
\r
2468 byte BIT4 :1; /* Port E Bit 4 */
\r
2469 byte BIT5 :1; /* Port E Bit 5 */
\r
2470 byte BIT6 :1; /* Port E Bit 6 */
\r
2471 byte BIT7 :1; /* Port E Bit 7 */
\r
2477 extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);
\r
2478 #define PORTE _PORTE.Byte
\r
2479 #define PORTE_BIT0 _PORTE.Bits.BIT0
\r
2480 #define PORTE_BIT1 _PORTE.Bits.BIT1
\r
2481 #define PORTE_BIT2 _PORTE.Bits.BIT2
\r
2482 #define PORTE_BIT3 _PORTE.Bits.BIT3
\r
2483 #define PORTE_BIT4 _PORTE.Bits.BIT4
\r
2484 #define PORTE_BIT5 _PORTE.Bits.BIT5
\r
2485 #define PORTE_BIT6 _PORTE.Bits.BIT6
\r
2486 #define PORTE_BIT7 _PORTE.Bits.BIT7
\r
2487 #define PORTE_BIT _PORTE.MergedBits.grpBIT
\r
2490 /*** DDRE - Port E Data Direction Register; 0x00000009 ***/
\r
2496 byte BIT2 :1; /* Data Direction Port A Bit 2 */
\r
2497 byte BIT3 :1; /* Data Direction Port A Bit 3 */
\r
2498 byte BIT4 :1; /* Data Direction Port A Bit 4 */
\r
2499 byte BIT5 :1; /* Data Direction Port A Bit 5 */
\r
2500 byte BIT6 :1; /* Data Direction Port A Bit 6 */
\r
2501 byte BIT7 :1; /* Data Direction Port A Bit 7 */
\r
2509 extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);
\r
2510 #define DDRE _DDRE.Byte
\r
2511 #define DDRE_BIT2 _DDRE.Bits.BIT2
\r
2512 #define DDRE_BIT3 _DDRE.Bits.BIT3
\r
2513 #define DDRE_BIT4 _DDRE.Bits.BIT4
\r
2514 #define DDRE_BIT5 _DDRE.Bits.BIT5
\r
2515 #define DDRE_BIT6 _DDRE.Bits.BIT6
\r
2516 #define DDRE_BIT7 _DDRE.Bits.BIT7
\r
2517 #define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2
\r
2518 #define DDRE_BIT DDRE_BIT_2
\r
2521 /*** PEAR - Port E Assignment Register; 0x0000000A ***/
\r
2527 byte RDWE :1; /* Read / Write Enable */
\r
2528 byte LSTRE :1; /* Low Strobe (LSTRB) Enable */
\r
2529 byte NECLK :1; /* No External E Clock */
\r
2530 byte PIPOE :1; /* Pipe Status Signal Output Enable */
\r
2532 byte NOACCE :1; /* CPU No Access Output Enable */
\r
2535 extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);
\r
2536 #define PEAR _PEAR.Byte
\r
2537 #define PEAR_RDWE _PEAR.Bits.RDWE
\r
2538 #define PEAR_LSTRE _PEAR.Bits.LSTRE
\r
2539 #define PEAR_NECLK _PEAR.Bits.NECLK
\r
2540 #define PEAR_PIPOE _PEAR.Bits.PIPOE
\r
2541 #define PEAR_NOACCE _PEAR.Bits.NOACCE
\r
2544 /*** MODE - Mode Register; 0x0000000B ***/
\r
2548 byte EME :1; /* Emulate Port E */
\r
2549 byte EMK :1; /* Emulate Port K */
\r
2551 byte IVIS :1; /* Internal Visibility */
\r
2553 byte MODA :1; /* Mode Select Bit A */
\r
2554 byte MODB :1; /* Mode Select Bit B */
\r
2555 byte MODC :1; /* Mode Select Bit C */
\r
2558 extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);
\r
2559 #define MODE _MODE.Byte
\r
2560 #define MODE_EME _MODE.Bits.EME
\r
2561 #define MODE_EMK _MODE.Bits.EMK
\r
2562 #define MODE_IVIS _MODE.Bits.IVIS
\r
2563 #define MODE_MODA _MODE.Bits.MODA
\r
2564 #define MODE_MODB _MODE.Bits.MODB
\r
2565 #define MODE_MODC _MODE.Bits.MODC
\r
2568 /*** PUCR - Pull-Up Control Register; 0x0000000C ***/
\r
2572 byte PUPAE :1; /* Pull-Up Port A Enable */
\r
2573 byte PUPBE :1; /* Pull-Up Port B Enable */
\r
2576 byte PUPEE :1; /* Pull-Up Port E Enable */
\r
2579 byte PUPKE :1; /* Pull-Up Port K Enable */
\r
2582 extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);
\r
2583 #define PUCR _PUCR.Byte
\r
2584 #define PUCR_PUPAE _PUCR.Bits.PUPAE
\r
2585 #define PUCR_PUPBE _PUCR.Bits.PUPBE
\r
2586 #define PUCR_PUPEE _PUCR.Bits.PUPEE
\r
2587 #define PUCR_PUPKE _PUCR.Bits.PUPKE
\r
2590 /*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/
\r
2594 byte RDPA :1; /* Reduced Drive of Port A */
\r
2595 byte RDPB :1; /* Reduced Drive of Port B */
\r
2598 byte RDPE :1; /* Reduced Drive of Port E */
\r
2601 byte RDPK :1; /* Reduced Drive of Port K */
\r
2604 extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);
\r
2605 #define RDRIV _RDRIV.Byte
\r
2606 #define RDRIV_RDPA _RDRIV.Bits.RDPA
\r
2607 #define RDRIV_RDPB _RDRIV.Bits.RDPB
\r
2608 #define RDRIV_RDPE _RDRIV.Bits.RDPE
\r
2609 #define RDRIV_RDPK _RDRIV.Bits.RDPK
\r
2612 /*** EBICTL - External Bus Interface Control; 0x0000000E ***/
\r
2616 byte ESTR :1; /* E Stretches */
\r
2626 extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);
\r
2627 #define EBICTL _EBICTL.Byte
\r
2628 #define EBICTL_ESTR _EBICTL.Bits.ESTR
\r
2631 /*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/
\r
2635 byte RAMHAL :1; /* Internal RAM map alignment */
\r
2638 byte RAM11 :1; /* Internal RAM map position Bit 11 */
\r
2639 byte RAM12 :1; /* Internal RAM map position Bit 12 */
\r
2640 byte RAM13 :1; /* Internal RAM map position Bit 13 */
\r
2641 byte RAM14 :1; /* Internal RAM map position Bit 14 */
\r
2642 byte RAM15 :1; /* Internal RAM map position Bit 15 */
\r
2648 byte grpRAM_11 :5;
\r
2651 extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);
\r
2652 #define INITRM _INITRM.Byte
\r
2653 #define INITRM_RAMHAL _INITRM.Bits.RAMHAL
\r
2654 #define INITRM_RAM11 _INITRM.Bits.RAM11
\r
2655 #define INITRM_RAM12 _INITRM.Bits.RAM12
\r
2656 #define INITRM_RAM13 _INITRM.Bits.RAM13
\r
2657 #define INITRM_RAM14 _INITRM.Bits.RAM14
\r
2658 #define INITRM_RAM15 _INITRM.Bits.RAM15
\r
2659 #define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11
\r
2660 #define INITRM_RAM INITRM_RAM_11
\r
2663 /*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***/
\r
2670 byte REG11 :1; /* Internal register map position REG11 */
\r
2671 byte REG12 :1; /* Internal register map position REG12 */
\r
2672 byte REG13 :1; /* Internal register map position REG13 */
\r
2673 byte REG14 :1; /* Internal register map position REG14 */
\r
2680 byte grpREG_11 :4;
\r
2684 extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);
\r
2685 #define INITRG _INITRG.Byte
\r
2686 #define INITRG_REG11 _INITRG.Bits.REG11
\r
2687 #define INITRG_REG12 _INITRG.Bits.REG12
\r
2688 #define INITRG_REG13 _INITRG.Bits.REG13
\r
2689 #define INITRG_REG14 _INITRG.Bits.REG14
\r
2690 #define INITRG_REG_11 _INITRG.MergedBits.grpREG_11
\r
2691 #define INITRG_REG INITRG_REG_11
\r
2694 /*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/
\r
2698 byte EEON :1; /* Internal EEPROM On */
\r
2702 byte EE12 :1; /* Internal EEPROM map position Bit 12 */
\r
2703 byte EE13 :1; /* Internal EEPROM map position Bit 13 */
\r
2704 byte EE14 :1; /* Internal EEPROM map position Bit 14 */
\r
2705 byte EE15 :1; /* Internal EEPROM map position Bit 15 */
\r
2715 extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);
\r
2716 #define INITEE _INITEE.Byte
\r
2717 #define INITEE_EEON _INITEE.Bits.EEON
\r
2718 #define INITEE_EE12 _INITEE.Bits.EE12
\r
2719 #define INITEE_EE13 _INITEE.Bits.EE13
\r
2720 #define INITEE_EE14 _INITEE.Bits.EE14
\r
2721 #define INITEE_EE15 _INITEE.Bits.EE15
\r
2722 #define INITEE_EE_12 _INITEE.MergedBits.grpEE_12
\r
2723 #define INITEE_EE INITEE_EE_12
\r
2726 /*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***/
\r
2730 byte ROMON :1; /* Enable Flash EEPROM */
\r
2731 byte ROMHM :1; /* Flash EEPROM only in second half of memory map */
\r
2732 byte EXSTR0 :1; /* External Access Stretch Bit 0 */
\r
2733 byte EXSTR1 :1; /* External Access Stretch Bit 1 */
\r
2749 extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013);
\r
2750 #define MISC _MISC.Byte
\r
2751 #define MISC_ROMON _MISC.Bits.ROMON
\r
2752 #define MISC_ROMHM _MISC.Bits.ROMHM
\r
2753 #define MISC_EXSTR0 _MISC.Bits.EXSTR0
\r
2754 #define MISC_EXSTR1 _MISC.Bits.EXSTR1
\r
2755 #define MISC_EXSTR _MISC.MergedBits.grpEXSTR
\r
2758 /*** MTST0 - MTST0; 0x00000014 ***/
\r
2762 byte BIT0 :1; /* MTST0 Bit 0 */
\r
2763 byte BIT1 :1; /* MTST0 Bit 1 */
\r
2764 byte BIT2 :1; /* MTST0 Bit 2 */
\r
2765 byte BIT3 :1; /* MTST0 Bit 3 */
\r
2766 byte BIT4 :1; /* MTST0 Bit 4 */
\r
2767 byte BIT5 :1; /* MTST0 Bit 5 */
\r
2768 byte BIT6 :1; /* MTST0 Bit 6 */
\r
2769 byte BIT7 :1; /* MTST0 Bit 7 */
\r
2775 extern volatile MTST0STR _MTST0 @(REG_BASE + 0x00000014);
\r
2776 #define MTST0 _MTST0.Byte
\r
2777 #define MTST0_BIT0 _MTST0.Bits.BIT0
\r
2778 #define MTST0_BIT1 _MTST0.Bits.BIT1
\r
2779 #define MTST0_BIT2 _MTST0.Bits.BIT2
\r
2780 #define MTST0_BIT3 _MTST0.Bits.BIT3
\r
2781 #define MTST0_BIT4 _MTST0.Bits.BIT4
\r
2782 #define MTST0_BIT5 _MTST0.Bits.BIT5
\r
2783 #define MTST0_BIT6 _MTST0.Bits.BIT6
\r
2784 #define MTST0_BIT7 _MTST0.Bits.BIT7
\r
2785 #define MTST0_BIT _MTST0.MergedBits.grpBIT
\r
2788 /*** ITCR - Interrupt Test Control Register; 0x00000015 ***/
\r
2792 byte ADR0 :1; /* Test register select Bit 0 */
\r
2793 byte ADR1 :1; /* Test register select Bit 1 */
\r
2794 byte ADR2 :1; /* Test register select Bit 2 */
\r
2795 byte ADR3 :1; /* Test register select Bit 3 */
\r
2796 byte WRTINT :1; /* Write to the Interrupt Test Registers */
\r
2809 extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);
\r
2810 #define ITCR _ITCR.Byte
\r
2811 #define ITCR_ADR0 _ITCR.Bits.ADR0
\r
2812 #define ITCR_ADR1 _ITCR.Bits.ADR1
\r
2813 #define ITCR_ADR2 _ITCR.Bits.ADR2
\r
2814 #define ITCR_ADR3 _ITCR.Bits.ADR3
\r
2815 #define ITCR_WRTINT _ITCR.Bits.WRTINT
\r
2816 #define ITCR_ADR _ITCR.MergedBits.grpADR
\r
2819 /*** ITEST - Interrupt Test Register; 0x00000016 ***/
\r
2823 byte INT0 :1; /* Interrupt Test Register Bit 0 */
\r
2824 byte INT2 :1; /* Interrupt Test Register Bit 1 */
\r
2825 byte INT4 :1; /* Interrupt Test Register Bit 2 */
\r
2826 byte INT6 :1; /* Interrupt Test Register Bit 3 */
\r
2827 byte INT8 :1; /* Interrupt Test Register Bit 4 */
\r
2828 byte INTA :1; /* Interrupt Test Register Bit 5 */
\r
2829 byte INTC :1; /* Interrupt Test Register Bit 6 */
\r
2830 byte INTE :1; /* Interrupt Test Register Bit 7 */
\r
2833 extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);
\r
2834 #define ITEST _ITEST.Byte
\r
2835 #define ITEST_INT0 _ITEST.Bits.INT0
\r
2836 #define ITEST_INT2 _ITEST.Bits.INT2
\r
2837 #define ITEST_INT4 _ITEST.Bits.INT4
\r
2838 #define ITEST_INT6 _ITEST.Bits.INT6
\r
2839 #define ITEST_INT8 _ITEST.Bits.INT8
\r
2840 #define ITEST_INTA _ITEST.Bits.INTA
\r
2841 #define ITEST_INTC _ITEST.Bits.INTC
\r
2842 #define ITEST_INTE _ITEST.Bits.INTE
\r
2845 /*** MTST1 - MTST1; 0x00000017 ***/
\r
2849 byte BIT0 :1; /* MTST1 Bit 0 */
\r
2850 byte BIT1 :1; /* MTST1 Bit 1 */
\r
2851 byte BIT2 :1; /* MTST1 Bit 2 */
\r
2852 byte BIT3 :1; /* MTST1 Bit 3 */
\r
2853 byte BIT4 :1; /* MTST1 Bit 4 */
\r
2854 byte BIT5 :1; /* MTST1 Bit 5 */
\r
2855 byte BIT6 :1; /* MTST1 Bit 6 */
\r
2856 byte BIT7 :1; /* MTST1 Bit 7 */
\r
2862 extern volatile MTST1STR _MTST1 @(REG_BASE + 0x00000017);
\r
2863 #define MTST1 _MTST1.Byte
\r
2864 #define MTST1_BIT0 _MTST1.Bits.BIT0
\r
2865 #define MTST1_BIT1 _MTST1.Bits.BIT1
\r
2866 #define MTST1_BIT2 _MTST1.Bits.BIT2
\r
2867 #define MTST1_BIT3 _MTST1.Bits.BIT3
\r
2868 #define MTST1_BIT4 _MTST1.Bits.BIT4
\r
2869 #define MTST1_BIT5 _MTST1.Bits.BIT5
\r
2870 #define MTST1_BIT6 _MTST1.Bits.BIT6
\r
2871 #define MTST1_BIT7 _MTST1.Bits.BIT7
\r
2872 #define MTST1_BIT _MTST1.MergedBits.grpBIT
\r
2875 /*** PARTIDH - Part ID Register High; 0x0000001A ***/
\r
2879 byte ID15 :1; /* Part ID Register Bit 15 */
\r
2880 byte ID14 :1; /* Part ID Register Bit 14 */
\r
2881 byte ID13 :1; /* Part ID Register Bit 13 */
\r
2882 byte ID12 :1; /* Part ID Register Bit 12 */
\r
2883 byte ID11 :1; /* Part ID Register Bit 11 */
\r
2884 byte ID10 :1; /* Part ID Register Bit 10 */
\r
2885 byte ID9 :1; /* Part ID Register Bit 9 */
\r
2886 byte ID8 :1; /* Part ID Register Bit 8 */
\r
2889 extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A);
\r
2890 #define PARTIDH _PARTIDH.Byte
\r
2891 #define PARTIDH_ID15 _PARTIDH.Bits.ID15
\r
2892 #define PARTIDH_ID14 _PARTIDH.Bits.ID14
\r
2893 #define PARTIDH_ID13 _PARTIDH.Bits.ID13
\r
2894 #define PARTIDH_ID12 _PARTIDH.Bits.ID12
\r
2895 #define PARTIDH_ID11 _PARTIDH.Bits.ID11
\r
2896 #define PARTIDH_ID10 _PARTIDH.Bits.ID10
\r
2897 #define PARTIDH_ID9 _PARTIDH.Bits.ID9
\r
2898 #define PARTIDH_ID8 _PARTIDH.Bits.ID8
\r
2901 /*** PARTIDL - Part ID Register Low; 0x0000001B ***/
\r
2905 byte ID0 :1; /* Part ID Register Bit 0 */
\r
2906 byte ID1 :1; /* Part ID Register Bit 1 */
\r
2907 byte ID2 :1; /* Part ID Register Bit 2 */
\r
2908 byte ID3 :1; /* Part ID Register Bit 3 */
\r
2909 byte ID4 :1; /* Part ID Register Bit 4 */
\r
2910 byte ID5 :1; /* Part ID Register Bit 5 */
\r
2911 byte ID6 :1; /* Part ID Register Bit 6 */
\r
2912 byte ID7 :1; /* Part ID Register Bit 7 */
\r
2918 extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);
\r
2919 #define PARTIDL _PARTIDL.Byte
\r
2920 #define PARTIDL_ID0 _PARTIDL.Bits.ID0
\r
2921 #define PARTIDL_ID1 _PARTIDL.Bits.ID1
\r
2922 #define PARTIDL_ID2 _PARTIDL.Bits.ID2
\r
2923 #define PARTIDL_ID3 _PARTIDL.Bits.ID3
\r
2924 #define PARTIDL_ID4 _PARTIDL.Bits.ID4
\r
2925 #define PARTIDL_ID5 _PARTIDL.Bits.ID5
\r
2926 #define PARTIDL_ID6 _PARTIDL.Bits.ID6
\r
2927 #define PARTIDL_ID7 _PARTIDL.Bits.ID7
\r
2928 #define PARTIDL_ID _PARTIDL.MergedBits.grpID
\r
2931 /*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/
\r
2935 byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */
\r
2936 byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */
\r
2937 byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */
\r
2939 byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */
\r
2940 byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */
\r
2942 byte reg_sw0 :1; /* Allocated System Register Space */
\r
2945 byte grpram_sw :3;
\r
2947 byte grpeep_sw :2;
\r
2949 byte grpreg_sw :1;
\r
2952 extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);
\r
2953 #define MEMSIZ0 _MEMSIZ0.Byte
\r
2954 #define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0
\r
2955 #define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1
\r
2956 #define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2
\r
2957 #define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0
\r
2958 #define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1
\r
2959 #define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0
\r
2960 #define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw
\r
2961 #define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw
\r
2964 /*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/
\r
2968 byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */
\r
2969 byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */
\r
2974 byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */
\r
2975 byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */
\r
2978 byte grppag_sw :2;
\r
2983 byte grprom_sw :2;
\r
2986 extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);
\r
2987 #define MEMSIZ1 _MEMSIZ1.Byte
\r
2988 #define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0
\r
2989 #define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1
\r
2990 #define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0
\r
2991 #define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1
\r
2992 #define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw
\r
2993 #define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw
\r
2996 /*** INTCR - Interrupt Control Register; 0x0000001E ***/
\r
3006 byte IRQEN :1; /* External IRQ Enable */
\r
3007 byte IRQE :1; /* IRQ Select Edge Sensitive Only */
\r
3010 extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);
\r
3011 #define INTCR _INTCR.Byte
\r
3012 #define INTCR_IRQEN _INTCR.Bits.IRQEN
\r
3013 #define INTCR_IRQE _INTCR.Bits.IRQE
\r
3016 /*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/
\r
3021 byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */
\r
3022 byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */
\r
3023 byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */
\r
3024 byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */
\r
3025 byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */
\r
3026 byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */
\r
3027 byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */
\r
3031 byte grpPSEL_1 :7;
\r
3034 extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);
\r
3035 #define HPRIO _HPRIO.Byte
\r
3036 #define HPRIO_PSEL1 _HPRIO.Bits.PSEL1
\r
3037 #define HPRIO_PSEL2 _HPRIO.Bits.PSEL2
\r
3038 #define HPRIO_PSEL3 _HPRIO.Bits.PSEL3
\r
3039 #define HPRIO_PSEL4 _HPRIO.Bits.PSEL4
\r
3040 #define HPRIO_PSEL5 _HPRIO.Bits.PSEL5
\r
3041 #define HPRIO_PSEL6 _HPRIO.Bits.PSEL6
\r
3042 #define HPRIO_PSEL7 _HPRIO.Bits.PSEL7
\r
3043 #define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1
\r
3044 #define HPRIO_PSEL HPRIO_PSEL_1
\r
3047 /*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/
\r
3055 byte BKTAG :1; /* Breakpoint on Tag */
\r
3056 byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */
\r
3057 byte BKFULL :1; /* Full Breakpoint Mode Enable */
\r
3058 byte BKEN :1; /* Breakpoint Enable */
\r
3061 extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);
\r
3062 #define BKPCT0 _BKPCT0.Byte
\r
3063 #define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG
\r
3064 #define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM
\r
3065 #define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL
\r
3066 #define BKPCT0_BKEN _BKPCT0.Bits.BKEN
\r
3069 /*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/
\r
3073 byte BK1RW :1; /* R/W Compare Value 1 */
\r
3074 byte BK1RWE :1; /* R/W Compare Enable 1 */
\r
3075 byte BK0RW :1; /* R/W Compare Value 0 */
\r
3076 byte BK0RWE :1; /* R/W Compare Enable 0 */
\r
3077 byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */
\r
3078 byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */
\r
3079 byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */
\r
3080 byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */
\r
3083 extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);
\r
3084 #define BKPCT1 _BKPCT1.Byte
\r
3085 #define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW
\r
3086 #define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE
\r
3087 #define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW
\r
3088 #define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE
\r
3089 #define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL
\r
3090 #define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH
\r
3091 #define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL
\r
3092 #define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH
\r
3095 /*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/
\r
3099 byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */
\r
3100 byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */
\r
3101 byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */
\r
3102 byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */
\r
3103 byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */
\r
3104 byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */
\r
3114 extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);
\r
3115 #define BKP0X _BKP0X.Byte
\r
3116 #define BKP0X_BK0V0 _BKP0X.Bits.BK0V0
\r
3117 #define BKP0X_BK0V1 _BKP0X.Bits.BK0V1
\r
3118 #define BKP0X_BK0V2 _BKP0X.Bits.BK0V2
\r
3119 #define BKP0X_BK0V3 _BKP0X.Bits.BK0V3
\r
3120 #define BKP0X_BK0V4 _BKP0X.Bits.BK0V4
\r
3121 #define BKP0X_BK0V5 _BKP0X.Bits.BK0V5
\r
3122 #define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V
\r
3125 /*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/
\r
3129 byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */
\r
3130 byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */
\r
3131 byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */
\r
3132 byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */
\r
3133 byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */
\r
3134 byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */
\r
3135 byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */
\r
3136 byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */
\r
3142 extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);
\r
3143 #define BKP0H _BKP0H.Byte
\r
3144 #define BKP0H_BIT8 _BKP0H.Bits.BIT8
\r
3145 #define BKP0H_BIT9 _BKP0H.Bits.BIT9
\r
3146 #define BKP0H_BIT10 _BKP0H.Bits.BIT10
\r
3147 #define BKP0H_BIT11 _BKP0H.Bits.BIT11
\r
3148 #define BKP0H_BIT12 _BKP0H.Bits.BIT12
\r
3149 #define BKP0H_BIT13 _BKP0H.Bits.BIT13
\r
3150 #define BKP0H_BIT14 _BKP0H.Bits.BIT14
\r
3151 #define BKP0H_BIT15 _BKP0H.Bits.BIT15
\r
3152 #define BKP0H_BIT_8 _BKP0H.MergedBits.grpBIT_8
\r
3153 #define BKP0H_BIT BKP0H_BIT_8
\r
3156 /*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/
\r
3160 byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */
\r
3161 byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */
\r
3162 byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */
\r
3163 byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */
\r
3164 byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */
\r
3165 byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */
\r
3166 byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */
\r
3167 byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */
\r
3173 extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);
\r
3174 #define BKP0L _BKP0L.Byte
\r
3175 #define BKP0L_BIT0 _BKP0L.Bits.BIT0
\r
3176 #define BKP0L_BIT1 _BKP0L.Bits.BIT1
\r
3177 #define BKP0L_BIT2 _BKP0L.Bits.BIT2
\r
3178 #define BKP0L_BIT3 _BKP0L.Bits.BIT3
\r
3179 #define BKP0L_BIT4 _BKP0L.Bits.BIT4
\r
3180 #define BKP0L_BIT5 _BKP0L.Bits.BIT5
\r
3181 #define BKP0L_BIT6 _BKP0L.Bits.BIT6
\r
3182 #define BKP0L_BIT7 _BKP0L.Bits.BIT7
\r
3183 #define BKP0L_BIT _BKP0L.MergedBits.grpBIT
\r
3186 /*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/
\r
3190 byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */
\r
3191 byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */
\r
3192 byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */
\r
3193 byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */
\r
3194 byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */
\r
3195 byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */
\r
3205 extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);
\r
3206 #define BKP1X _BKP1X.Byte
\r
3207 #define BKP1X_BK1V0 _BKP1X.Bits.BK1V0
\r
3208 #define BKP1X_BK1V1 _BKP1X.Bits.BK1V1
\r
3209 #define BKP1X_BK1V2 _BKP1X.Bits.BK1V2
\r
3210 #define BKP1X_BK1V3 _BKP1X.Bits.BK1V3
\r
3211 #define BKP1X_BK1V4 _BKP1X.Bits.BK1V4
\r
3212 #define BKP1X_BK1V5 _BKP1X.Bits.BK1V5
\r
3213 #define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V
\r
3216 /*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/
\r
3220 byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */
\r
3221 byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */
\r
3222 byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */
\r
3223 byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */
\r
3224 byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */
\r
3225 byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */
\r
3226 byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */
\r
3227 byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */
\r
3233 extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);
\r
3234 #define BKP1H _BKP1H.Byte
\r
3235 #define BKP1H_BIT8 _BKP1H.Bits.BIT8
\r
3236 #define BKP1H_BIT9 _BKP1H.Bits.BIT9
\r
3237 #define BKP1H_BIT10 _BKP1H.Bits.BIT10
\r
3238 #define BKP1H_BIT11 _BKP1H.Bits.BIT11
\r
3239 #define BKP1H_BIT12 _BKP1H.Bits.BIT12
\r
3240 #define BKP1H_BIT13 _BKP1H.Bits.BIT13
\r
3241 #define BKP1H_BIT14 _BKP1H.Bits.BIT14
\r
3242 #define BKP1H_BIT15 _BKP1H.Bits.BIT15
\r
3243 #define BKP1H_BIT_8 _BKP1H.MergedBits.grpBIT_8
\r
3244 #define BKP1H_BIT BKP1H_BIT_8
\r
3247 /*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/
\r
3251 byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */
\r
3252 byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */
\r
3253 byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */
\r
3254 byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */
\r
3255 byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */
\r
3256 byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */
\r
3257 byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */
\r
3258 byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */
\r
3264 extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);
\r
3265 #define BKP1L _BKP1L.Byte
\r
3266 #define BKP1L_BIT0 _BKP1L.Bits.BIT0
\r
3267 #define BKP1L_BIT1 _BKP1L.Bits.BIT1
\r
3268 #define BKP1L_BIT2 _BKP1L.Bits.BIT2
\r
3269 #define BKP1L_BIT3 _BKP1L.Bits.BIT3
\r
3270 #define BKP1L_BIT4 _BKP1L.Bits.BIT4
\r
3271 #define BKP1L_BIT5 _BKP1L.Bits.BIT5
\r
3272 #define BKP1L_BIT6 _BKP1L.Bits.BIT6
\r
3273 #define BKP1L_BIT7 _BKP1L.Bits.BIT7
\r
3274 #define BKP1L_BIT _BKP1L.MergedBits.grpBIT
\r
3277 /*** PPAGE - Page Index Register; 0x00000030 ***/
\r
3281 byte PIX0 :1; /* Page Index Register Bit 0 */
\r
3282 byte PIX1 :1; /* Page Index Register Bit 1 */
\r
3283 byte PIX2 :1; /* Page Index Register Bit 2 */
\r
3284 byte PIX3 :1; /* Page Index Register Bit 3 */
\r
3285 byte PIX4 :1; /* Page Index Register Bit 4 */
\r
3286 byte PIX5 :1; /* Page Index Register Bit 5 */
\r
3296 extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);
\r
3297 #define PPAGE _PPAGE.Byte
\r
3298 #define PPAGE_PIX0 _PPAGE.Bits.PIX0
\r
3299 #define PPAGE_PIX1 _PPAGE.Bits.PIX1
\r
3300 #define PPAGE_PIX2 _PPAGE.Bits.PIX2
\r
3301 #define PPAGE_PIX3 _PPAGE.Bits.PIX3
\r
3302 #define PPAGE_PIX4 _PPAGE.Bits.PIX4
\r
3303 #define PPAGE_PIX5 _PPAGE.Bits.PIX5
\r
3304 #define PPAGE_PIX _PPAGE.MergedBits.grpPIX
\r
3307 /*** PORTK - Port K Data Register; 0x00000032 ***/
\r
3311 byte BIT0 :1; /* Port K Bit 0, XAB14 */
\r
3312 byte BIT1 :1; /* Port K Bit 1, XAB15 */
\r
3313 byte BIT2 :1; /* Port K Bit 2, XAB16 */
\r
3314 byte BIT3 :1; /* Port K Bit 3, XAB17 */
\r
3315 byte BIT4 :1; /* Port K Bit 4, XAB18 */
\r
3316 byte BIT5 :1; /* Port K Bit 5, XAB19 */
\r
3317 byte BIT6 :1; /* Port K Bit 6 */
\r
3318 byte BIT7 :1; /* Port K Bit 7, ECS/ROMONE */
\r
3324 extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);
\r
3325 #define PORTK _PORTK.Byte
\r
3326 #define PORTK_BIT0 _PORTK.Bits.BIT0
\r
3327 #define PORTK_BIT1 _PORTK.Bits.BIT1
\r
3328 #define PORTK_BIT2 _PORTK.Bits.BIT2
\r
3329 #define PORTK_BIT3 _PORTK.Bits.BIT3
\r
3330 #define PORTK_BIT4 _PORTK.Bits.BIT4
\r
3331 #define PORTK_BIT5 _PORTK.Bits.BIT5
\r
3332 #define PORTK_BIT6 _PORTK.Bits.BIT6
\r
3333 #define PORTK_BIT7 _PORTK.Bits.BIT7
\r
3334 #define PORTK_BIT _PORTK.MergedBits.grpBIT
\r
3337 /*** DDRK - Port K Data Direction Register; 0x00000033 ***/
\r
3341 byte DDK0 :1; /* Port K Data Direction Bit 0 */
\r
3342 byte DDK1 :1; /* Port K Data Direction Bit 1 */
\r
3343 byte DDK2 :1; /* Port K Data Direction Bit 2 */
\r
3344 byte DDK3 :1; /* Port K Data Direction Bit 3 */
\r
3345 byte DDK4 :1; /* Port K Data Direction Bit 4 */
\r
3346 byte DDK5 :1; /* Port K Data Direction Bit 5 */
\r
3348 byte DDK7 :1; /* Port K Data Direction Bit 7 */
\r
3356 extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);
\r
3357 #define DDRK _DDRK.Byte
\r
3358 #define DDRK_DDK0 _DDRK.Bits.DDK0
\r
3359 #define DDRK_DDK1 _DDRK.Bits.DDK1
\r
3360 #define DDRK_DDK2 _DDRK.Bits.DDK2
\r
3361 #define DDRK_DDK3 _DDRK.Bits.DDK3
\r
3362 #define DDRK_DDK4 _DDRK.Bits.DDK4
\r
3363 #define DDRK_DDK5 _DDRK.Bits.DDK5
\r
3364 #define DDRK_DDK7 _DDRK.Bits.DDK7
\r
3365 #define DDRK_DDK _DDRK.MergedBits.grpDDK
\r
3368 /*** SYNR - CRG Synthesizer Register; 0x00000034 ***/
\r
3372 byte SYN0 :1; /* CRG Synthesizer Bit 0 */
\r
3373 byte SYN1 :1; /* CRG Synthesizer Bit 1 */
\r
3374 byte SYN2 :1; /* CRG Synthesizer Bit 2 */
\r
3375 byte SYN3 :1; /* CRG Synthesizer Bit 3 */
\r
3376 byte SYN4 :1; /* CRG Synthesizer Bit 4 */
\r
3377 byte SYN5 :1; /* CRG Synthesizer Bit 5 */
\r
3387 extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);
\r
3388 #define SYNR _SYNR.Byte
\r
3389 #define SYNR_SYN0 _SYNR.Bits.SYN0
\r
3390 #define SYNR_SYN1 _SYNR.Bits.SYN1
\r
3391 #define SYNR_SYN2 _SYNR.Bits.SYN2
\r
3392 #define SYNR_SYN3 _SYNR.Bits.SYN3
\r
3393 #define SYNR_SYN4 _SYNR.Bits.SYN4
\r
3394 #define SYNR_SYN5 _SYNR.Bits.SYN5
\r
3395 #define SYNR_SYN _SYNR.MergedBits.grpSYN
\r
3398 /*** REFDV - CRG Reference Divider Register; 0x00000035 ***/
\r
3402 byte REFDV0 :1; /* CRG Reference Divider Bit 0 */
\r
3403 byte REFDV1 :1; /* CRG Reference Divider Bit 1 */
\r
3404 byte REFDV2 :1; /* CRG Reference Divider Bit 2 */
\r
3405 byte REFDV3 :1; /* CRG Reference Divider Bit 3 */
\r
3419 extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);
\r
3420 #define REFDV _REFDV.Byte
\r
3421 #define REFDV_REFDV0 _REFDV.Bits.REFDV0
\r
3422 #define REFDV_REFDV1 _REFDV.Bits.REFDV1
\r
3423 #define REFDV_REFDV2 _REFDV.Bits.REFDV2
\r
3424 #define REFDV_REFDV3 _REFDV.Bits.REFDV3
\r
3425 #define REFDV_REFDV _REFDV.MergedBits.grpREFDV
\r
3428 /*** CTFLG - CRG Test Flags Register; 0x00000036 ***/
\r
3432 byte TOUT0 :1; /* CRG Test Flags Bit 0 */
\r
3433 byte TOUT1 :1; /* CRG Test Flags Bit 1 */
\r
3434 byte TOUT2 :1; /* CRG Test Flags Bit 2 */
\r
3435 byte TOUT3 :1; /* CRG Test Flags Bit 3 */
\r
3436 byte TOUT4 :1; /* CRG Test Flags Bit 4 */
\r
3437 byte TOUT5 :1; /* CRG Test Flags Bit 5 */
\r
3438 byte TOUT6 :1; /* CRG Test Flags Bit 6 */
\r
3439 byte TOUT7 :1; /* CRG Test Flags Bit 7 */
\r
3445 extern volatile CTFLGSTR _CTFLG @(REG_BASE + 0x00000036);
\r
3446 #define CTFLG _CTFLG.Byte
\r
3447 #define CTFLG_TOUT0 _CTFLG.Bits.TOUT0
\r
3448 #define CTFLG_TOUT1 _CTFLG.Bits.TOUT1
\r
3449 #define CTFLG_TOUT2 _CTFLG.Bits.TOUT2
\r
3450 #define CTFLG_TOUT3 _CTFLG.Bits.TOUT3
\r
3451 #define CTFLG_TOUT4 _CTFLG.Bits.TOUT4
\r
3452 #define CTFLG_TOUT5 _CTFLG.Bits.TOUT5
\r
3453 #define CTFLG_TOUT6 _CTFLG.Bits.TOUT6
\r
3454 #define CTFLG_TOUT7 _CTFLG.Bits.TOUT7
\r
3455 #define CTFLG_TOUT _CTFLG.MergedBits.grpTOUT
\r
3458 /*** CRGFLG - CRG Flags Register; 0x00000037 ***/
\r
3462 byte SCM :1; /* Self-clock mode Status */
\r
3463 byte SCMIF :1; /* Self-clock mode Interrupt Flag */
\r
3464 byte TRACK :1; /* Track Status */
\r
3465 byte LOCK :1; /* Lock Status */
\r
3466 byte LOCKIF :1; /* PLL Lock Interrupt Flag */
\r
3468 byte PORF :1; /* Power on Reset Flag */
\r
3469 byte RTIF :1; /* Real Time Interrupt Flag */
\r
3472 extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);
\r
3473 #define CRGFLG _CRGFLG.Byte
\r
3474 #define CRGFLG_SCM _CRGFLG.Bits.SCM
\r
3475 #define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF
\r
3476 #define CRGFLG_TRACK _CRGFLG.Bits.TRACK
\r
3477 #define CRGFLG_LOCK _CRGFLG.Bits.LOCK
\r
3478 #define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF
\r
3479 #define CRGFLG_PORF _CRGFLG.Bits.PORF
\r
3480 #define CRGFLG_RTIF _CRGFLG.Bits.RTIF
\r
3483 /*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/
\r
3488 byte SCMIE :1; /* Self-clock mode Interrupt Enable */
\r
3491 byte LOCKIE :1; /* Lock Interrupt Enable */
\r
3494 byte RTIE :1; /* Real Time Interrupt Enable */
\r
3497 extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);
\r
3498 #define CRGINT _CRGINT.Byte
\r
3499 #define CRGINT_SCMIE _CRGINT.Bits.SCMIE
\r
3500 #define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE
\r
3501 #define CRGINT_RTIE _CRGINT.Bits.RTIE
\r
3504 /*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/
\r
3508 byte COPWAI :1; /* COP stops in WAIT mode */
\r
3509 byte RTIWAI :1; /* RTI stops in WAIT mode */
\r
3510 byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */
\r
3511 byte PLLWAI :1; /* PLL stops in WAIT mode */
\r
3512 byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */
\r
3513 byte SYSWAI :1; /* System clocks stop in WAIT mode */
\r
3514 byte PSTP :1; /* Pseudo Stop */
\r
3515 byte PLLSEL :1; /* PLL selected for system clock */
\r
3518 extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);
\r
3519 #define CLKSEL _CLKSEL.Byte
\r
3520 #define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI
\r
3521 #define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI
\r
3522 #define CLKSEL_CWAI _CLKSEL.Bits.CWAI
\r
3523 #define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI
\r
3524 #define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI
\r
3525 #define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI
\r
3526 #define CLKSEL_PSTP _CLKSEL.Bits.PSTP
\r
3527 #define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL
\r
3530 /*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/
\r
3534 byte SCME :1; /* Self-clock mode enable */
\r
3538 byte ACQ :1; /* Acquisition */
\r
3539 byte AUTO :1; /* Automatic Bandwidth Control */
\r
3540 byte PLLON :1; /* Phase Lock Loop On */
\r
3541 byte CME :1; /* Crystal Monitor Enable */
\r
3544 extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);
\r
3545 #define PLLCTL _PLLCTL.Byte
\r
3546 #define PLLCTL_SCME _PLLCTL.Bits.SCME
\r
3547 #define PLLCTL_ACQ _PLLCTL.Bits.ACQ
\r
3548 #define PLLCTL_AUTO _PLLCTL.Bits.AUTO
\r
3549 #define PLLCTL_PLLON _PLLCTL.Bits.PLLON
\r
3550 #define PLLCTL_CME _PLLCTL.Bits.CME
\r
3553 /*** RTICTL - CRG RTI Control Register; 0x0000003B ***/
\r
3557 byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select */
\r
3558 byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select */
\r
3559 byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select */
\r
3560 byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select */
\r
3561 byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select */
\r
3562 byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select */
\r
3563 byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select */
\r
3571 extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);
\r
3572 #define RTICTL _RTICTL.Byte
\r
3573 #define RTICTL_RTR0 _RTICTL.Bits.RTR0
\r
3574 #define RTICTL_RTR1 _RTICTL.Bits.RTR1
\r
3575 #define RTICTL_RTR2 _RTICTL.Bits.RTR2
\r
3576 #define RTICTL_RTR3 _RTICTL.Bits.RTR3
\r
3577 #define RTICTL_RTR4 _RTICTL.Bits.RTR4
\r
3578 #define RTICTL_RTR5 _RTICTL.Bits.RTR5
\r
3579 #define RTICTL_RTR6 _RTICTL.Bits.RTR6
\r
3580 #define RTICTL_RTR _RTICTL.MergedBits.grpRTR
\r
3583 /*** COPCTL - CRG COP Control Register; 0x0000003C ***/
\r
3587 byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */
\r
3588 byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */
\r
3589 byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */
\r
3593 byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */
\r
3594 byte WCOP :1; /* Window COP mode */
\r
3605 extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);
\r
3606 #define COPCTL _COPCTL.Byte
\r
3607 #define COPCTL_CR0 _COPCTL.Bits.CR0
\r
3608 #define COPCTL_CR1 _COPCTL.Bits.CR1
\r
3609 #define COPCTL_CR2 _COPCTL.Bits.CR2
\r
3610 #define COPCTL_RSBCK _COPCTL.Bits.RSBCK
\r
3611 #define COPCTL_WCOP _COPCTL.Bits.WCOP
\r
3612 #define COPCTL_CR _COPCTL.MergedBits.grpCR
\r
3615 /*** CTCTL - CRG Test Control Register; 0x0000003E ***/
\r
3619 byte TCTL0 :1; /* CRG Test Control Bit 0 */
\r
3620 byte TCTL1 :1; /* CRG Test Control Bit 1 */
\r
3621 byte TCTL2 :1; /* CRG Test Control Bit 2 */
\r
3622 byte TCTL3 :1; /* CRG Test Control Bit 3 */
\r
3623 byte TCTL4 :1; /* CRG Test Control Bit 4 */
\r
3624 byte TCTL5 :1; /* CRG Test Control Bit 5 */
\r
3625 byte TCTL6 :1; /* CRG Test Control Bit 6 */
\r
3626 byte TCTL7 :1; /* CRG Test Control Bit 7 */
\r
3632 extern volatile CTCTLSTR _CTCTL @(REG_BASE + 0x0000003E);
\r
3633 #define CTCTL _CTCTL.Byte
\r
3634 #define CTCTL_TCTL0 _CTCTL.Bits.TCTL0
\r
3635 #define CTCTL_TCTL1 _CTCTL.Bits.TCTL1
\r
3636 #define CTCTL_TCTL2 _CTCTL.Bits.TCTL2
\r
3637 #define CTCTL_TCTL3 _CTCTL.Bits.TCTL3
\r
3638 #define CTCTL_TCTL4 _CTCTL.Bits.TCTL4
\r
3639 #define CTCTL_TCTL5 _CTCTL.Bits.TCTL5
\r
3640 #define CTCTL_TCTL6 _CTCTL.Bits.TCTL6
\r
3641 #define CTCTL_TCTL7 _CTCTL.Bits.TCTL7
\r
3642 #define CTCTL_TCTL _CTCTL.MergedBits.grpTCTL
\r
3645 /*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/
\r
3649 byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */
\r
3650 byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */
\r
3651 byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */
\r
3652 byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */
\r
3653 byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */
\r
3654 byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */
\r
3655 byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */
\r
3656 byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */
\r
3662 extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);
\r
3663 #define ARMCOP _ARMCOP.Byte
\r
3664 #define ARMCOP_BIT0 _ARMCOP.Bits.BIT0
\r
3665 #define ARMCOP_BIT1 _ARMCOP.Bits.BIT1
\r
3666 #define ARMCOP_BIT2 _ARMCOP.Bits.BIT2
\r
3667 #define ARMCOP_BIT3 _ARMCOP.Bits.BIT3
\r
3668 #define ARMCOP_BIT4 _ARMCOP.Bits.BIT4
\r
3669 #define ARMCOP_BIT5 _ARMCOP.Bits.BIT5
\r
3670 #define ARMCOP_BIT6 _ARMCOP.Bits.BIT6
\r
3671 #define ARMCOP_BIT7 _ARMCOP.Bits.BIT7
\r
3672 #define ARMCOP_BIT _ARMCOP.MergedBits.grpBIT
\r
3675 /*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/
\r
3679 byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */
\r
3680 byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */
\r
3681 byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */
\r
3682 byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */
\r
3683 byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */
\r
3684 byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */
\r
3685 byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */
\r
3686 byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */
\r
3692 extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);
\r
3693 #define TIOS _TIOS.Byte
\r
3694 #define TIOS_IOS0 _TIOS.Bits.IOS0
\r
3695 #define TIOS_IOS1 _TIOS.Bits.IOS1
\r
3696 #define TIOS_IOS2 _TIOS.Bits.IOS2
\r
3697 #define TIOS_IOS3 _TIOS.Bits.IOS3
\r
3698 #define TIOS_IOS4 _TIOS.Bits.IOS4
\r
3699 #define TIOS_IOS5 _TIOS.Bits.IOS5
\r
3700 #define TIOS_IOS6 _TIOS.Bits.IOS6
\r
3701 #define TIOS_IOS7 _TIOS.Bits.IOS7
\r
3702 #define TIOS_IOS _TIOS.MergedBits.grpIOS
\r
3705 /*** CFORC - Timer Compare Force Register; 0x00000041 ***/
\r
3709 byte FOC0 :1; /* Force Output Compare Action for Channel 0 */
\r
3710 byte FOC1 :1; /* Force Output Compare Action for Channel 1 */
\r
3711 byte FOC2 :1; /* Force Output Compare Action for Channel 2 */
\r
3712 byte FOC3 :1; /* Force Output Compare Action for Channel 3 */
\r
3713 byte FOC4 :1; /* Force Output Compare Action for Channel 4 */
\r
3714 byte FOC5 :1; /* Force Output Compare Action for Channel 5 */
\r
3715 byte FOC6 :1; /* Force Output Compare Action for Channel 6 */
\r
3716 byte FOC7 :1; /* Force Output Compare Action for Channel 7 */
\r
3722 extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);
\r
3723 #define CFORC _CFORC.Byte
\r
3724 #define CFORC_FOC0 _CFORC.Bits.FOC0
\r
3725 #define CFORC_FOC1 _CFORC.Bits.FOC1
\r
3726 #define CFORC_FOC2 _CFORC.Bits.FOC2
\r
3727 #define CFORC_FOC3 _CFORC.Bits.FOC3
\r
3728 #define CFORC_FOC4 _CFORC.Bits.FOC4
\r
3729 #define CFORC_FOC5 _CFORC.Bits.FOC5
\r
3730 #define CFORC_FOC6 _CFORC.Bits.FOC6
\r
3731 #define CFORC_FOC7 _CFORC.Bits.FOC7
\r
3732 #define CFORC_FOC _CFORC.MergedBits.grpFOC
\r
3735 /*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/
\r
3739 byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */
\r
3740 byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */
\r
3741 byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */
\r
3742 byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */
\r
3743 byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */
\r
3744 byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */
\r
3745 byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */
\r
3746 byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */
\r
3752 extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);
\r
3753 #define OC7M _OC7M.Byte
\r
3754 #define OC7M_OC7M0 _OC7M.Bits.OC7M0
\r
3755 #define OC7M_OC7M1 _OC7M.Bits.OC7M1
\r
3756 #define OC7M_OC7M2 _OC7M.Bits.OC7M2
\r
3757 #define OC7M_OC7M3 _OC7M.Bits.OC7M3
\r
3758 #define OC7M_OC7M4 _OC7M.Bits.OC7M4
\r
3759 #define OC7M_OC7M5 _OC7M.Bits.OC7M5
\r
3760 #define OC7M_OC7M6 _OC7M.Bits.OC7M6
\r
3761 #define OC7M_OC7M7 _OC7M.Bits.OC7M7
\r
3762 #define OC7M_OC7M _OC7M.MergedBits.grpOC7M
\r
3765 /*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/
\r
3769 byte OC7D0 :1; /* Output Compare 7 Bit 0 */
\r
3770 byte OC7D1 :1; /* Output Compare 7 Bit 1 */
\r
3771 byte OC7D2 :1; /* Output Compare 7 Bit 2 */
\r
3772 byte OC7D3 :1; /* Output Compare 7 Bit 3 */
\r
3773 byte OC7D4 :1; /* Output Compare 7 Bit 4 */
\r
3774 byte OC7D5 :1; /* Output Compare 7 Bit 5 */
\r
3775 byte OC7D6 :1; /* Output Compare 7 Bit 6 */
\r
3776 byte OC7D7 :1; /* Output Compare 7 Bit 7 */
\r
3782 extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);
\r
3783 #define OC7D _OC7D.Byte
\r
3784 #define OC7D_OC7D0 _OC7D.Bits.OC7D0
\r
3785 #define OC7D_OC7D1 _OC7D.Bits.OC7D1
\r
3786 #define OC7D_OC7D2 _OC7D.Bits.OC7D2
\r
3787 #define OC7D_OC7D3 _OC7D.Bits.OC7D3
\r
3788 #define OC7D_OC7D4 _OC7D.Bits.OC7D4
\r
3789 #define OC7D_OC7D5 _OC7D.Bits.OC7D5
\r
3790 #define OC7D_OC7D6 _OC7D.Bits.OC7D6
\r
3791 #define OC7D_OC7D7 _OC7D.Bits.OC7D7
\r
3792 #define OC7D_OC7D _OC7D.MergedBits.grpOC7D
\r
3795 /*** TSCR1 - Timer System Control Register1; 0x00000046 ***/
\r
3803 byte TFFCA :1; /* Timer Fast Flag Clear All */
\r
3804 byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */
\r
3805 byte TSWAI :1; /* Timer Module Stops While in Wait */
\r
3806 byte TEN :1; /* Timer Enable */
\r
3809 extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);
\r
3810 #define TSCR1 _TSCR1.Byte
\r
3811 #define TSCR1_TFFCA _TSCR1.Bits.TFFCA
\r
3812 #define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ
\r
3813 #define TSCR1_TSWAI _TSCR1.Bits.TSWAI
\r
3814 #define TSCR1_TEN _TSCR1.Bits.TEN
\r
3817 /*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/
\r
3821 byte TOV0 :1; /* Toggle On Overflow Bit 0 */
\r
3822 byte TOV1 :1; /* Toggle On Overflow Bit 1 */
\r
3823 byte TOV2 :1; /* Toggle On Overflow Bit 2 */
\r
3824 byte TOV3 :1; /* Toggle On Overflow Bit 3 */
\r
3825 byte TOV4 :1; /* Toggle On Overflow Bit 4 */
\r
3826 byte TOV5 :1; /* Toggle On Overflow Bit 5 */
\r
3827 byte TOV6 :1; /* Toggle On Overflow Bit 6 */
\r
3828 byte TOV7 :1; /* Toggle On Overflow Bit 7 */
\r
3834 extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);
\r
3835 #define TTOV _TTOV.Byte
\r
3836 #define TTOV_TOV0 _TTOV.Bits.TOV0
\r
3837 #define TTOV_TOV1 _TTOV.Bits.TOV1
\r
3838 #define TTOV_TOV2 _TTOV.Bits.TOV2
\r
3839 #define TTOV_TOV3 _TTOV.Bits.TOV3
\r
3840 #define TTOV_TOV4 _TTOV.Bits.TOV4
\r
3841 #define TTOV_TOV5 _TTOV.Bits.TOV5
\r
3842 #define TTOV_TOV6 _TTOV.Bits.TOV6
\r
3843 #define TTOV_TOV7 _TTOV.Bits.TOV7
\r
3844 #define TTOV_TOV _TTOV.MergedBits.grpTOV
\r
3847 /*** TCTL1 - Timer Control Register 1; 0x00000048 ***/
\r
3851 byte OL4 :1; /* Output Level Bit 4 */
\r
3852 byte OM4 :1; /* Output Mode Bit 4 */
\r
3853 byte OL5 :1; /* Output Level Bit 5 */
\r
3854 byte OM5 :1; /* Output Mode Bit 5 */
\r
3855 byte OL6 :1; /* Output Level Bit 6 */
\r
3856 byte OM6 :1; /* Output Mode Bit 6 */
\r
3857 byte OL7 :1; /* Output Level Bit 7 */
\r
3858 byte OM7 :1; /* Output Mode Bit 7 */
\r
3861 extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);
\r
3862 #define TCTL1 _TCTL1.Byte
\r
3863 #define TCTL1_OL4 _TCTL1.Bits.OL4
\r
3864 #define TCTL1_OM4 _TCTL1.Bits.OM4
\r
3865 #define TCTL1_OL5 _TCTL1.Bits.OL5
\r
3866 #define TCTL1_OM5 _TCTL1.Bits.OM5
\r
3867 #define TCTL1_OL6 _TCTL1.Bits.OL6
\r
3868 #define TCTL1_OM6 _TCTL1.Bits.OM6
\r
3869 #define TCTL1_OL7 _TCTL1.Bits.OL7
\r
3870 #define TCTL1_OM7 _TCTL1.Bits.OM7
\r
3873 /*** TCTL2 - Timer Control Register 2; 0x00000049 ***/
\r
3877 byte OL0 :1; /* Output Level Bit 0 */
\r
3878 byte OM0 :1; /* Output Mode Bit 0 */
\r
3879 byte OL1 :1; /* Output Level Bit 1 */
\r
3880 byte OM1 :1; /* Output Mode Bit 1 */
\r
3881 byte OL2 :1; /* Output Level Bit 2 */
\r
3882 byte OM2 :1; /* Output Mode Bit 2 */
\r
3883 byte OL3 :1; /* Output Level Bit 3 */
\r
3884 byte OM3 :1; /* Output Mode Bit 3 */
\r
3887 extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);
\r
3888 #define TCTL2 _TCTL2.Byte
\r
3889 #define TCTL2_OL0 _TCTL2.Bits.OL0
\r
3890 #define TCTL2_OM0 _TCTL2.Bits.OM0
\r
3891 #define TCTL2_OL1 _TCTL2.Bits.OL1
\r
3892 #define TCTL2_OM1 _TCTL2.Bits.OM1
\r
3893 #define TCTL2_OL2 _TCTL2.Bits.OL2
\r
3894 #define TCTL2_OM2 _TCTL2.Bits.OM2
\r
3895 #define TCTL2_OL3 _TCTL2.Bits.OL3
\r
3896 #define TCTL2_OM3 _TCTL2.Bits.OM3
\r
3899 /*** TCTL3 - Timer Control Register 3; 0x0000004A ***/
\r
3903 byte EDG4A :1; /* Input Capture Edge Control 4A */
\r
3904 byte EDG4B :1; /* Input Capture Edge Control 4B */
\r
3905 byte EDG5A :1; /* Input Capture Edge Control 5A */
\r
3906 byte EDG5B :1; /* Input Capture Edge Control 5B */
\r
3907 byte EDG6A :1; /* Input Capture Edge Control 6A */
\r
3908 byte EDG6B :1; /* Input Capture Edge Control 6B */
\r
3909 byte EDG7A :1; /* Input Capture Edge Control 7A */
\r
3910 byte EDG7B :1; /* Input Capture Edge Control 7B */
\r
3913 extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);
\r
3914 #define TCTL3 _TCTL3.Byte
\r
3915 #define TCTL3_EDG4A _TCTL3.Bits.EDG4A
\r
3916 #define TCTL3_EDG4B _TCTL3.Bits.EDG4B
\r
3917 #define TCTL3_EDG5A _TCTL3.Bits.EDG5A
\r
3918 #define TCTL3_EDG5B _TCTL3.Bits.EDG5B
\r
3919 #define TCTL3_EDG6A _TCTL3.Bits.EDG6A
\r
3920 #define TCTL3_EDG6B _TCTL3.Bits.EDG6B
\r
3921 #define TCTL3_EDG7A _TCTL3.Bits.EDG7A
\r
3922 #define TCTL3_EDG7B _TCTL3.Bits.EDG7B
\r
3925 /*** TCTL4 - Timer Control Register 4; 0x0000004B ***/
\r
3929 byte EDG0A :1; /* Input Capture Edge Control 0A */
\r
3930 byte EDG0B :1; /* Input Capture Edge Control 0B */
\r
3931 byte EDG1A :1; /* Input Capture Edge Control 1A */
\r
3932 byte EDG1B :1; /* Input Capture Edge Control 1B */
\r
3933 byte EDG2A :1; /* Input Capture Edge Control 2A */
\r
3934 byte EDG2B :1; /* Input Capture Edge Control 2B */
\r
3935 byte EDG3A :1; /* Input Capture Edge Control 3A */
\r
3936 byte EDG3B :1; /* Input Capture Edge Control 3B */
\r
3939 extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);
\r
3940 #define TCTL4 _TCTL4.Byte
\r
3941 #define TCTL4_EDG0A _TCTL4.Bits.EDG0A
\r
3942 #define TCTL4_EDG0B _TCTL4.Bits.EDG0B
\r
3943 #define TCTL4_EDG1A _TCTL4.Bits.EDG1A
\r
3944 #define TCTL4_EDG1B _TCTL4.Bits.EDG1B
\r
3945 #define TCTL4_EDG2A _TCTL4.Bits.EDG2A
\r
3946 #define TCTL4_EDG2B _TCTL4.Bits.EDG2B
\r
3947 #define TCTL4_EDG3A _TCTL4.Bits.EDG3A
\r
3948 #define TCTL4_EDG3B _TCTL4.Bits.EDG3B
\r
3951 /*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/
\r
3955 byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */
\r
3956 byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */
\r
3957 byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */
\r
3958 byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */
\r
3959 byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */
\r
3960 byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */
\r
3961 byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */
\r
3962 byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */
\r
3965 extern volatile TIESTR _TIE @(REG_BASE + 0x0000004C);
\r
3966 #define TIE _TIE.Byte
\r
3967 #define TIE_C0I _TIE.Bits.C0I
\r
3968 #define TIE_C1I _TIE.Bits.C1I
\r
3969 #define TIE_C2I _TIE.Bits.C2I
\r
3970 #define TIE_C3I _TIE.Bits.C3I
\r
3971 #define TIE_C4I _TIE.Bits.C4I
\r
3972 #define TIE_C5I _TIE.Bits.C5I
\r
3973 #define TIE_C6I _TIE.Bits.C6I
\r
3974 #define TIE_C7I _TIE.Bits.C7I
\r
3977 /*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/
\r
3981 byte PR0 :1; /* Timer Prescaler Select Bit 0 */
\r
3982 byte PR1 :1; /* Timer Prescaler Select Bit 1 */
\r
3983 byte PR2 :1; /* Timer Prescaler Select Bit 2 */
\r
3984 byte TCRE :1; /* Timer Counter Reset Enable */
\r
3988 byte TOI :1; /* Timer Overflow Interrupt Enable */
\r
3999 extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);
\r
4000 #define TSCR2 _TSCR2.Byte
\r
4001 #define TSCR2_PR0 _TSCR2.Bits.PR0
\r
4002 #define TSCR2_PR1 _TSCR2.Bits.PR1
\r
4003 #define TSCR2_PR2 _TSCR2.Bits.PR2
\r
4004 #define TSCR2_TCRE _TSCR2.Bits.TCRE
\r
4005 #define TSCR2_TOI _TSCR2.Bits.TOI
\r
4006 #define TSCR2_PR _TSCR2.MergedBits.grpPR
\r
4009 /*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/
\r
4013 byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */
\r
4014 byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */
\r
4015 byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */
\r
4016 byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */
\r
4017 byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */
\r
4018 byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */
\r
4019 byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */
\r
4020 byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */
\r
4023 extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);
\r
4024 #define TFLG1 _TFLG1.Byte
\r
4025 #define TFLG1_C0F _TFLG1.Bits.C0F
\r
4026 #define TFLG1_C1F _TFLG1.Bits.C1F
\r
4027 #define TFLG1_C2F _TFLG1.Bits.C2F
\r
4028 #define TFLG1_C3F _TFLG1.Bits.C3F
\r
4029 #define TFLG1_C4F _TFLG1.Bits.C4F
\r
4030 #define TFLG1_C5F _TFLG1.Bits.C5F
\r
4031 #define TFLG1_C6F _TFLG1.Bits.C6F
\r
4032 #define TFLG1_C7F _TFLG1.Bits.C7F
\r
4035 /*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/
\r
4046 byte TOF :1; /* Timer Overflow Flag */
\r
4049 extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);
\r
4050 #define TFLG2 _TFLG2.Byte
\r
4051 #define TFLG2_TOF _TFLG2.Bits.TOF
\r
4054 /*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/
\r
4058 byte PAI :1; /* Pulse Accumulator Input Interrupt enable */
\r
4059 byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */
\r
4060 byte CLK0 :1; /* Clock Select Bit 0 */
\r
4061 byte CLK1 :1; /* Clock Select Bit 1 */
\r
4062 byte PEDGE :1; /* Pulse Accumulator Edge Control */
\r
4063 byte PAMOD :1; /* Pulse Accumulator Mode */
\r
4064 byte PAEN :1; /* Pulse Accumulator A System Enable */
\r
4077 extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);
\r
4078 #define PACTL _PACTL.Byte
\r
4079 #define PACTL_PAI _PACTL.Bits.PAI
\r
4080 #define PACTL_PAOVI _PACTL.Bits.PAOVI
\r
4081 #define PACTL_CLK0 _PACTL.Bits.CLK0
\r
4082 #define PACTL_CLK1 _PACTL.Bits.CLK1
\r
4083 #define PACTL_PEDGE _PACTL.Bits.PEDGE
\r
4084 #define PACTL_PAMOD _PACTL.Bits.PAMOD
\r
4085 #define PACTL_PAEN _PACTL.Bits.PAEN
\r
4086 #define PACTL_CLK _PACTL.MergedBits.grpCLK
\r
4089 /*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/
\r
4093 byte PAIF :1; /* Pulse Accumulator Input edge Flag */
\r
4094 byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */
\r
4103 extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);
\r
4104 #define PAFLG _PAFLG.Byte
\r
4105 #define PAFLG_PAIF _PAFLG.Bits.PAIF
\r
4106 #define PAFLG_PAOVF _PAFLG.Bits.PAOVF
\r
4109 /*** ATDSTAT0 - A/D Status Register 0; 0x00000086 ***/
\r
4113 byte CC0 :1; /* Conversion Counter 0 */
\r
4114 byte CC1 :1; /* Conversion Counter 1 */
\r
4115 byte CC2 :1; /* Conversion Counter 2 */
\r
4117 byte FIFOR :1; /* FIFO Over Run Flag */
\r
4118 byte ETORF :1; /* External Trigger Overrun Flag */
\r
4120 byte SCF :1; /* Sequence Complete Flag */
\r
4131 extern volatile ATDSTAT0STR _ATDSTAT0 @(REG_BASE + 0x00000086);
\r
4132 #define ATDSTAT0 _ATDSTAT0.Byte
\r
4133 #define ATDSTAT0_CC0 _ATDSTAT0.Bits.CC0
\r
4134 #define ATDSTAT0_CC1 _ATDSTAT0.Bits.CC1
\r
4135 #define ATDSTAT0_CC2 _ATDSTAT0.Bits.CC2
\r
4136 #define ATDSTAT0_FIFOR _ATDSTAT0.Bits.FIFOR
\r
4137 #define ATDSTAT0_ETORF _ATDSTAT0.Bits.ETORF
\r
4138 #define ATDSTAT0_SCF _ATDSTAT0.Bits.SCF
\r
4139 #define ATDSTAT0_CC _ATDSTAT0.MergedBits.grpCC
\r
4142 /*** ATDSTAT1 - A/D Status Register 1; 0x0000008B ***/
\r
4146 byte CCF0 :1; /* Conversion Complete Flag 0 */
\r
4147 byte CCF1 :1; /* Conversion Complete Flag 1 */
\r
4148 byte CCF2 :1; /* Conversion Complete Flag 2 */
\r
4149 byte CCF3 :1; /* Conversion Complete Flag 3 */
\r
4150 byte CCF4 :1; /* Conversion Complete Flag 4 */
\r
4151 byte CCF5 :1; /* Conversion Complete Flag 5 */
\r
4152 byte CCF6 :1; /* Conversion Complete Flag 6 */
\r
4153 byte CCF7 :1; /* Conversion Complete Flag 7 */
\r
4159 extern volatile ATDSTAT1STR _ATDSTAT1 @(REG_BASE + 0x0000008B);
\r
4160 #define ATDSTAT1 _ATDSTAT1.Byte
\r
4161 #define ATDSTAT1_CCF0 _ATDSTAT1.Bits.CCF0
\r
4162 #define ATDSTAT1_CCF1 _ATDSTAT1.Bits.CCF1
\r
4163 #define ATDSTAT1_CCF2 _ATDSTAT1.Bits.CCF2
\r
4164 #define ATDSTAT1_CCF3 _ATDSTAT1.Bits.CCF3
\r
4165 #define ATDSTAT1_CCF4 _ATDSTAT1.Bits.CCF4
\r
4166 #define ATDSTAT1_CCF5 _ATDSTAT1.Bits.CCF5
\r
4167 #define ATDSTAT1_CCF6 _ATDSTAT1.Bits.CCF6
\r
4168 #define ATDSTAT1_CCF7 _ATDSTAT1.Bits.CCF7
\r
4169 #define ATDSTAT1_CCF _ATDSTAT1.MergedBits.grpCCF
\r
4172 /*** ATDDIEN - ATD Input Enable Mask Register; 0x0000008D ***/
\r
4176 byte BIT0 :1; /* Disable/Enable digital input buffer */
\r
4177 byte BIT1 :1; /* Disable/Enable digital input buffer */
\r
4178 byte BIT2 :1; /* Disable/Enable digital input buffer */
\r
4179 byte BIT3 :1; /* Disable/Enable digital input buffer */
\r
4180 byte BIT4 :1; /* Disable/Enable digital input buffer */
\r
4181 byte BIT5 :1; /* Disable/Enable digital input buffer */
\r
4182 byte BIT6 :1; /* Disable/Enable digital input buffer */
\r
4183 byte BIT7 :1; /* Disable/Enable digital input buffer */
\r
4189 extern volatile ATDDIENSTR _ATDDIEN @(REG_BASE + 0x0000008D);
\r
4190 #define ATDDIEN _ATDDIEN.Byte
\r
4191 #define ATDDIEN_BIT0 _ATDDIEN.Bits.BIT0
\r
4192 #define ATDDIEN_BIT1 _ATDDIEN.Bits.BIT1
\r
4193 #define ATDDIEN_BIT2 _ATDDIEN.Bits.BIT2
\r
4194 #define ATDDIEN_BIT3 _ATDDIEN.Bits.BIT3
\r
4195 #define ATDDIEN_BIT4 _ATDDIEN.Bits.BIT4
\r
4196 #define ATDDIEN_BIT5 _ATDDIEN.Bits.BIT5
\r
4197 #define ATDDIEN_BIT6 _ATDDIEN.Bits.BIT6
\r
4198 #define ATDDIEN_BIT7 _ATDDIEN.Bits.BIT7
\r
4199 #define ATDDIEN_BIT _ATDDIEN.MergedBits.grpBIT
\r
4202 /*** PORTAD0 - Port AD0 Register; 0x0000008F ***/
\r
4206 byte BIT0 :1; /* AN0 */
\r
4207 byte BIT1 :1; /* AN1 */
\r
4208 byte BIT2 :1; /* AN2 */
\r
4209 byte BIT3 :1; /* AN3 */
\r
4210 byte BIT4 :1; /* AN4 */
\r
4211 byte BIT5 :1; /* AN5 */
\r
4212 byte BIT6 :1; /* AN6 */
\r
4213 byte BIT7 :1; /* AN7 */
\r
4219 extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008F);
\r
4220 #define PORTAD0 _PORTAD0.Byte
\r
4221 #define PORTAD0_BIT0 _PORTAD0.Bits.BIT0
\r
4222 #define PORTAD0_BIT1 _PORTAD0.Bits.BIT1
\r
4223 #define PORTAD0_BIT2 _PORTAD0.Bits.BIT2
\r
4224 #define PORTAD0_BIT3 _PORTAD0.Bits.BIT3
\r
4225 #define PORTAD0_BIT4 _PORTAD0.Bits.BIT4
\r
4226 #define PORTAD0_BIT5 _PORTAD0.Bits.BIT5
\r
4227 #define PORTAD0_BIT6 _PORTAD0.Bits.BIT6
\r
4228 #define PORTAD0_BIT7 _PORTAD0.Bits.BIT7
\r
4229 #define PORTAD0_BIT _PORTAD0.MergedBits.grpBIT
\r
4232 /*** SCICR1 - SCI Control Register 1; 0x000000CA ***/
\r
4236 byte PT :1; /* Parity Type Bit */
\r
4237 byte PE :1; /* Parity Enable Bit */
\r
4238 byte ILT :1; /* Idle Line Type Bit */
\r
4239 byte WAKE :1; /* Wakeup Condition Bit */
\r
4240 byte M :1; /* Data Format Mode Bit */
\r
4241 byte RSRC :1; /* Receiver Source Bit */
\r
4242 byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */
\r
4243 byte LOOPS :1; /* Loop Select Bit */
\r
4246 extern volatile SCICR1STR _SCICR1 @(REG_BASE + 0x000000CA);
\r
4247 #define SCICR1 _SCICR1.Byte
\r
4248 #define SCICR1_PT _SCICR1.Bits.PT
\r
4249 #define SCICR1_PE _SCICR1.Bits.PE
\r
4250 #define SCICR1_ILT _SCICR1.Bits.ILT
\r
4251 #define SCICR1_WAKE _SCICR1.Bits.WAKE
\r
4252 #define SCICR1_M _SCICR1.Bits.M
\r
4253 #define SCICR1_RSRC _SCICR1.Bits.RSRC
\r
4254 #define SCICR1_SCISWAI _SCICR1.Bits.SCISWAI
\r
4255 #define SCICR1_LOOPS _SCICR1.Bits.LOOPS
\r
4258 /*** SCICR2 - SCI Control Register 2; 0x000000CB ***/
\r
4262 byte SBK :1; /* Send Break Bit */
\r
4263 byte RWU :1; /* Receiver Wakeup Bit */
\r
4264 byte RE :1; /* Receiver Enable Bit */
\r
4265 byte TE :1; /* Transmitter Enable Bit */
\r
4266 byte ILIE :1; /* Idle Line Interrupt Enable Bit */
\r
4267 byte RIE :1; /* Receiver Full Interrupt Enable Bit */
\r
4268 byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */
\r
4269 byte SCTIE :1; /* Transmitter Interrupt Enable Bit */
\r
4272 extern volatile SCICR2STR _SCICR2 @(REG_BASE + 0x000000CB);
\r
4273 #define SCICR2 _SCICR2.Byte
\r
4274 #define SCICR2_SBK _SCICR2.Bits.SBK
\r
4275 #define SCICR2_RWU _SCICR2.Bits.RWU
\r
4276 #define SCICR2_RE _SCICR2.Bits.RE
\r
4277 #define SCICR2_TE _SCICR2.Bits.TE
\r
4278 #define SCICR2_ILIE _SCICR2.Bits.ILIE
\r
4279 #define SCICR2_RIE _SCICR2.Bits.RIE
\r
4280 #define SCICR2_TCIE _SCICR2.Bits.TCIE
\r
4281 #define SCICR2_SCTIE _SCICR2.Bits.SCTIE
\r
4284 /*** SCISR1 - SCI Status Register 1; 0x000000CC ***/
\r
4288 byte PF :1; /* Parity Error Flag */
\r
4289 byte FE :1; /* Framing Error Flag */
\r
4290 byte NF :1; /* Noise Flag */
\r
4291 byte OR :1; /* Overrun Flag */
\r
4292 byte IDLE :1; /* Idle Line Flag */
\r
4293 byte RDRF :1; /* Receive Data Register Full Flag */
\r
4294 byte TC :1; /* Transmit Complete Flag */
\r
4295 byte TDRE :1; /* Transmit Data Register Empty Flag */
\r
4298 extern volatile SCISR1STR _SCISR1 @(REG_BASE + 0x000000CC);
\r
4299 #define SCISR1 _SCISR1.Byte
\r
4300 #define SCISR1_PF _SCISR1.Bits.PF
\r
4301 #define SCISR1_FE _SCISR1.Bits.FE
\r
4302 #define SCISR1_NF _SCISR1.Bits.NF
\r
4303 #define SCISR1_OR _SCISR1.Bits.OR
\r
4304 #define SCISR1_IDLE _SCISR1.Bits.IDLE
\r
4305 #define SCISR1_RDRF _SCISR1.Bits.RDRF
\r
4306 #define SCISR1_TC _SCISR1.Bits.TC
\r
4307 #define SCISR1_TDRE _SCISR1.Bits.TDRE
\r
4310 /*** SCISR2 - SCI Status Register 2; 0x000000CD ***/
\r
4314 byte RAF :1; /* Receiver Active Flag */
\r
4315 byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */
\r
4316 byte BRK13 :1; /* Break Transmit character length */
\r
4324 extern volatile SCISR2STR _SCISR2 @(REG_BASE + 0x000000CD);
\r
4325 #define SCISR2 _SCISR2.Byte
\r
4326 #define SCISR2_RAF _SCISR2.Bits.RAF
\r
4327 #define SCISR2_TXDIR _SCISR2.Bits.TXDIR
\r
4328 #define SCISR2_BRK13 _SCISR2.Bits.BRK13
\r
4331 /*** SCIDRH - SCI Data Register High; 0x000000CE ***/
\r
4341 byte T8 :1; /* Transmit Bit 8 */
\r
4342 byte R8 :1; /* Received Bit 8 */
\r
4345 extern volatile SCIDRHSTR _SCIDRH @(REG_BASE + 0x000000CE);
\r
4346 #define SCIDRH _SCIDRH.Byte
\r
4347 #define SCIDRH_T8 _SCIDRH.Bits.T8
\r
4348 #define SCIDRH_R8 _SCIDRH.Bits.R8
\r
4351 /*** SCIDRL - SCI Data Register Low; 0x000000CF ***/
\r
4355 byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */
\r
4356 byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */
\r
4357 byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */
\r
4358 byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */
\r
4359 byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */
\r
4360 byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */
\r
4361 byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */
\r
4362 byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */
\r
4365 extern volatile SCIDRLSTR _SCIDRL @(REG_BASE + 0x000000CF);
\r
4366 #define SCIDRL _SCIDRL.Byte
\r
4367 #define SCIDRL_R0_T0 _SCIDRL.Bits.R0_T0
\r
4368 #define SCIDRL_R1_T1 _SCIDRL.Bits.R1_T1
\r
4369 #define SCIDRL_R2_T2 _SCIDRL.Bits.R2_T2
\r
4370 #define SCIDRL_R3_T3 _SCIDRL.Bits.R3_T3
\r
4371 #define SCIDRL_R4_T4 _SCIDRL.Bits.R4_T4
\r
4372 #define SCIDRL_R5_T5 _SCIDRL.Bits.R5_T5
\r
4373 #define SCIDRL_R6_T6 _SCIDRL.Bits.R6_T6
\r
4374 #define SCIDRL_R7_T7 _SCIDRL.Bits.R7_T7
\r
4377 /*** SPICR1 - SPI Control Register; 0x000000D8 ***/
\r
4381 byte LSBFE :1; /* SPI LSB-First Enable */
\r
4382 byte SSOE :1; /* Slave Select Output Enable */
\r
4383 byte CPHA :1; /* SPI Clock Phase Bit */
\r
4384 byte CPOL :1; /* SPI Clock Polarity Bit */
\r
4385 byte MSTR :1; /* SPI Master/Slave Mode Select Bit */
\r
4386 byte SPTIE :1; /* SPI Transmit Interrupt Enable */
\r
4387 byte SPE :1; /* SPI System Enable Bit */
\r
4388 byte SPIE :1; /* SPI Interrupt Enable Bit */
\r
4391 extern volatile SPICR1STR _SPICR1 @(REG_BASE + 0x000000D8);
\r
4392 #define SPICR1 _SPICR1.Byte
\r
4393 #define SPICR1_LSBFE _SPICR1.Bits.LSBFE
\r
4394 #define SPICR1_SSOE _SPICR1.Bits.SSOE
\r
4395 #define SPICR1_CPHA _SPICR1.Bits.CPHA
\r
4396 #define SPICR1_CPOL _SPICR1.Bits.CPOL
\r
4397 #define SPICR1_MSTR _SPICR1.Bits.MSTR
\r
4398 #define SPICR1_SPTIE _SPICR1.Bits.SPTIE
\r
4399 #define SPICR1_SPE _SPICR1.Bits.SPE
\r
4400 #define SPICR1_SPIE _SPICR1.Bits.SPIE
\r
4403 /*** SPICR2 - SPI Control Register 2; 0x000000D9 ***/
\r
4407 byte SPC0 :1; /* Serial Pin Control Bit 0 */
\r
4408 byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */
\r
4410 byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */
\r
4411 byte MODFEN :1; /* Mode Fault Enable Bit */
\r
4417 extern volatile SPICR2STR _SPICR2 @(REG_BASE + 0x000000D9);
\r
4418 #define SPICR2 _SPICR2.Byte
\r
4419 #define SPICR2_SPC0 _SPICR2.Bits.SPC0
\r
4420 #define SPICR2_SPISWAI _SPICR2.Bits.SPISWAI
\r
4421 #define SPICR2_BIDIROE _SPICR2.Bits.BIDIROE
\r
4422 #define SPICR2_MODFEN _SPICR2.Bits.MODFEN
\r
4425 /*** SPIBR - SPI Baud Rate Register; 0x000000DA ***/
\r
4429 byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */
\r
4430 byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */
\r
4431 byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */
\r
4433 byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */
\r
4434 byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */
\r
4435 byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */
\r
4445 extern volatile SPIBRSTR _SPIBR @(REG_BASE + 0x000000DA);
\r
4446 #define SPIBR _SPIBR.Byte
\r
4447 #define SPIBR_SPR0 _SPIBR.Bits.SPR0
\r
4448 #define SPIBR_SPR1 _SPIBR.Bits.SPR1
\r
4449 #define SPIBR_SPR2 _SPIBR.Bits.SPR2
\r
4450 #define SPIBR_SPPR0 _SPIBR.Bits.SPPR0
\r
4451 #define SPIBR_SPPR1 _SPIBR.Bits.SPPR1
\r
4452 #define SPIBR_SPPR2 _SPIBR.Bits.SPPR2
\r
4453 #define SPIBR_SPR _SPIBR.MergedBits.grpSPR
\r
4454 #define SPIBR_SPPR _SPIBR.MergedBits.grpSPPR
\r
4457 /*** SPISR - SPI Status Register; 0x000000DB ***/
\r
4465 byte MODF :1; /* Mode Fault Flag */
\r
4466 byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */
\r
4468 byte SPIF :1; /* SPIF Receive Interrupt Flag */
\r
4471 extern volatile SPISRSTR _SPISR @(REG_BASE + 0x000000DB);
\r
4472 #define SPISR _SPISR.Byte
\r
4473 #define SPISR_MODF _SPISR.Bits.MODF
\r
4474 #define SPISR_SPTEF _SPISR.Bits.SPTEF
\r
4475 #define SPISR_SPIF _SPISR.Bits.SPIF
\r
4478 /*** SPIDR - SPI Data Register; 0x000000DD ***/
\r
4485 extern volatile SPIDRSTR _SPIDR @(REG_BASE + 0x000000DD);
\r
4486 #define SPIDR _SPIDR.Byte
\r
4487 #define SPIDR_BIT _SPIDR.MergedBits.grpBIT
\r
4490 /*** PWME - PWM Enable Register; 0x000000E0 ***/
\r
4494 byte PWME0 :1; /* Pulse Width Channel 0 Enable */
\r
4495 byte PWME1 :1; /* Pulse Width Channel 1 Enable */
\r
4496 byte PWME2 :1; /* Pulse Width Channel 2 Enable */
\r
4497 byte PWME3 :1; /* Pulse Width Channel 3 Enable */
\r
4498 byte PWME4 :1; /* Pulse Width Channel 4 Enable */
\r
4499 byte PWME5 :1; /* Pulse Width Channel 5 Enable */
\r
4500 byte PWME6 :1; /* Pulse Width Channel 6 Enable */
\r
4501 byte PWME7 :1; /* Pulse Width Channel 7 Enable */
\r
4507 extern volatile PWMESTR _PWME @(REG_BASE + 0x000000E0);
\r
4508 #define PWME _PWME.Byte
\r
4509 #define PWME_PWME0 _PWME.Bits.PWME0
\r
4510 #define PWME_PWME1 _PWME.Bits.PWME1
\r
4511 #define PWME_PWME2 _PWME.Bits.PWME2
\r
4512 #define PWME_PWME3 _PWME.Bits.PWME3
\r
4513 #define PWME_PWME4 _PWME.Bits.PWME4
\r
4514 #define PWME_PWME5 _PWME.Bits.PWME5
\r
4515 #define PWME_PWME6 _PWME.Bits.PWME6
\r
4516 #define PWME_PWME7 _PWME.Bits.PWME7
\r
4517 #define PWME_PWME _PWME.MergedBits.grpPWME
\r
4520 /*** PWMPOL - PWM Polarity Register; 0x000000E1 ***/
\r
4524 byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */
\r
4525 byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */
\r
4526 byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */
\r
4527 byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */
\r
4528 byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */
\r
4529 byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */
\r
4530 byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */
\r
4531 byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */
\r
4537 extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000E1);
\r
4538 #define PWMPOL _PWMPOL.Byte
\r
4539 #define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0
\r
4540 #define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1
\r
4541 #define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2
\r
4542 #define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3
\r
4543 #define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4
\r
4544 #define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5
\r
4545 #define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6
\r
4546 #define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7
\r
4547 #define PWMPOL_PPOL _PWMPOL.MergedBits.grpPPOL
\r
4550 /*** PWMCLK - PWM Clock Select Register; 0x000000E2 ***/
\r
4554 byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */
\r
4555 byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */
\r
4556 byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */
\r
4557 byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */
\r
4558 byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */
\r
4559 byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */
\r
4560 byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */
\r
4561 byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */
\r
4567 extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000E2);
\r
4568 #define PWMCLK _PWMCLK.Byte
\r
4569 #define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0
\r
4570 #define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1
\r
4571 #define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2
\r
4572 #define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3
\r
4573 #define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4
\r
4574 #define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5
\r
4575 #define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6
\r
4576 #define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7
\r
4577 #define PWMCLK_PCLK _PWMCLK.MergedBits.grpPCLK
\r
4580 /*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000E3 ***/
\r
4584 byte PCKA0 :1; /* Prescaler Select for Clock A 0 */
\r
4585 byte PCKA1 :1; /* Prescaler Select for Clock A 1 */
\r
4586 byte PCKA2 :1; /* Prescaler Select for Clock A 2 */
\r
4588 byte PCKB0 :1; /* Prescaler Select for Clock B 0 */
\r
4589 byte PCKB1 :1; /* Prescaler Select for Clock B 1 */
\r
4590 byte PCKB2 :1; /* Prescaler Select for Clock B 2 */
\r
4600 extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000E3);
\r
4601 #define PWMPRCLK _PWMPRCLK.Byte
\r
4602 #define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0
\r
4603 #define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1
\r
4604 #define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2
\r
4605 #define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0
\r
4606 #define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1
\r
4607 #define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2
\r
4608 #define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA
\r
4609 #define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB
\r
4612 /*** PWMCAE - PWM Center Align Enable Register; 0x000000E4 ***/
\r
4616 byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */
\r
4617 byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */
\r
4618 byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */
\r
4619 byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */
\r
4620 byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */
\r
4621 byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */
\r
4622 byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */
\r
4623 byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */
\r
4629 extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000E4);
\r
4630 #define PWMCAE _PWMCAE.Byte
\r
4631 #define PWMCAE_CAE0 _PWMCAE.Bits.CAE0
\r
4632 #define PWMCAE_CAE1 _PWMCAE.Bits.CAE1
\r
4633 #define PWMCAE_CAE2 _PWMCAE.Bits.CAE2
\r
4634 #define PWMCAE_CAE3 _PWMCAE.Bits.CAE3
\r
4635 #define PWMCAE_CAE4 _PWMCAE.Bits.CAE4
\r
4636 #define PWMCAE_CAE5 _PWMCAE.Bits.CAE5
\r
4637 #define PWMCAE_CAE6 _PWMCAE.Bits.CAE6
\r
4638 #define PWMCAE_CAE7 _PWMCAE.Bits.CAE7
\r
4639 #define PWMCAE_CAE _PWMCAE.MergedBits.grpCAE
\r
4642 /*** PWMCTL - PWM Control Register; 0x000000E5 ***/
\r
4648 byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */
\r
4649 byte PSWAI :1; /* PWM Stops in Wait Mode */
\r
4650 byte CON01 :1; /* Concatenate channels 0 and 1 */
\r
4651 byte CON23 :1; /* Concatenate channels 2 and 3 */
\r
4652 byte CON45 :1; /* Concatenate channels 4 and 5 */
\r
4653 byte CON67 :1; /* Concatenate channels 6 and 7 */
\r
4656 extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000E5);
\r
4657 #define PWMCTL _PWMCTL.Byte
\r
4658 #define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ
\r
4659 #define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI
\r
4660 #define PWMCTL_CON01 _PWMCTL.Bits.CON01
\r
4661 #define PWMCTL_CON23 _PWMCTL.Bits.CON23
\r
4662 #define PWMCTL_CON45 _PWMCTL.Bits.CON45
\r
4663 #define PWMCTL_CON67 _PWMCTL.Bits.CON67
\r
4666 /*** PWMSCLA - PWM Scale A Register; 0x000000E8 ***/
\r
4670 byte BIT0 :1; /* PWM Scale A Bit 0 */
\r
4671 byte BIT1 :1; /* PWM Scale A Bit 1 */
\r
4672 byte BIT2 :1; /* PWM Scale A Bit 2 */
\r
4673 byte BIT3 :1; /* PWM Scale A Bit 3 */
\r
4674 byte BIT4 :1; /* PWM Scale A Bit 4 */
\r
4675 byte BIT5 :1; /* PWM Scale A Bit 5 */
\r
4676 byte BIT6 :1; /* PWM Scale A Bit 6 */
\r
4677 byte BIT7 :1; /* PWM Scale A Bit 7 */
\r
4683 extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000E8);
\r
4684 #define PWMSCLA _PWMSCLA.Byte
\r
4685 #define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0
\r
4686 #define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1
\r
4687 #define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2
\r
4688 #define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3
\r
4689 #define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4
\r
4690 #define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5
\r
4691 #define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6
\r
4692 #define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7
\r
4693 #define PWMSCLA_BIT _PWMSCLA.MergedBits.grpBIT
\r
4696 /*** PWMSCLB - PWM Scale B Register; 0x000000E9 ***/
\r
4700 byte BIT0 :1; /* PWM Scale B Bit 0 */
\r
4701 byte BIT1 :1; /* PWM Scale B Bit 1 */
\r
4702 byte BIT2 :1; /* PWM Scale B Bit 2 */
\r
4703 byte BIT3 :1; /* PWM Scale B Bit 3 */
\r
4704 byte BIT4 :1; /* PWM Scale B Bit 4 */
\r
4705 byte BIT5 :1; /* PWM Scale B Bit 5 */
\r
4706 byte BIT6 :1; /* PWM Scale B Bit 6 */
\r
4707 byte BIT7 :1; /* PWM Scale B Bit 7 */
\r
4713 extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000E9);
\r
4714 #define PWMSCLB _PWMSCLB.Byte
\r
4715 #define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0
\r
4716 #define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1
\r
4717 #define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2
\r
4718 #define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3
\r
4719 #define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4
\r
4720 #define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5
\r
4721 #define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6
\r
4722 #define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7
\r
4723 #define PWMSCLB_BIT _PWMSCLB.MergedBits.grpBIT
\r
4726 /*** PWMSDN - PWM Shutdown Register; 0x000000FE ***/
\r
4730 byte PWM7ENA :1; /* PWM emergency shutdown Enable */
\r
4731 byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */
\r
4732 byte PWM7IN :1; /* PWM channel 7 input status */
\r
4734 byte PWMLVL :1; /* PWM shutdown output Level */
\r
4735 byte PWMRSTRT :1; /* PWM Restart */
\r
4736 byte PWMIE :1; /* PWM Interrupt Enable */
\r
4737 byte PWMIF :1; /* PWM Interrupt Flag */
\r
4740 extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000FE);
\r
4741 #define PWMSDN _PWMSDN.Byte
\r
4742 #define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA
\r
4743 #define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL
\r
4744 #define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN
\r
4745 #define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL
\r
4746 #define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT
\r
4747 #define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE
\r
4748 #define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF
\r
4751 /*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/
\r
4755 byte FDIV0 :1; /* Flash Clock Divider Bit 0 */
\r
4756 byte FDIV1 :1; /* Flash Clock Divider Bit 1 */
\r
4757 byte FDIV2 :1; /* Flash Clock Divider Bit 2 */
\r
4758 byte FDIV3 :1; /* Flash Clock Divider Bit 3 */
\r
4759 byte FDIV4 :1; /* Flash Clock Divider Bit 4 */
\r
4760 byte FDIV5 :1; /* Flash Clock Divider Bit 5 */
\r
4761 byte PRDIV8 :1; /* Enable Prescaler by 8 */
\r
4762 byte FDIVLD :1; /* Flash Clock Divider Loaded */
\r
4766 byte grpPRDIV_8 :1;
\r
4770 extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);
\r
4771 #define FCLKDIV _FCLKDIV.Byte
\r
4772 #define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0
\r
4773 #define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1
\r
4774 #define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2
\r
4775 #define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3
\r
4776 #define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4
\r
4777 #define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5
\r
4778 #define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8
\r
4779 #define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD
\r
4780 #define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV
\r
4783 /*** FSEC - Flash Security Register; 0x00000101 ***/
\r
4787 byte SEC0 :1; /* Memory security bit 0 */
\r
4788 byte SEC1 :1; /* Memory security bit 1 */
\r
4789 byte NV2 :1; /* Non Volatile flag bit 2 */
\r
4790 byte NV3 :1; /* Non Volatile flag bit 3 */
\r
4791 byte NV4 :1; /* Non Volatile flag bit 4 */
\r
4792 byte NV5 :1; /* Non Volatile flag bit 5 */
\r
4793 byte NV6 :1; /* Non Volatile flag bit 6 */
\r
4794 byte KEYEN :1; /* Enable backdoor key to security */
\r
4802 extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);
\r
4803 #define FSEC _FSEC.Byte
\r
4804 #define FSEC_SEC0 _FSEC.Bits.SEC0
\r
4805 #define FSEC_SEC1 _FSEC.Bits.SEC1
\r
4806 #define FSEC_NV2 _FSEC.Bits.NV2
\r
4807 #define FSEC_NV3 _FSEC.Bits.NV3
\r
4808 #define FSEC_NV4 _FSEC.Bits.NV4
\r
4809 #define FSEC_NV5 _FSEC.Bits.NV5
\r
4810 #define FSEC_NV6 _FSEC.Bits.NV6
\r
4811 #define FSEC_KEYEN _FSEC.Bits.KEYEN
\r
4812 #define FSEC_SEC _FSEC.MergedBits.grpSEC
\r
4813 #define FSEC_NV_2 _FSEC.MergedBits.grpNV_2
\r
4814 #define FSEC_NV FSEC_NV_2
\r
4817 /*** FCNFG - Flash Configuration Register; 0x00000103 ***/
\r
4821 byte BKSEL0 :1; /* Register bank select 0 */
\r
4822 byte BKSEL1 :1; /* Register bank select 1 */
\r
4826 byte KEYACC :1; /* Enable Security Key Writing */
\r
4827 byte CCIE :1; /* Command Complete Interrupt Enable */
\r
4828 byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */
\r
4840 extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);
\r
4841 #define FCNFG _FCNFG.Byte
\r
4842 #define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0
\r
4843 #define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1
\r
4844 #define FCNFG_KEYACC _FCNFG.Bits.KEYACC
\r
4845 #define FCNFG_CCIE _FCNFG.Bits.CCIE
\r
4846 #define FCNFG_CBEIE _FCNFG.Bits.CBEIE
\r
4847 #define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL
\r
4850 /*** FPROT - Flash Protection Register; 0x00000104 ***/
\r
4854 byte FPLS0 :1; /* Flash Protection Lower Address size 0 */
\r
4855 byte FPLS1 :1; /* Flash Protection Lower Address size 1 */
\r
4856 byte FPLDIS :1; /* Flash Protection Lower address range disable */
\r
4857 byte FPHS0 :1; /* Flash Protection Higher address size 0 */
\r
4858 byte FPHS1 :1; /* Flash Protection Higher address size 1 */
\r
4859 byte FPHDIS :1; /* Flash Protection Higher address range disable */
\r
4860 byte NV6 :1; /* Non Volatile Flag Bit */
\r
4861 byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */
\r
4872 extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);
\r
4873 #define FPROT _FPROT.Byte
\r
4874 #define FPROT_FPLS0 _FPROT.Bits.FPLS0
\r
4875 #define FPROT_FPLS1 _FPROT.Bits.FPLS1
\r
4876 #define FPROT_FPLDIS _FPROT.Bits.FPLDIS
\r
4877 #define FPROT_FPHS0 _FPROT.Bits.FPHS0
\r
4878 #define FPROT_FPHS1 _FPROT.Bits.FPHS1
\r
4879 #define FPROT_FPHDIS _FPROT.Bits.FPHDIS
\r
4880 #define FPROT_NV6 _FPROT.Bits.NV6
\r
4881 #define FPROT_FPOPEN _FPROT.Bits.FPOPEN
\r
4882 #define FPROT_FPLS _FPROT.MergedBits.grpFPLS
\r
4883 #define FPROT_FPHS _FPROT.MergedBits.grpFPHS
\r
4886 /*** FSTAT - Flash Status Register; 0x00000105 ***/
\r
4892 byte BLANK :1; /* Blank Verify Flag */
\r
4894 byte ACCERR :1; /* Access error */
\r
4895 byte PVIOL :1; /* Protection violation */
\r
4896 byte CCIF :1; /* Command Complete Interrupt Flag */
\r
4897 byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */
\r
4900 extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);
\r
4901 #define FSTAT _FSTAT.Byte
\r
4902 #define FSTAT_BLANK _FSTAT.Bits.BLANK
\r
4903 #define FSTAT_ACCERR _FSTAT.Bits.ACCERR
\r
4904 #define FSTAT_PVIOL _FSTAT.Bits.PVIOL
\r
4905 #define FSTAT_CCIF _FSTAT.Bits.CCIF
\r
4906 #define FSTAT_CBEIF _FSTAT.Bits.CBEIF
\r
4909 /*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/
\r
4913 byte CMDB0 :1; /* NVM User Mode Command Bit 0 */
\r
4915 byte CMDB2 :1; /* NVM User Mode Command Bit 2 */
\r
4918 byte CMDB5 :1; /* NVM User Mode Command Bit 5 */
\r
4919 byte CMDB6 :1; /* NVM User Mode Command Bit 6 */
\r
4925 byte grpCMDB_2 :1;
\r
4928 byte grpCMDB_5 :2;
\r
4932 extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);
\r
4933 #define FCMD _FCMD.Byte
\r
4934 #define FCMD_CMDB0 _FCMD.Bits.CMDB0
\r
4935 #define FCMD_CMDB2 _FCMD.Bits.CMDB2
\r
4936 #define FCMD_CMDB5 _FCMD.Bits.CMDB5
\r
4937 #define FCMD_CMDB6 _FCMD.Bits.CMDB6
\r
4938 #define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5
\r
4939 #define FCMD_CMDB FCMD_CMDB_5
\r
4942 /*** CANCTL0 - MSCAN Control 0 Register; 0x00000140 ***/
\r
4946 byte INITRQ :1; /* Initialization Mode Request */
\r
4947 byte SLPRQ :1; /* Sleep Mode Request */
\r
4948 byte WUPE :1; /* Wake-Up Enable */
\r
4949 byte TIME :1; /* Timer Enable */
\r
4950 byte SYNCH :1; /* Synchronized Status */
\r
4951 byte CSWAI :1; /* CAN Stops in Wait Mode */
\r
4952 byte RXACT :1; /* Receiver Active Status */
\r
4953 byte RXFRM :1; /* Received Frame Flag */
\r
4956 extern volatile CANCTL0STR _CANCTL0 @(REG_BASE + 0x00000140);
\r
4957 #define CANCTL0 _CANCTL0.Byte
\r
4958 #define CANCTL0_INITRQ _CANCTL0.Bits.INITRQ
\r
4959 #define CANCTL0_SLPRQ _CANCTL0.Bits.SLPRQ
\r
4960 #define CANCTL0_WUPE _CANCTL0.Bits.WUPE
\r
4961 #define CANCTL0_TIME _CANCTL0.Bits.TIME
\r
4962 #define CANCTL0_SYNCH _CANCTL0.Bits.SYNCH
\r
4963 #define CANCTL0_CSWAI _CANCTL0.Bits.CSWAI
\r
4964 #define CANCTL0_RXACT _CANCTL0.Bits.RXACT
\r
4965 #define CANCTL0_RXFRM _CANCTL0.Bits.RXFRM
\r
4968 /*** CANCTL1 - MSCAN Control 1 Register; 0x00000141 ***/
\r
4972 byte INITAK :1; /* Initialization Mode Acknowledge */
\r
4973 byte SLPAK :1; /* Sleep Mode Acknowledge */
\r
4974 byte WUPM :1; /* Wake-Up Mode */
\r
4976 byte LISTEN :1; /* Listen Only Mode */
\r
4977 byte LOOPB :1; /* Loop Back Self Test Mode */
\r
4978 byte CLKSRC :1; /* MSCAN Clock Source */
\r
4979 byte CANE :1; /* MSCAN Enable */
\r
4982 extern volatile CANCTL1STR _CANCTL1 @(REG_BASE + 0x00000141);
\r
4983 #define CANCTL1 _CANCTL1.Byte
\r
4984 #define CANCTL1_INITAK _CANCTL1.Bits.INITAK
\r
4985 #define CANCTL1_SLPAK _CANCTL1.Bits.SLPAK
\r
4986 #define CANCTL1_WUPM _CANCTL1.Bits.WUPM
\r
4987 #define CANCTL1_LISTEN _CANCTL1.Bits.LISTEN
\r
4988 #define CANCTL1_LOOPB _CANCTL1.Bits.LOOPB
\r
4989 #define CANCTL1_CLKSRC _CANCTL1.Bits.CLKSRC
\r
4990 #define CANCTL1_CANE _CANCTL1.Bits.CANE
\r
4993 /*** CANBTR0 - MSCAN Bus Timing Register 0; 0x00000142 ***/
\r
4997 byte BRP0 :1; /* Baud Rate Prescaler 0 */
\r
4998 byte BRP1 :1; /* Baud Rate Prescaler 1 */
\r
4999 byte BRP2 :1; /* Baud Rate Prescaler 2 */
\r
5000 byte BRP3 :1; /* Baud Rate Prescaler 3 */
\r
5001 byte BRP4 :1; /* Baud Rate Prescaler 4 */
\r
5002 byte BRP5 :1; /* Baud Rate Prescaler 5 */
\r
5003 byte SJW0 :1; /* Synchronization Jump Width 0 */
\r
5004 byte SJW1 :1; /* Synchronization Jump Width 1 */
\r
5011 extern volatile CANBTR0STR _CANBTR0 @(REG_BASE + 0x00000142);
\r
5012 #define CANBTR0 _CANBTR0.Byte
\r
5013 #define CANBTR0_BRP0 _CANBTR0.Bits.BRP0
\r
5014 #define CANBTR0_BRP1 _CANBTR0.Bits.BRP1
\r
5015 #define CANBTR0_BRP2 _CANBTR0.Bits.BRP2
\r
5016 #define CANBTR0_BRP3 _CANBTR0.Bits.BRP3
\r
5017 #define CANBTR0_BRP4 _CANBTR0.Bits.BRP4
\r
5018 #define CANBTR0_BRP5 _CANBTR0.Bits.BRP5
\r
5019 #define CANBTR0_SJW0 _CANBTR0.Bits.SJW0
\r
5020 #define CANBTR0_SJW1 _CANBTR0.Bits.SJW1
\r
5021 #define CANBTR0_BRP _CANBTR0.MergedBits.grpBRP
\r
5022 #define CANBTR0_SJW _CANBTR0.MergedBits.grpSJW
\r
5025 /*** CANBTR1 - MSCAN Bus Timing Register 1; 0x00000143 ***/
\r
5029 byte TSEG10 :1; /* Time Segment 1 */
\r
5030 byte TSEG11 :1; /* Time Segment 1 */
\r
5031 byte TSEG12 :1; /* Time Segment 1 */
\r
5032 byte TSEG13 :1; /* Time Segment 1 */
\r
5033 byte TSEG20 :1; /* Time Segment 2 */
\r
5034 byte TSEG21 :1; /* Time Segment 2 */
\r
5035 byte TSEG22 :1; /* Time Segment 2 */
\r
5036 byte SAMP :1; /* Sampling */
\r
5039 byte grpTSEG_10 :4;
\r
5040 byte grpTSEG_20 :3;
\r
5044 extern volatile CANBTR1STR _CANBTR1 @(REG_BASE + 0x00000143);
\r
5045 #define CANBTR1 _CANBTR1.Byte
\r
5046 #define CANBTR1_TSEG10 _CANBTR1.Bits.TSEG10
\r
5047 #define CANBTR1_TSEG11 _CANBTR1.Bits.TSEG11
\r
5048 #define CANBTR1_TSEG12 _CANBTR1.Bits.TSEG12
\r
5049 #define CANBTR1_TSEG13 _CANBTR1.Bits.TSEG13
\r
5050 #define CANBTR1_TSEG20 _CANBTR1.Bits.TSEG20
\r
5051 #define CANBTR1_TSEG21 _CANBTR1.Bits.TSEG21
\r
5052 #define CANBTR1_TSEG22 _CANBTR1.Bits.TSEG22
\r
5053 #define CANBTR1_SAMP _CANBTR1.Bits.SAMP
\r
5054 #define CANBTR1_TSEG_10 _CANBTR1.MergedBits.grpTSEG_10
\r
5055 #define CANBTR1_TSEG_20 _CANBTR1.MergedBits.grpTSEG_20
\r
5056 #define CANBTR1_TSEG CANBTR1_TSEG_10
\r
5059 /*** CANRFLG - MSCAN Receiver Flag Register; 0x00000144 ***/
\r
5063 byte RXF :1; /* Receive Buffer Full */
\r
5064 byte OVRIF :1; /* Overrun Interrupt Flag */
\r
5065 byte TSTAT0 :1; /* Transmitter Status Bit 0 */
\r
5066 byte TSTAT1 :1; /* Transmitter Status Bit 1 */
\r
5067 byte RSTAT0 :1; /* Receiver Status Bit 0 */
\r
5068 byte RSTAT1 :1; /* Receiver Status Bit 1 */
\r
5069 byte CSCIF :1; /* CAN Status Change Interrupt Flag */
\r
5070 byte WUPIF :1; /* Wake-up Interrupt Flag */
\r
5081 extern volatile CANRFLGSTR _CANRFLG @(REG_BASE + 0x00000144);
\r
5082 #define CANRFLG _CANRFLG.Byte
\r
5083 #define CANRFLG_RXF _CANRFLG.Bits.RXF
\r
5084 #define CANRFLG_OVRIF _CANRFLG.Bits.OVRIF
\r
5085 #define CANRFLG_TSTAT0 _CANRFLG.Bits.TSTAT0
\r
5086 #define CANRFLG_TSTAT1 _CANRFLG.Bits.TSTAT1
\r
5087 #define CANRFLG_RSTAT0 _CANRFLG.Bits.RSTAT0
\r
5088 #define CANRFLG_RSTAT1 _CANRFLG.Bits.RSTAT1
\r
5089 #define CANRFLG_CSCIF _CANRFLG.Bits.CSCIF
\r
5090 #define CANRFLG_WUPIF _CANRFLG.Bits.WUPIF
\r
5091 #define CANRFLG_TSTAT _CANRFLG.MergedBits.grpTSTAT
\r
5092 #define CANRFLG_RSTAT _CANRFLG.MergedBits.grpRSTAT
\r
5095 /*** CANRIER - MSCAN Receiver Interrupt Enable Register; 0x00000145 ***/
\r
5099 byte RXFIE :1; /* Receiver Full Interrupt Enable */
\r
5100 byte OVRIE :1; /* Overrun Interrupt Enable */
\r
5101 byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */
\r
5102 byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */
\r
5103 byte RSTATE0 :1; /* Receiver Status Change Enable 0 */
\r
5104 byte RSTATE1 :1; /* Receiver Status Change Enable 1 */
\r
5105 byte CSCIE :1; /* CAN Status Change Interrupt Enable */
\r
5106 byte WUPIE :1; /* Wake-up Interrupt Enable */
\r
5111 byte grpTSTATE :2;
\r
5112 byte grpRSTATE :2;
\r
5117 extern volatile CANRIERSTR _CANRIER @(REG_BASE + 0x00000145);
\r
5118 #define CANRIER _CANRIER.Byte
\r
5119 #define CANRIER_RXFIE _CANRIER.Bits.RXFIE
\r
5120 #define CANRIER_OVRIE _CANRIER.Bits.OVRIE
\r
5121 #define CANRIER_TSTATE0 _CANRIER.Bits.TSTATE0
\r
5122 #define CANRIER_TSTATE1 _CANRIER.Bits.TSTATE1
\r
5123 #define CANRIER_RSTATE0 _CANRIER.Bits.RSTATE0
\r
5124 #define CANRIER_RSTATE1 _CANRIER.Bits.RSTATE1
\r
5125 #define CANRIER_CSCIE _CANRIER.Bits.CSCIE
\r
5126 #define CANRIER_WUPIE _CANRIER.Bits.WUPIE
\r
5127 #define CANRIER_TSTATE _CANRIER.MergedBits.grpTSTATE
\r
5128 #define CANRIER_RSTATE _CANRIER.MergedBits.grpRSTATE
\r
5131 /*** CANTFLG - MSCAN Transmitter Flag Register; 0x00000146 ***/
\r
5135 byte TXE0 :1; /* Transmitter Buffer Empty 0 */
\r
5136 byte TXE1 :1; /* Transmitter Buffer Empty 1 */
\r
5137 byte TXE2 :1; /* Transmitter Buffer Empty 2 */
\r
5153 extern volatile CANTFLGSTR _CANTFLG @(REG_BASE + 0x00000146);
\r
5154 #define CANTFLG _CANTFLG.Byte
\r
5155 #define CANTFLG_TXE0 _CANTFLG.Bits.TXE0
\r
5156 #define CANTFLG_TXE1 _CANTFLG.Bits.TXE1
\r
5157 #define CANTFLG_TXE2 _CANTFLG.Bits.TXE2
\r
5158 #define CANTFLG_TXE _CANTFLG.MergedBits.grpTXE
\r
5161 /*** CANTIER - MSCAN Transmitter Interrupt Enable Register; 0x00000147 ***/
\r
5165 byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */
\r
5166 byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */
\r
5167 byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */
\r
5183 extern volatile CANTIERSTR _CANTIER @(REG_BASE + 0x00000147);
\r
5184 #define CANTIER _CANTIER.Byte
\r
5185 #define CANTIER_TXEIE0 _CANTIER.Bits.TXEIE0
\r
5186 #define CANTIER_TXEIE1 _CANTIER.Bits.TXEIE1
\r
5187 #define CANTIER_TXEIE2 _CANTIER.Bits.TXEIE2
\r
5188 #define CANTIER_TXEIE _CANTIER.MergedBits.grpTXEIE
\r
5191 /*** CANTARQ - MSCAN Transmitter Message Abort Request; 0x00000148 ***/
\r
5195 byte ABTRQ0 :1; /* Abort Request 0 */
\r
5196 byte ABTRQ1 :1; /* Abort Request 1 */
\r
5197 byte ABTRQ2 :1; /* Abort Request 2 */
\r
5213 extern volatile CANTARQSTR _CANTARQ @(REG_BASE + 0x00000148);
\r
5214 #define CANTARQ _CANTARQ.Byte
\r
5215 #define CANTARQ_ABTRQ0 _CANTARQ.Bits.ABTRQ0
\r
5216 #define CANTARQ_ABTRQ1 _CANTARQ.Bits.ABTRQ1
\r
5217 #define CANTARQ_ABTRQ2 _CANTARQ.Bits.ABTRQ2
\r
5218 #define CANTARQ_ABTRQ _CANTARQ.MergedBits.grpABTRQ
\r
5221 /*** CANTAAK - MSCAN Transmitter Message Abort Control; 0x00000149 ***/
\r
5225 byte ABTAK0 :1; /* Abort Acknowledge 0 */
\r
5226 byte ABTAK1 :1; /* Abort Acknowledge 1 */
\r
5227 byte ABTAK2 :1; /* Abort Acknowledge 2 */
\r
5243 extern volatile CANTAAKSTR _CANTAAK @(REG_BASE + 0x00000149);
\r
5244 #define CANTAAK _CANTAAK.Byte
\r
5245 #define CANTAAK_ABTAK0 _CANTAAK.Bits.ABTAK0
\r
5246 #define CANTAAK_ABTAK1 _CANTAAK.Bits.ABTAK1
\r
5247 #define CANTAAK_ABTAK2 _CANTAAK.Bits.ABTAK2
\r
5248 #define CANTAAK_ABTAK _CANTAAK.MergedBits.grpABTAK
\r
5251 /*** CANTBSEL - MSCAN Transmit Buffer Selection; 0x0000014A ***/
\r
5255 byte TX0 :1; /* Transmit Buffer Select 0 */
\r
5256 byte TX1 :1; /* Transmit Buffer Select 1 */
\r
5257 byte TX2 :1; /* Transmit Buffer Select 2 */
\r
5273 extern volatile CANTBSELSTR _CANTBSEL @(REG_BASE + 0x0000014A);
\r
5274 #define CANTBSEL _CANTBSEL.Byte
\r
5275 #define CANTBSEL_TX0 _CANTBSEL.Bits.TX0
\r
5276 #define CANTBSEL_TX1 _CANTBSEL.Bits.TX1
\r
5277 #define CANTBSEL_TX2 _CANTBSEL.Bits.TX2
\r
5278 #define CANTBSEL_TX _CANTBSEL.MergedBits.grpTX
\r
5281 /*** CANIDAC - MSCAN Identifier Acceptance Control Register; 0x0000014B ***/
\r
5285 byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */
\r
5286 byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */
\r
5287 byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */
\r
5289 byte IDAM0 :1; /* Identifier Acceptance Mode 0 */
\r
5290 byte IDAM1 :1; /* Identifier Acceptance Mode 1 */
\r
5302 extern volatile CANIDACSTR _CANIDAC @(REG_BASE + 0x0000014B);
\r
5303 #define CANIDAC _CANIDAC.Byte
\r
5304 #define CANIDAC_IDHIT0 _CANIDAC.Bits.IDHIT0
\r
5305 #define CANIDAC_IDHIT1 _CANIDAC.Bits.IDHIT1
\r
5306 #define CANIDAC_IDHIT2 _CANIDAC.Bits.IDHIT2
\r
5307 #define CANIDAC_IDAM0 _CANIDAC.Bits.IDAM0
\r
5308 #define CANIDAC_IDAM1 _CANIDAC.Bits.IDAM1
\r
5309 #define CANIDAC_IDHIT _CANIDAC.MergedBits.grpIDHIT
\r
5310 #define CANIDAC_IDAM _CANIDAC.MergedBits.grpIDAM
\r
5313 /*** CANRXERR - MSCAN Receive Error Counter Register; 0x0000014E ***/
\r
5317 byte RXERR0 :1; /* Bit 0 */
\r
5318 byte RXERR1 :1; /* Bit 1 */
\r
5319 byte RXERR2 :1; /* Bit 2 */
\r
5320 byte RXERR3 :1; /* Bit 3 */
\r
5321 byte RXERR4 :1; /* Bit 4 */
\r
5322 byte RXERR5 :1; /* Bit 5 */
\r
5323 byte RXERR6 :1; /* Bit 6 */
\r
5324 byte RXERR7 :1; /* Bit 7 */
\r
5330 extern volatile CANRXERRSTR _CANRXERR @(REG_BASE + 0x0000014E);
\r
5331 #define CANRXERR _CANRXERR.Byte
\r
5332 #define CANRXERR_RXERR0 _CANRXERR.Bits.RXERR0
\r
5333 #define CANRXERR_RXERR1 _CANRXERR.Bits.RXERR1
\r
5334 #define CANRXERR_RXERR2 _CANRXERR.Bits.RXERR2
\r
5335 #define CANRXERR_RXERR3 _CANRXERR.Bits.RXERR3
\r
5336 #define CANRXERR_RXERR4 _CANRXERR.Bits.RXERR4
\r
5337 #define CANRXERR_RXERR5 _CANRXERR.Bits.RXERR5
\r
5338 #define CANRXERR_RXERR6 _CANRXERR.Bits.RXERR6
\r
5339 #define CANRXERR_RXERR7 _CANRXERR.Bits.RXERR7
\r
5340 #define CANRXERR_RXERR _CANRXERR.MergedBits.grpRXERR
\r
5343 /*** CANTXERR - MSCAN Transmit Error Counter Register; 0x0000014F ***/
\r
5347 byte TXERR0 :1; /* Bit 0 */
\r
5348 byte TXERR1 :1; /* Bit 1 */
\r
5349 byte TXERR2 :1; /* Bit 2 */
\r
5350 byte TXERR3 :1; /* Bit 3 */
\r
5351 byte TXERR4 :1; /* Bit 4 */
\r
5352 byte TXERR5 :1; /* Bit 5 */
\r
5353 byte TXERR6 :1; /* Bit 6 */
\r
5354 byte TXERR7 :1; /* Bit 7 */
\r
5360 extern volatile CANTXERRSTR _CANTXERR @(REG_BASE + 0x0000014F);
\r
5361 #define CANTXERR _CANTXERR.Byte
\r
5362 #define CANTXERR_TXERR0 _CANTXERR.Bits.TXERR0
\r
5363 #define CANTXERR_TXERR1 _CANTXERR.Bits.TXERR1
\r
5364 #define CANTXERR_TXERR2 _CANTXERR.Bits.TXERR2
\r
5365 #define CANTXERR_TXERR3 _CANTXERR.Bits.TXERR3
\r
5366 #define CANTXERR_TXERR4 _CANTXERR.Bits.TXERR4
\r
5367 #define CANTXERR_TXERR5 _CANTXERR.Bits.TXERR5
\r
5368 #define CANTXERR_TXERR6 _CANTXERR.Bits.TXERR6
\r
5369 #define CANTXERR_TXERR7 _CANTXERR.Bits.TXERR7
\r
5370 #define CANTXERR_TXERR _CANTXERR.MergedBits.grpTXERR
\r
5373 /*** CANIDAR0 - MSCAN Identifier Acceptance Register 0; 0x00000150 ***/
\r
5377 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
5378 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
5379 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
5380 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
5381 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
5382 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
5383 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
5384 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
5390 extern volatile CANIDAR0STR _CANIDAR0 @(REG_BASE + 0x00000150);
\r
5391 #define CANIDAR0 _CANIDAR0.Byte
\r
5392 #define CANIDAR0_AC0 _CANIDAR0.Bits.AC0
\r
5393 #define CANIDAR0_AC1 _CANIDAR0.Bits.AC1
\r
5394 #define CANIDAR0_AC2 _CANIDAR0.Bits.AC2
\r
5395 #define CANIDAR0_AC3 _CANIDAR0.Bits.AC3
\r
5396 #define CANIDAR0_AC4 _CANIDAR0.Bits.AC4
\r
5397 #define CANIDAR0_AC5 _CANIDAR0.Bits.AC5
\r
5398 #define CANIDAR0_AC6 _CANIDAR0.Bits.AC6
\r
5399 #define CANIDAR0_AC7 _CANIDAR0.Bits.AC7
\r
5400 #define CANIDAR0_AC _CANIDAR0.MergedBits.grpAC
\r
5403 /*** CANIDAR1 - MSCAN Identifier Acceptance Register 1; 0x00000151 ***/
\r
5407 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
5408 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
5409 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
5410 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
5411 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
5412 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
5413 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
5414 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
5420 extern volatile CANIDAR1STR _CANIDAR1 @(REG_BASE + 0x00000151);
\r
5421 #define CANIDAR1 _CANIDAR1.Byte
\r
5422 #define CANIDAR1_AC0 _CANIDAR1.Bits.AC0
\r
5423 #define CANIDAR1_AC1 _CANIDAR1.Bits.AC1
\r
5424 #define CANIDAR1_AC2 _CANIDAR1.Bits.AC2
\r
5425 #define CANIDAR1_AC3 _CANIDAR1.Bits.AC3
\r
5426 #define CANIDAR1_AC4 _CANIDAR1.Bits.AC4
\r
5427 #define CANIDAR1_AC5 _CANIDAR1.Bits.AC5
\r
5428 #define CANIDAR1_AC6 _CANIDAR1.Bits.AC6
\r
5429 #define CANIDAR1_AC7 _CANIDAR1.Bits.AC7
\r
5430 #define CANIDAR1_AC _CANIDAR1.MergedBits.grpAC
\r
5433 /*** CANIDAR2 - MSCAN Identifier Acceptance Register 2; 0x00000152 ***/
\r
5437 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
5438 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
5439 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
5440 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
5441 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
5442 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
5443 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
5444 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
5450 extern volatile CANIDAR2STR _CANIDAR2 @(REG_BASE + 0x00000152);
\r
5451 #define CANIDAR2 _CANIDAR2.Byte
\r
5452 #define CANIDAR2_AC0 _CANIDAR2.Bits.AC0
\r
5453 #define CANIDAR2_AC1 _CANIDAR2.Bits.AC1
\r
5454 #define CANIDAR2_AC2 _CANIDAR2.Bits.AC2
\r
5455 #define CANIDAR2_AC3 _CANIDAR2.Bits.AC3
\r
5456 #define CANIDAR2_AC4 _CANIDAR2.Bits.AC4
\r
5457 #define CANIDAR2_AC5 _CANIDAR2.Bits.AC5
\r
5458 #define CANIDAR2_AC6 _CANIDAR2.Bits.AC6
\r
5459 #define CANIDAR2_AC7 _CANIDAR2.Bits.AC7
\r
5460 #define CANIDAR2_AC _CANIDAR2.MergedBits.grpAC
\r
5463 /*** CANIDAR3 - MSCAN Identifier Acceptance Register 3; 0x00000153 ***/
\r
5467 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
5468 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
5469 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
5470 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
5471 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
5472 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
5473 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
5474 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
5480 extern volatile CANIDAR3STR _CANIDAR3 @(REG_BASE + 0x00000153);
\r
5481 #define CANIDAR3 _CANIDAR3.Byte
\r
5482 #define CANIDAR3_AC0 _CANIDAR3.Bits.AC0
\r
5483 #define CANIDAR3_AC1 _CANIDAR3.Bits.AC1
\r
5484 #define CANIDAR3_AC2 _CANIDAR3.Bits.AC2
\r
5485 #define CANIDAR3_AC3 _CANIDAR3.Bits.AC3
\r
5486 #define CANIDAR3_AC4 _CANIDAR3.Bits.AC4
\r
5487 #define CANIDAR3_AC5 _CANIDAR3.Bits.AC5
\r
5488 #define CANIDAR3_AC6 _CANIDAR3.Bits.AC6
\r
5489 #define CANIDAR3_AC7 _CANIDAR3.Bits.AC7
\r
5490 #define CANIDAR3_AC _CANIDAR3.MergedBits.grpAC
\r
5493 /*** CANIDMR0 - MSCAN Identifier Mask Register 0; 0x00000154 ***/
\r
5497 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
5498 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
5499 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
5500 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
5501 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
5502 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
5503 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
5504 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
5510 extern volatile CANIDMR0STR _CANIDMR0 @(REG_BASE + 0x00000154);
\r
5511 #define CANIDMR0 _CANIDMR0.Byte
\r
5512 #define CANIDMR0_AM0 _CANIDMR0.Bits.AM0
\r
5513 #define CANIDMR0_AM1 _CANIDMR0.Bits.AM1
\r
5514 #define CANIDMR0_AM2 _CANIDMR0.Bits.AM2
\r
5515 #define CANIDMR0_AM3 _CANIDMR0.Bits.AM3
\r
5516 #define CANIDMR0_AM4 _CANIDMR0.Bits.AM4
\r
5517 #define CANIDMR0_AM5 _CANIDMR0.Bits.AM5
\r
5518 #define CANIDMR0_AM6 _CANIDMR0.Bits.AM6
\r
5519 #define CANIDMR0_AM7 _CANIDMR0.Bits.AM7
\r
5520 #define CANIDMR0_AM _CANIDMR0.MergedBits.grpAM
\r
5523 /*** CANIDMR1 - MSCAN Identifier Mask Register 1; 0x00000155 ***/
\r
5527 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
5528 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
5529 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
5530 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
5531 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
5532 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
5533 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
5534 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
5540 extern volatile CANIDMR1STR _CANIDMR1 @(REG_BASE + 0x00000155);
\r
5541 #define CANIDMR1 _CANIDMR1.Byte
\r
5542 #define CANIDMR1_AM0 _CANIDMR1.Bits.AM0
\r
5543 #define CANIDMR1_AM1 _CANIDMR1.Bits.AM1
\r
5544 #define CANIDMR1_AM2 _CANIDMR1.Bits.AM2
\r
5545 #define CANIDMR1_AM3 _CANIDMR1.Bits.AM3
\r
5546 #define CANIDMR1_AM4 _CANIDMR1.Bits.AM4
\r
5547 #define CANIDMR1_AM5 _CANIDMR1.Bits.AM5
\r
5548 #define CANIDMR1_AM6 _CANIDMR1.Bits.AM6
\r
5549 #define CANIDMR1_AM7 _CANIDMR1.Bits.AM7
\r
5550 #define CANIDMR1_AM _CANIDMR1.MergedBits.grpAM
\r
5553 /*** CANIDMR2 - MSCAN Identifier Mask Register 2; 0x00000156 ***/
\r
5557 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
5558 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
5559 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
5560 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
5561 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
5562 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
5563 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
5564 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
5570 extern volatile CANIDMR2STR _CANIDMR2 @(REG_BASE + 0x00000156);
\r
5571 #define CANIDMR2 _CANIDMR2.Byte
\r
5572 #define CANIDMR2_AM0 _CANIDMR2.Bits.AM0
\r
5573 #define CANIDMR2_AM1 _CANIDMR2.Bits.AM1
\r
5574 #define CANIDMR2_AM2 _CANIDMR2.Bits.AM2
\r
5575 #define CANIDMR2_AM3 _CANIDMR2.Bits.AM3
\r
5576 #define CANIDMR2_AM4 _CANIDMR2.Bits.AM4
\r
5577 #define CANIDMR2_AM5 _CANIDMR2.Bits.AM5
\r
5578 #define CANIDMR2_AM6 _CANIDMR2.Bits.AM6
\r
5579 #define CANIDMR2_AM7 _CANIDMR2.Bits.AM7
\r
5580 #define CANIDMR2_AM _CANIDMR2.MergedBits.grpAM
\r
5583 /*** CANIDMR3 - MSCAN Identifier Mask Register 3; 0x00000157 ***/
\r
5587 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
5588 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
5589 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
5590 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
5591 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
5592 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
5593 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
5594 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
5600 extern volatile CANIDMR3STR _CANIDMR3 @(REG_BASE + 0x00000157);
\r
5601 #define CANIDMR3 _CANIDMR3.Byte
\r
5602 #define CANIDMR3_AM0 _CANIDMR3.Bits.AM0
\r
5603 #define CANIDMR3_AM1 _CANIDMR3.Bits.AM1
\r
5604 #define CANIDMR3_AM2 _CANIDMR3.Bits.AM2
\r
5605 #define CANIDMR3_AM3 _CANIDMR3.Bits.AM3
\r
5606 #define CANIDMR3_AM4 _CANIDMR3.Bits.AM4
\r
5607 #define CANIDMR3_AM5 _CANIDMR3.Bits.AM5
\r
5608 #define CANIDMR3_AM6 _CANIDMR3.Bits.AM6
\r
5609 #define CANIDMR3_AM7 _CANIDMR3.Bits.AM7
\r
5610 #define CANIDMR3_AM _CANIDMR3.MergedBits.grpAM
\r
5613 /*** CANIDAR4 - MSCAN Identifier Acceptance Register 4; 0x00000158 ***/
\r
5617 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
5618 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
5619 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
5620 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
5621 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
5622 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
5623 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
5624 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
5630 extern volatile CANIDAR4STR _CANIDAR4 @(REG_BASE + 0x00000158);
\r
5631 #define CANIDAR4 _CANIDAR4.Byte
\r
5632 #define CANIDAR4_AC0 _CANIDAR4.Bits.AC0
\r
5633 #define CANIDAR4_AC1 _CANIDAR4.Bits.AC1
\r
5634 #define CANIDAR4_AC2 _CANIDAR4.Bits.AC2
\r
5635 #define CANIDAR4_AC3 _CANIDAR4.Bits.AC3
\r
5636 #define CANIDAR4_AC4 _CANIDAR4.Bits.AC4
\r
5637 #define CANIDAR4_AC5 _CANIDAR4.Bits.AC5
\r
5638 #define CANIDAR4_AC6 _CANIDAR4.Bits.AC6
\r
5639 #define CANIDAR4_AC7 _CANIDAR4.Bits.AC7
\r
5640 #define CANIDAR4_AC _CANIDAR4.MergedBits.grpAC
\r
5643 /*** CANIDAR5 - MSCAN Identifier Acceptance Register 5; 0x00000159 ***/
\r
5647 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
5648 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
5649 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
5650 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
5651 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
5652 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
5653 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
5654 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
5660 extern volatile CANIDAR5STR _CANIDAR5 @(REG_BASE + 0x00000159);
\r
5661 #define CANIDAR5 _CANIDAR5.Byte
\r
5662 #define CANIDAR5_AC0 _CANIDAR5.Bits.AC0
\r
5663 #define CANIDAR5_AC1 _CANIDAR5.Bits.AC1
\r
5664 #define CANIDAR5_AC2 _CANIDAR5.Bits.AC2
\r
5665 #define CANIDAR5_AC3 _CANIDAR5.Bits.AC3
\r
5666 #define CANIDAR5_AC4 _CANIDAR5.Bits.AC4
\r
5667 #define CANIDAR5_AC5 _CANIDAR5.Bits.AC5
\r
5668 #define CANIDAR5_AC6 _CANIDAR5.Bits.AC6
\r
5669 #define CANIDAR5_AC7 _CANIDAR5.Bits.AC7
\r
5670 #define CANIDAR5_AC _CANIDAR5.MergedBits.grpAC
\r
5673 /*** CANIDAR6 - MSCAN Identifier Acceptance Register 6; 0x0000015A ***/
\r
5677 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
5678 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
5679 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
5680 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
5681 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
5682 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
5683 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
5684 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
5690 extern volatile CANIDAR6STR _CANIDAR6 @(REG_BASE + 0x0000015A);
\r
5691 #define CANIDAR6 _CANIDAR6.Byte
\r
5692 #define CANIDAR6_AC0 _CANIDAR6.Bits.AC0
\r
5693 #define CANIDAR6_AC1 _CANIDAR6.Bits.AC1
\r
5694 #define CANIDAR6_AC2 _CANIDAR6.Bits.AC2
\r
5695 #define CANIDAR6_AC3 _CANIDAR6.Bits.AC3
\r
5696 #define CANIDAR6_AC4 _CANIDAR6.Bits.AC4
\r
5697 #define CANIDAR6_AC5 _CANIDAR6.Bits.AC5
\r
5698 #define CANIDAR6_AC6 _CANIDAR6.Bits.AC6
\r
5699 #define CANIDAR6_AC7 _CANIDAR6.Bits.AC7
\r
5700 #define CANIDAR6_AC _CANIDAR6.MergedBits.grpAC
\r
5703 /*** CANIDAR7 - MSCAN Identifier Acceptance Register 7; 0x0000015B ***/
\r
5707 byte AC0 :1; /* Acceptance Code Bit 0 */
\r
5708 byte AC1 :1; /* Acceptance Code Bit 1 */
\r
5709 byte AC2 :1; /* Acceptance Code Bit 2 */
\r
5710 byte AC3 :1; /* Acceptance Code Bit 3 */
\r
5711 byte AC4 :1; /* Acceptance Code Bit 4 */
\r
5712 byte AC5 :1; /* Acceptance Code Bit 5 */
\r
5713 byte AC6 :1; /* Acceptance Code Bit 6 */
\r
5714 byte AC7 :1; /* Acceptance Code Bit 7 */
\r
5720 extern volatile CANIDAR7STR _CANIDAR7 @(REG_BASE + 0x0000015B);
\r
5721 #define CANIDAR7 _CANIDAR7.Byte
\r
5722 #define CANIDAR7_AC0 _CANIDAR7.Bits.AC0
\r
5723 #define CANIDAR7_AC1 _CANIDAR7.Bits.AC1
\r
5724 #define CANIDAR7_AC2 _CANIDAR7.Bits.AC2
\r
5725 #define CANIDAR7_AC3 _CANIDAR7.Bits.AC3
\r
5726 #define CANIDAR7_AC4 _CANIDAR7.Bits.AC4
\r
5727 #define CANIDAR7_AC5 _CANIDAR7.Bits.AC5
\r
5728 #define CANIDAR7_AC6 _CANIDAR7.Bits.AC6
\r
5729 #define CANIDAR7_AC7 _CANIDAR7.Bits.AC7
\r
5730 #define CANIDAR7_AC _CANIDAR7.MergedBits.grpAC
\r
5733 /*** CANIDMR4 - MSCAN Identifier Mask Register 4; 0x0000015C ***/
\r
5737 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
5738 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
5739 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
5740 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
5741 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
5742 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
5743 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
5744 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
5750 extern volatile CANIDMR4STR _CANIDMR4 @(REG_BASE + 0x0000015C);
\r
5751 #define CANIDMR4 _CANIDMR4.Byte
\r
5752 #define CANIDMR4_AM0 _CANIDMR4.Bits.AM0
\r
5753 #define CANIDMR4_AM1 _CANIDMR4.Bits.AM1
\r
5754 #define CANIDMR4_AM2 _CANIDMR4.Bits.AM2
\r
5755 #define CANIDMR4_AM3 _CANIDMR4.Bits.AM3
\r
5756 #define CANIDMR4_AM4 _CANIDMR4.Bits.AM4
\r
5757 #define CANIDMR4_AM5 _CANIDMR4.Bits.AM5
\r
5758 #define CANIDMR4_AM6 _CANIDMR4.Bits.AM6
\r
5759 #define CANIDMR4_AM7 _CANIDMR4.Bits.AM7
\r
5760 #define CANIDMR4_AM _CANIDMR4.MergedBits.grpAM
\r
5763 /*** CANIDMR5 - MSCAN Identifier Mask Register 5; 0x0000015D ***/
\r
5767 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
5768 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
5769 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
5770 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
5771 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
5772 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
5773 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
5774 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
5780 extern volatile CANIDMR5STR _CANIDMR5 @(REG_BASE + 0x0000015D);
\r
5781 #define CANIDMR5 _CANIDMR5.Byte
\r
5782 #define CANIDMR5_AM0 _CANIDMR5.Bits.AM0
\r
5783 #define CANIDMR5_AM1 _CANIDMR5.Bits.AM1
\r
5784 #define CANIDMR5_AM2 _CANIDMR5.Bits.AM2
\r
5785 #define CANIDMR5_AM3 _CANIDMR5.Bits.AM3
\r
5786 #define CANIDMR5_AM4 _CANIDMR5.Bits.AM4
\r
5787 #define CANIDMR5_AM5 _CANIDMR5.Bits.AM5
\r
5788 #define CANIDMR5_AM6 _CANIDMR5.Bits.AM6
\r
5789 #define CANIDMR5_AM7 _CANIDMR5.Bits.AM7
\r
5790 #define CANIDMR5_AM _CANIDMR5.MergedBits.grpAM
\r
5793 /*** CANIDMR6 - MSCAN Identifier Mask Register 6; 0x0000015E ***/
\r
5797 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
5798 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
5799 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
5800 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
5801 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
5802 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
5803 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
5804 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
5810 extern volatile CANIDMR6STR _CANIDMR6 @(REG_BASE + 0x0000015E);
\r
5811 #define CANIDMR6 _CANIDMR6.Byte
\r
5812 #define CANIDMR6_AM0 _CANIDMR6.Bits.AM0
\r
5813 #define CANIDMR6_AM1 _CANIDMR6.Bits.AM1
\r
5814 #define CANIDMR6_AM2 _CANIDMR6.Bits.AM2
\r
5815 #define CANIDMR6_AM3 _CANIDMR6.Bits.AM3
\r
5816 #define CANIDMR6_AM4 _CANIDMR6.Bits.AM4
\r
5817 #define CANIDMR6_AM5 _CANIDMR6.Bits.AM5
\r
5818 #define CANIDMR6_AM6 _CANIDMR6.Bits.AM6
\r
5819 #define CANIDMR6_AM7 _CANIDMR6.Bits.AM7
\r
5820 #define CANIDMR6_AM _CANIDMR6.MergedBits.grpAM
\r
5823 /*** CANIDMR7 - MSCAN Identifier Mask Register 7; 0x0000015F ***/
\r
5827 byte AM0 :1; /* Acceptance Mask Bit 0 */
\r
5828 byte AM1 :1; /* Acceptance Mask Bit 1 */
\r
5829 byte AM2 :1; /* Acceptance Mask Bit 2 */
\r
5830 byte AM3 :1; /* Acceptance Mask Bit 3 */
\r
5831 byte AM4 :1; /* Acceptance Mask Bit 4 */
\r
5832 byte AM5 :1; /* Acceptance Mask Bit 5 */
\r
5833 byte AM6 :1; /* Acceptance Mask Bit 6 */
\r
5834 byte AM7 :1; /* Acceptance Mask Bit 7 */
\r
5840 extern volatile CANIDMR7STR _CANIDMR7 @(REG_BASE + 0x0000015F);
\r
5841 #define CANIDMR7 _CANIDMR7.Byte
\r
5842 #define CANIDMR7_AM0 _CANIDMR7.Bits.AM0
\r
5843 #define CANIDMR7_AM1 _CANIDMR7.Bits.AM1
\r
5844 #define CANIDMR7_AM2 _CANIDMR7.Bits.AM2
\r
5845 #define CANIDMR7_AM3 _CANIDMR7.Bits.AM3
\r
5846 #define CANIDMR7_AM4 _CANIDMR7.Bits.AM4
\r
5847 #define CANIDMR7_AM5 _CANIDMR7.Bits.AM5
\r
5848 #define CANIDMR7_AM6 _CANIDMR7.Bits.AM6
\r
5849 #define CANIDMR7_AM7 _CANIDMR7.Bits.AM7
\r
5850 #define CANIDMR7_AM _CANIDMR7.MergedBits.grpAM
\r
5853 /*** CANRXIDR0 - MSCAN Receive Identifier Register 0; 0x00000160 ***/
\r
5857 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
5858 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
5859 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
5860 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
5861 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
5862 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
5863 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
5864 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
5870 extern volatile CANRXIDR0STR _CANRXIDR0 @(REG_BASE + 0x00000160);
\r
5871 #define CANRXIDR0 _CANRXIDR0.Byte
\r
5872 #define CANRXIDR0_ID21 _CANRXIDR0.Bits.ID21
\r
5873 #define CANRXIDR0_ID22 _CANRXIDR0.Bits.ID22
\r
5874 #define CANRXIDR0_ID23 _CANRXIDR0.Bits.ID23
\r
5875 #define CANRXIDR0_ID24 _CANRXIDR0.Bits.ID24
\r
5876 #define CANRXIDR0_ID25 _CANRXIDR0.Bits.ID25
\r
5877 #define CANRXIDR0_ID26 _CANRXIDR0.Bits.ID26
\r
5878 #define CANRXIDR0_ID27 _CANRXIDR0.Bits.ID27
\r
5879 #define CANRXIDR0_ID28 _CANRXIDR0.Bits.ID28
\r
5880 #define CANRXIDR0_ID_21 _CANRXIDR0.MergedBits.grpID_21
\r
5881 #define CANRXIDR0_ID CANRXIDR0_ID_21
\r
5884 /*** CANRXIDR1 - MSCAN Receive Identifier Register 1; 0x00000161 ***/
\r
5888 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
5889 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
5890 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
5891 byte IDE :1; /* ID Extended */
\r
5892 byte SRR :1; /* Substitute Remote Request */
\r
5893 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
5894 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
5895 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
5904 extern volatile CANRXIDR1STR _CANRXIDR1 @(REG_BASE + 0x00000161);
\r
5905 #define CANRXIDR1 _CANRXIDR1.Byte
\r
5906 #define CANRXIDR1_ID15 _CANRXIDR1.Bits.ID15
\r
5907 #define CANRXIDR1_ID16 _CANRXIDR1.Bits.ID16
\r
5908 #define CANRXIDR1_ID17 _CANRXIDR1.Bits.ID17
\r
5909 #define CANRXIDR1_IDE _CANRXIDR1.Bits.IDE
\r
5910 #define CANRXIDR1_SRR _CANRXIDR1.Bits.SRR
\r
5911 #define CANRXIDR1_ID18 _CANRXIDR1.Bits.ID18
\r
5912 #define CANRXIDR1_ID19 _CANRXIDR1.Bits.ID19
\r
5913 #define CANRXIDR1_ID20 _CANRXIDR1.Bits.ID20
\r
5914 #define CANRXIDR1_ID_15 _CANRXIDR1.MergedBits.grpID_15
\r
5915 #define CANRXIDR1_ID_18 _CANRXIDR1.MergedBits.grpID_18
\r
5916 #define CANRXIDR1_ID CANRXIDR1_ID_15
\r
5919 /*** CANRXIDR2 - MSCAN Receive Identifier Register 2; 0x00000162 ***/
\r
5923 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
5924 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
5925 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
5926 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
5927 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
5928 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
5929 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
5930 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
5936 extern volatile CANRXIDR2STR _CANRXIDR2 @(REG_BASE + 0x00000162);
\r
5937 #define CANRXIDR2 _CANRXIDR2.Byte
\r
5938 #define CANRXIDR2_ID7 _CANRXIDR2.Bits.ID7
\r
5939 #define CANRXIDR2_ID8 _CANRXIDR2.Bits.ID8
\r
5940 #define CANRXIDR2_ID9 _CANRXIDR2.Bits.ID9
\r
5941 #define CANRXIDR2_ID10 _CANRXIDR2.Bits.ID10
\r
5942 #define CANRXIDR2_ID11 _CANRXIDR2.Bits.ID11
\r
5943 #define CANRXIDR2_ID12 _CANRXIDR2.Bits.ID12
\r
5944 #define CANRXIDR2_ID13 _CANRXIDR2.Bits.ID13
\r
5945 #define CANRXIDR2_ID14 _CANRXIDR2.Bits.ID14
\r
5946 #define CANRXIDR2_ID_7 _CANRXIDR2.MergedBits.grpID_7
\r
5947 #define CANRXIDR2_ID CANRXIDR2_ID_7
\r
5950 /*** CANRXIDR3 - MSCAN Receive Identifier Register 3; 0x00000163 ***/
\r
5954 byte RTR :1; /* Remote Transmission Request */
\r
5955 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
5956 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
5957 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
5958 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
5959 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
5960 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
5961 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
5968 extern volatile CANRXIDR3STR _CANRXIDR3 @(REG_BASE + 0x00000163);
\r
5969 #define CANRXIDR3 _CANRXIDR3.Byte
\r
5970 #define CANRXIDR3_RTR _CANRXIDR3.Bits.RTR
\r
5971 #define CANRXIDR3_ID0 _CANRXIDR3.Bits.ID0
\r
5972 #define CANRXIDR3_ID1 _CANRXIDR3.Bits.ID1
\r
5973 #define CANRXIDR3_ID2 _CANRXIDR3.Bits.ID2
\r
5974 #define CANRXIDR3_ID3 _CANRXIDR3.Bits.ID3
\r
5975 #define CANRXIDR3_ID4 _CANRXIDR3.Bits.ID4
\r
5976 #define CANRXIDR3_ID5 _CANRXIDR3.Bits.ID5
\r
5977 #define CANRXIDR3_ID6 _CANRXIDR3.Bits.ID6
\r
5978 #define CANRXIDR3_ID _CANRXIDR3.MergedBits.grpID
\r
5981 /*** CANRXDSR0 - MSCAN Receive Data Segment Register 0; 0x00000164 ***/
\r
5985 byte DB0 :1; /* Data Bit 0 */
\r
5986 byte DB1 :1; /* Data Bit 1 */
\r
5987 byte DB2 :1; /* Data Bit 2 */
\r
5988 byte DB3 :1; /* Data Bit 3 */
\r
5989 byte DB4 :1; /* Data Bit 4 */
\r
5990 byte DB5 :1; /* Data Bit 5 */
\r
5991 byte DB6 :1; /* Data Bit 6 */
\r
5992 byte DB7 :1; /* Data Bit 7 */
\r
5998 extern volatile CANRXDSR0STR _CANRXDSR0 @(REG_BASE + 0x00000164);
\r
5999 #define CANRXDSR0 _CANRXDSR0.Byte
\r
6000 #define CANRXDSR0_DB0 _CANRXDSR0.Bits.DB0
\r
6001 #define CANRXDSR0_DB1 _CANRXDSR0.Bits.DB1
\r
6002 #define CANRXDSR0_DB2 _CANRXDSR0.Bits.DB2
\r
6003 #define CANRXDSR0_DB3 _CANRXDSR0.Bits.DB3
\r
6004 #define CANRXDSR0_DB4 _CANRXDSR0.Bits.DB4
\r
6005 #define CANRXDSR0_DB5 _CANRXDSR0.Bits.DB5
\r
6006 #define CANRXDSR0_DB6 _CANRXDSR0.Bits.DB6
\r
6007 #define CANRXDSR0_DB7 _CANRXDSR0.Bits.DB7
\r
6008 #define CANRXDSR0_DB _CANRXDSR0.MergedBits.grpDB
\r
6011 /*** CANRXDSR1 - MSCAN Receive Data Segment Register 1; 0x00000165 ***/
\r
6015 byte DB0 :1; /* Data Bit 0 */
\r
6016 byte DB1 :1; /* Data Bit 1 */
\r
6017 byte DB2 :1; /* Data Bit 2 */
\r
6018 byte DB3 :1; /* Data Bit 3 */
\r
6019 byte DB4 :1; /* Data Bit 4 */
\r
6020 byte DB5 :1; /* Data Bit 5 */
\r
6021 byte DB6 :1; /* Data Bit 6 */
\r
6022 byte DB7 :1; /* Data Bit 7 */
\r
6028 extern volatile CANRXDSR1STR _CANRXDSR1 @(REG_BASE + 0x00000165);
\r
6029 #define CANRXDSR1 _CANRXDSR1.Byte
\r
6030 #define CANRXDSR1_DB0 _CANRXDSR1.Bits.DB0
\r
6031 #define CANRXDSR1_DB1 _CANRXDSR1.Bits.DB1
\r
6032 #define CANRXDSR1_DB2 _CANRXDSR1.Bits.DB2
\r
6033 #define CANRXDSR1_DB3 _CANRXDSR1.Bits.DB3
\r
6034 #define CANRXDSR1_DB4 _CANRXDSR1.Bits.DB4
\r
6035 #define CANRXDSR1_DB5 _CANRXDSR1.Bits.DB5
\r
6036 #define CANRXDSR1_DB6 _CANRXDSR1.Bits.DB6
\r
6037 #define CANRXDSR1_DB7 _CANRXDSR1.Bits.DB7
\r
6038 #define CANRXDSR1_DB _CANRXDSR1.MergedBits.grpDB
\r
6041 /*** CANRXDSR2 - MSCAN Receive Data Segment Register 2; 0x00000166 ***/
\r
6045 byte DB0 :1; /* Data Bit 0 */
\r
6046 byte DB1 :1; /* Data Bit 1 */
\r
6047 byte DB2 :1; /* Data Bit 2 */
\r
6048 byte DB3 :1; /* Data Bit 3 */
\r
6049 byte DB4 :1; /* Data Bit 4 */
\r
6050 byte DB5 :1; /* Data Bit 5 */
\r
6051 byte DB6 :1; /* Data Bit 6 */
\r
6052 byte DB7 :1; /* Data Bit 7 */
\r
6058 extern volatile CANRXDSR2STR _CANRXDSR2 @(REG_BASE + 0x00000166);
\r
6059 #define CANRXDSR2 _CANRXDSR2.Byte
\r
6060 #define CANRXDSR2_DB0 _CANRXDSR2.Bits.DB0
\r
6061 #define CANRXDSR2_DB1 _CANRXDSR2.Bits.DB1
\r
6062 #define CANRXDSR2_DB2 _CANRXDSR2.Bits.DB2
\r
6063 #define CANRXDSR2_DB3 _CANRXDSR2.Bits.DB3
\r
6064 #define CANRXDSR2_DB4 _CANRXDSR2.Bits.DB4
\r
6065 #define CANRXDSR2_DB5 _CANRXDSR2.Bits.DB5
\r
6066 #define CANRXDSR2_DB6 _CANRXDSR2.Bits.DB6
\r
6067 #define CANRXDSR2_DB7 _CANRXDSR2.Bits.DB7
\r
6068 #define CANRXDSR2_DB _CANRXDSR2.MergedBits.grpDB
\r
6071 /*** CANRXDSR3 - MSCAN Receive Data Segment Register 3; 0x00000167 ***/
\r
6075 byte DB0 :1; /* Data Bit 0 */
\r
6076 byte DB1 :1; /* Data Bit 1 */
\r
6077 byte DB2 :1; /* Data Bit 2 */
\r
6078 byte DB3 :1; /* Data Bit 3 */
\r
6079 byte DB4 :1; /* Data Bit 4 */
\r
6080 byte DB5 :1; /* Data Bit 5 */
\r
6081 byte DB6 :1; /* Data Bit 6 */
\r
6082 byte DB7 :1; /* Data Bit 7 */
\r
6088 extern volatile CANRXDSR3STR _CANRXDSR3 @(REG_BASE + 0x00000167);
\r
6089 #define CANRXDSR3 _CANRXDSR3.Byte
\r
6090 #define CANRXDSR3_DB0 _CANRXDSR3.Bits.DB0
\r
6091 #define CANRXDSR3_DB1 _CANRXDSR3.Bits.DB1
\r
6092 #define CANRXDSR3_DB2 _CANRXDSR3.Bits.DB2
\r
6093 #define CANRXDSR3_DB3 _CANRXDSR3.Bits.DB3
\r
6094 #define CANRXDSR3_DB4 _CANRXDSR3.Bits.DB4
\r
6095 #define CANRXDSR3_DB5 _CANRXDSR3.Bits.DB5
\r
6096 #define CANRXDSR3_DB6 _CANRXDSR3.Bits.DB6
\r
6097 #define CANRXDSR3_DB7 _CANRXDSR3.Bits.DB7
\r
6098 #define CANRXDSR3_DB _CANRXDSR3.MergedBits.grpDB
\r
6101 /*** CANRXDSR4 - MSCAN Receive Data Segment Register 4; 0x00000168 ***/
\r
6105 byte DB0 :1; /* Data Bit 0 */
\r
6106 byte DB1 :1; /* Data Bit 1 */
\r
6107 byte DB2 :1; /* Data Bit 2 */
\r
6108 byte DB3 :1; /* Data Bit 3 */
\r
6109 byte DB4 :1; /* Data Bit 4 */
\r
6110 byte DB5 :1; /* Data Bit 5 */
\r
6111 byte DB6 :1; /* Data Bit 6 */
\r
6112 byte DB7 :1; /* Data Bit 7 */
\r
6118 extern volatile CANRXDSR4STR _CANRXDSR4 @(REG_BASE + 0x00000168);
\r
6119 #define CANRXDSR4 _CANRXDSR4.Byte
\r
6120 #define CANRXDSR4_DB0 _CANRXDSR4.Bits.DB0
\r
6121 #define CANRXDSR4_DB1 _CANRXDSR4.Bits.DB1
\r
6122 #define CANRXDSR4_DB2 _CANRXDSR4.Bits.DB2
\r
6123 #define CANRXDSR4_DB3 _CANRXDSR4.Bits.DB3
\r
6124 #define CANRXDSR4_DB4 _CANRXDSR4.Bits.DB4
\r
6125 #define CANRXDSR4_DB5 _CANRXDSR4.Bits.DB5
\r
6126 #define CANRXDSR4_DB6 _CANRXDSR4.Bits.DB6
\r
6127 #define CANRXDSR4_DB7 _CANRXDSR4.Bits.DB7
\r
6128 #define CANRXDSR4_DB _CANRXDSR4.MergedBits.grpDB
\r
6131 /*** CANRXDSR5 - MSCAN Receive Data Segment Register 5; 0x00000169 ***/
\r
6135 byte DB0 :1; /* Data Bit 0 */
\r
6136 byte DB1 :1; /* Data Bit 1 */
\r
6137 byte DB2 :1; /* Data Bit 2 */
\r
6138 byte DB3 :1; /* Data Bit 3 */
\r
6139 byte DB4 :1; /* Data Bit 4 */
\r
6140 byte DB5 :1; /* Data Bit 5 */
\r
6141 byte DB6 :1; /* Data Bit 6 */
\r
6142 byte DB7 :1; /* Data Bit 7 */
\r
6148 extern volatile CANRXDSR5STR _CANRXDSR5 @(REG_BASE + 0x00000169);
\r
6149 #define CANRXDSR5 _CANRXDSR5.Byte
\r
6150 #define CANRXDSR5_DB0 _CANRXDSR5.Bits.DB0
\r
6151 #define CANRXDSR5_DB1 _CANRXDSR5.Bits.DB1
\r
6152 #define CANRXDSR5_DB2 _CANRXDSR5.Bits.DB2
\r
6153 #define CANRXDSR5_DB3 _CANRXDSR5.Bits.DB3
\r
6154 #define CANRXDSR5_DB4 _CANRXDSR5.Bits.DB4
\r
6155 #define CANRXDSR5_DB5 _CANRXDSR5.Bits.DB5
\r
6156 #define CANRXDSR5_DB6 _CANRXDSR5.Bits.DB6
\r
6157 #define CANRXDSR5_DB7 _CANRXDSR5.Bits.DB7
\r
6158 #define CANRXDSR5_DB _CANRXDSR5.MergedBits.grpDB
\r
6161 /*** CANRXDSR6 - MSCAN Receive Data Segment Register 6; 0x0000016A ***/
\r
6165 byte DB0 :1; /* Data Bit 0 */
\r
6166 byte DB1 :1; /* Data Bit 1 */
\r
6167 byte DB2 :1; /* Data Bit 2 */
\r
6168 byte DB3 :1; /* Data Bit 3 */
\r
6169 byte DB4 :1; /* Data Bit 4 */
\r
6170 byte DB5 :1; /* Data Bit 5 */
\r
6171 byte DB6 :1; /* Data Bit 6 */
\r
6172 byte DB7 :1; /* Data Bit 7 */
\r
6178 extern volatile CANRXDSR6STR _CANRXDSR6 @(REG_BASE + 0x0000016A);
\r
6179 #define CANRXDSR6 _CANRXDSR6.Byte
\r
6180 #define CANRXDSR6_DB0 _CANRXDSR6.Bits.DB0
\r
6181 #define CANRXDSR6_DB1 _CANRXDSR6.Bits.DB1
\r
6182 #define CANRXDSR6_DB2 _CANRXDSR6.Bits.DB2
\r
6183 #define CANRXDSR6_DB3 _CANRXDSR6.Bits.DB3
\r
6184 #define CANRXDSR6_DB4 _CANRXDSR6.Bits.DB4
\r
6185 #define CANRXDSR6_DB5 _CANRXDSR6.Bits.DB5
\r
6186 #define CANRXDSR6_DB6 _CANRXDSR6.Bits.DB6
\r
6187 #define CANRXDSR6_DB7 _CANRXDSR6.Bits.DB7
\r
6188 #define CANRXDSR6_DB _CANRXDSR6.MergedBits.grpDB
\r
6191 /*** CANRXDSR7 - MSCAN Receive Data Segment Register 7; 0x0000016B ***/
\r
6195 byte DB0 :1; /* Data Bit 0 */
\r
6196 byte DB1 :1; /* Data Bit 1 */
\r
6197 byte DB2 :1; /* Data Bit 2 */
\r
6198 byte DB3 :1; /* Data Bit 3 */
\r
6199 byte DB4 :1; /* Data Bit 4 */
\r
6200 byte DB5 :1; /* Data Bit 5 */
\r
6201 byte DB6 :1; /* Data Bit 6 */
\r
6202 byte DB7 :1; /* Data Bit 7 */
\r
6208 extern volatile CANRXDSR7STR _CANRXDSR7 @(REG_BASE + 0x0000016B);
\r
6209 #define CANRXDSR7 _CANRXDSR7.Byte
\r
6210 #define CANRXDSR7_DB0 _CANRXDSR7.Bits.DB0
\r
6211 #define CANRXDSR7_DB1 _CANRXDSR7.Bits.DB1
\r
6212 #define CANRXDSR7_DB2 _CANRXDSR7.Bits.DB2
\r
6213 #define CANRXDSR7_DB3 _CANRXDSR7.Bits.DB3
\r
6214 #define CANRXDSR7_DB4 _CANRXDSR7.Bits.DB4
\r
6215 #define CANRXDSR7_DB5 _CANRXDSR7.Bits.DB5
\r
6216 #define CANRXDSR7_DB6 _CANRXDSR7.Bits.DB6
\r
6217 #define CANRXDSR7_DB7 _CANRXDSR7.Bits.DB7
\r
6218 #define CANRXDSR7_DB _CANRXDSR7.MergedBits.grpDB
\r
6221 /*** CANRXDLR - MSCAN Receive Data Length Register; 0x0000016C ***/
\r
6225 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
6226 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
6227 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
6228 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
6242 extern volatile CANRXDLRSTR _CANRXDLR @(REG_BASE + 0x0000016C);
\r
6243 #define CANRXDLR _CANRXDLR.Byte
\r
6244 #define CANRXDLR_DLC0 _CANRXDLR.Bits.DLC0
\r
6245 #define CANRXDLR_DLC1 _CANRXDLR.Bits.DLC1
\r
6246 #define CANRXDLR_DLC2 _CANRXDLR.Bits.DLC2
\r
6247 #define CANRXDLR_DLC3 _CANRXDLR.Bits.DLC3
\r
6248 #define CANRXDLR_DLC _CANRXDLR.MergedBits.grpDLC
\r
6251 /*** CANTXIDR0 - MSCAN Transmit Identifier Register 0; 0x00000170 ***/
\r
6255 byte ID21 :1; /* Extended format identifier Bit 21 */
\r
6256 byte ID22 :1; /* Extended format identifier Bit 22 */
\r
6257 byte ID23 :1; /* Extended format identifier Bit 23 */
\r
6258 byte ID24 :1; /* Extended format identifier Bit 24 */
\r
6259 byte ID25 :1; /* Extended format identifier Bit 25 */
\r
6260 byte ID26 :1; /* Extended format identifier Bit 26 */
\r
6261 byte ID27 :1; /* Extended format identifier Bit 27 */
\r
6262 byte ID28 :1; /* Extended format identifier Bit 28 */
\r
6268 extern volatile CANTXIDR0STR _CANTXIDR0 @(REG_BASE + 0x00000170);
\r
6269 #define CANTXIDR0 _CANTXIDR0.Byte
\r
6270 #define CANTXIDR0_ID21 _CANTXIDR0.Bits.ID21
\r
6271 #define CANTXIDR0_ID22 _CANTXIDR0.Bits.ID22
\r
6272 #define CANTXIDR0_ID23 _CANTXIDR0.Bits.ID23
\r
6273 #define CANTXIDR0_ID24 _CANTXIDR0.Bits.ID24
\r
6274 #define CANTXIDR0_ID25 _CANTXIDR0.Bits.ID25
\r
6275 #define CANTXIDR0_ID26 _CANTXIDR0.Bits.ID26
\r
6276 #define CANTXIDR0_ID27 _CANTXIDR0.Bits.ID27
\r
6277 #define CANTXIDR0_ID28 _CANTXIDR0.Bits.ID28
\r
6278 #define CANTXIDR0_ID_21 _CANTXIDR0.MergedBits.grpID_21
\r
6279 #define CANTXIDR0_ID CANTXIDR0_ID_21
\r
6282 /*** CANTXIDR1 - MSCAN Transmit Identifier Register 1; 0x00000171 ***/
\r
6286 byte ID15 :1; /* Extended format identifier Bit 15 */
\r
6287 byte ID16 :1; /* Extended format identifier Bit 16 */
\r
6288 byte ID17 :1; /* Extended format identifier Bit 17 */
\r
6289 byte IDE :1; /* ID Extended */
\r
6290 byte SRR :1; /* Substitute Remote Request */
\r
6291 byte ID18 :1; /* Extended format identifier Bit 18 */
\r
6292 byte ID19 :1; /* Extended format identifier Bit 19 */
\r
6293 byte ID20 :1; /* Extended format identifier Bit 20 */
\r
6302 extern volatile CANTXIDR1STR _CANTXIDR1 @(REG_BASE + 0x00000171);
\r
6303 #define CANTXIDR1 _CANTXIDR1.Byte
\r
6304 #define CANTXIDR1_ID15 _CANTXIDR1.Bits.ID15
\r
6305 #define CANTXIDR1_ID16 _CANTXIDR1.Bits.ID16
\r
6306 #define CANTXIDR1_ID17 _CANTXIDR1.Bits.ID17
\r
6307 #define CANTXIDR1_IDE _CANTXIDR1.Bits.IDE
\r
6308 #define CANTXIDR1_SRR _CANTXIDR1.Bits.SRR
\r
6309 #define CANTXIDR1_ID18 _CANTXIDR1.Bits.ID18
\r
6310 #define CANTXIDR1_ID19 _CANTXIDR1.Bits.ID19
\r
6311 #define CANTXIDR1_ID20 _CANTXIDR1.Bits.ID20
\r
6312 #define CANTXIDR1_ID_15 _CANTXIDR1.MergedBits.grpID_15
\r
6313 #define CANTXIDR1_ID_18 _CANTXIDR1.MergedBits.grpID_18
\r
6314 #define CANTXIDR1_ID CANTXIDR1_ID_15
\r
6317 /*** CANTXIDR2 - MSCAN Transmit Identifier Register 2; 0x00000172 ***/
\r
6321 byte ID7 :1; /* Extended format identifier Bit 7 */
\r
6322 byte ID8 :1; /* Extended format identifier Bit 8 */
\r
6323 byte ID9 :1; /* Extended format identifier Bit 9 */
\r
6324 byte ID10 :1; /* Extended format identifier Bit 10 */
\r
6325 byte ID11 :1; /* Extended format identifier Bit 11 */
\r
6326 byte ID12 :1; /* Extended format identifier Bit 12 */
\r
6327 byte ID13 :1; /* Extended format identifier Bit 13 */
\r
6328 byte ID14 :1; /* Extended format identifier Bit 14 */
\r
6334 extern volatile CANTXIDR2STR _CANTXIDR2 @(REG_BASE + 0x00000172);
\r
6335 #define CANTXIDR2 _CANTXIDR2.Byte
\r
6336 #define CANTXIDR2_ID7 _CANTXIDR2.Bits.ID7
\r
6337 #define CANTXIDR2_ID8 _CANTXIDR2.Bits.ID8
\r
6338 #define CANTXIDR2_ID9 _CANTXIDR2.Bits.ID9
\r
6339 #define CANTXIDR2_ID10 _CANTXIDR2.Bits.ID10
\r
6340 #define CANTXIDR2_ID11 _CANTXIDR2.Bits.ID11
\r
6341 #define CANTXIDR2_ID12 _CANTXIDR2.Bits.ID12
\r
6342 #define CANTXIDR2_ID13 _CANTXIDR2.Bits.ID13
\r
6343 #define CANTXIDR2_ID14 _CANTXIDR2.Bits.ID14
\r
6344 #define CANTXIDR2_ID_7 _CANTXIDR2.MergedBits.grpID_7
\r
6345 #define CANTXIDR2_ID CANTXIDR2_ID_7
\r
6348 /*** CANTXIDR3 - MSCAN Transmit Identifier Register 3; 0x00000173 ***/
\r
6352 byte RTR :1; /* Remote Transmission Request */
\r
6353 byte ID0 :1; /* Extended format identifier Bit 0 */
\r
6354 byte ID1 :1; /* Extended format identifier Bit 1 */
\r
6355 byte ID2 :1; /* Extended format identifier Bit 2 */
\r
6356 byte ID3 :1; /* Extended format identifier Bit 3 */
\r
6357 byte ID4 :1; /* Extended format identifier Bit 4 */
\r
6358 byte ID5 :1; /* Extended format identifier Bit 5 */
\r
6359 byte ID6 :1; /* Extended format identifier Bit 6 */
\r
6366 extern volatile CANTXIDR3STR _CANTXIDR3 @(REG_BASE + 0x00000173);
\r
6367 #define CANTXIDR3 _CANTXIDR3.Byte
\r
6368 #define CANTXIDR3_RTR _CANTXIDR3.Bits.RTR
\r
6369 #define CANTXIDR3_ID0 _CANTXIDR3.Bits.ID0
\r
6370 #define CANTXIDR3_ID1 _CANTXIDR3.Bits.ID1
\r
6371 #define CANTXIDR3_ID2 _CANTXIDR3.Bits.ID2
\r
6372 #define CANTXIDR3_ID3 _CANTXIDR3.Bits.ID3
\r
6373 #define CANTXIDR3_ID4 _CANTXIDR3.Bits.ID4
\r
6374 #define CANTXIDR3_ID5 _CANTXIDR3.Bits.ID5
\r
6375 #define CANTXIDR3_ID6 _CANTXIDR3.Bits.ID6
\r
6376 #define CANTXIDR3_ID _CANTXIDR3.MergedBits.grpID
\r
6379 /*** CANTXDSR0 - MSCAN Transmit Data Segment Register 0; 0x00000174 ***/
\r
6383 byte DB0 :1; /* Data Bit 0 */
\r
6384 byte DB1 :1; /* Data Bit 1 */
\r
6385 byte DB2 :1; /* Data Bit 2 */
\r
6386 byte DB3 :1; /* Data Bit 3 */
\r
6387 byte DB4 :1; /* Data Bit 4 */
\r
6388 byte DB5 :1; /* Data Bit 5 */
\r
6389 byte DB6 :1; /* Data Bit 6 */
\r
6390 byte DB7 :1; /* Data Bit 7 */
\r
6396 extern volatile CANTXDSR0STR _CANTXDSR0 @(REG_BASE + 0x00000174);
\r
6397 #define CANTXDSR0 _CANTXDSR0.Byte
\r
6398 #define CANTXDSR0_DB0 _CANTXDSR0.Bits.DB0
\r
6399 #define CANTXDSR0_DB1 _CANTXDSR0.Bits.DB1
\r
6400 #define CANTXDSR0_DB2 _CANTXDSR0.Bits.DB2
\r
6401 #define CANTXDSR0_DB3 _CANTXDSR0.Bits.DB3
\r
6402 #define CANTXDSR0_DB4 _CANTXDSR0.Bits.DB4
\r
6403 #define CANTXDSR0_DB5 _CANTXDSR0.Bits.DB5
\r
6404 #define CANTXDSR0_DB6 _CANTXDSR0.Bits.DB6
\r
6405 #define CANTXDSR0_DB7 _CANTXDSR0.Bits.DB7
\r
6406 #define CANTXDSR0_DB _CANTXDSR0.MergedBits.grpDB
\r
6409 /*** CANTXDSR1 - MSCAN Transmit Data Segment Register 1; 0x00000175 ***/
\r
6413 byte DB0 :1; /* Data Bit 0 */
\r
6414 byte DB1 :1; /* Data Bit 1 */
\r
6415 byte DB2 :1; /* Data Bit 2 */
\r
6416 byte DB3 :1; /* Data Bit 3 */
\r
6417 byte DB4 :1; /* Data Bit 4 */
\r
6418 byte DB5 :1; /* Data Bit 5 */
\r
6419 byte DB6 :1; /* Data Bit 6 */
\r
6420 byte DB7 :1; /* Data Bit 7 */
\r
6426 extern volatile CANTXDSR1STR _CANTXDSR1 @(REG_BASE + 0x00000175);
\r
6427 #define CANTXDSR1 _CANTXDSR1.Byte
\r
6428 #define CANTXDSR1_DB0 _CANTXDSR1.Bits.DB0
\r
6429 #define CANTXDSR1_DB1 _CANTXDSR1.Bits.DB1
\r
6430 #define CANTXDSR1_DB2 _CANTXDSR1.Bits.DB2
\r
6431 #define CANTXDSR1_DB3 _CANTXDSR1.Bits.DB3
\r
6432 #define CANTXDSR1_DB4 _CANTXDSR1.Bits.DB4
\r
6433 #define CANTXDSR1_DB5 _CANTXDSR1.Bits.DB5
\r
6434 #define CANTXDSR1_DB6 _CANTXDSR1.Bits.DB6
\r
6435 #define CANTXDSR1_DB7 _CANTXDSR1.Bits.DB7
\r
6436 #define CANTXDSR1_DB _CANTXDSR1.MergedBits.grpDB
\r
6439 /*** CANTXDSR2 - MSCAN Transmit Data Segment Register 2; 0x00000176 ***/
\r
6443 byte DB0 :1; /* Data Bit 0 */
\r
6444 byte DB1 :1; /* Data Bit 1 */
\r
6445 byte DB2 :1; /* Data Bit 2 */
\r
6446 byte DB3 :1; /* Data Bit 3 */
\r
6447 byte DB4 :1; /* Data Bit 4 */
\r
6448 byte DB5 :1; /* Data Bit 5 */
\r
6449 byte DB6 :1; /* Data Bit 6 */
\r
6450 byte DB7 :1; /* Data Bit 7 */
\r
6456 extern volatile CANTXDSR2STR _CANTXDSR2 @(REG_BASE + 0x00000176);
\r
6457 #define CANTXDSR2 _CANTXDSR2.Byte
\r
6458 #define CANTXDSR2_DB0 _CANTXDSR2.Bits.DB0
\r
6459 #define CANTXDSR2_DB1 _CANTXDSR2.Bits.DB1
\r
6460 #define CANTXDSR2_DB2 _CANTXDSR2.Bits.DB2
\r
6461 #define CANTXDSR2_DB3 _CANTXDSR2.Bits.DB3
\r
6462 #define CANTXDSR2_DB4 _CANTXDSR2.Bits.DB4
\r
6463 #define CANTXDSR2_DB5 _CANTXDSR2.Bits.DB5
\r
6464 #define CANTXDSR2_DB6 _CANTXDSR2.Bits.DB6
\r
6465 #define CANTXDSR2_DB7 _CANTXDSR2.Bits.DB7
\r
6466 #define CANTXDSR2_DB _CANTXDSR2.MergedBits.grpDB
\r
6469 /*** CANTXDSR3 - MSCAN Transmit Data Segment Register 3; 0x00000177 ***/
\r
6473 byte DB0 :1; /* Data Bit 0 */
\r
6474 byte DB1 :1; /* Data Bit 1 */
\r
6475 byte DB2 :1; /* Data Bit 2 */
\r
6476 byte DB3 :1; /* Data Bit 3 */
\r
6477 byte DB4 :1; /* Data Bit 4 */
\r
6478 byte DB5 :1; /* Data Bit 5 */
\r
6479 byte DB6 :1; /* Data Bit 6 */
\r
6480 byte DB7 :1; /* Data Bit 7 */
\r
6486 extern volatile CANTXDSR3STR _CANTXDSR3 @(REG_BASE + 0x00000177);
\r
6487 #define CANTXDSR3 _CANTXDSR3.Byte
\r
6488 #define CANTXDSR3_DB0 _CANTXDSR3.Bits.DB0
\r
6489 #define CANTXDSR3_DB1 _CANTXDSR3.Bits.DB1
\r
6490 #define CANTXDSR3_DB2 _CANTXDSR3.Bits.DB2
\r
6491 #define CANTXDSR3_DB3 _CANTXDSR3.Bits.DB3
\r
6492 #define CANTXDSR3_DB4 _CANTXDSR3.Bits.DB4
\r
6493 #define CANTXDSR3_DB5 _CANTXDSR3.Bits.DB5
\r
6494 #define CANTXDSR3_DB6 _CANTXDSR3.Bits.DB6
\r
6495 #define CANTXDSR3_DB7 _CANTXDSR3.Bits.DB7
\r
6496 #define CANTXDSR3_DB _CANTXDSR3.MergedBits.grpDB
\r
6499 /*** CANTXDSR4 - MSCAN Transmit Data Segment Register 4; 0x00000178 ***/
\r
6503 byte DB0 :1; /* Data Bit 0 */
\r
6504 byte DB1 :1; /* Data Bit 1 */
\r
6505 byte DB2 :1; /* Data Bit 2 */
\r
6506 byte DB3 :1; /* Data Bit 3 */
\r
6507 byte DB4 :1; /* Data Bit 4 */
\r
6508 byte DB5 :1; /* Data Bit 5 */
\r
6509 byte DB6 :1; /* Data Bit 6 */
\r
6510 byte DB7 :1; /* Data Bit 7 */
\r
6516 extern volatile CANTXDSR4STR _CANTXDSR4 @(REG_BASE + 0x00000178);
\r
6517 #define CANTXDSR4 _CANTXDSR4.Byte
\r
6518 #define CANTXDSR4_DB0 _CANTXDSR4.Bits.DB0
\r
6519 #define CANTXDSR4_DB1 _CANTXDSR4.Bits.DB1
\r
6520 #define CANTXDSR4_DB2 _CANTXDSR4.Bits.DB2
\r
6521 #define CANTXDSR4_DB3 _CANTXDSR4.Bits.DB3
\r
6522 #define CANTXDSR4_DB4 _CANTXDSR4.Bits.DB4
\r
6523 #define CANTXDSR4_DB5 _CANTXDSR4.Bits.DB5
\r
6524 #define CANTXDSR4_DB6 _CANTXDSR4.Bits.DB6
\r
6525 #define CANTXDSR4_DB7 _CANTXDSR4.Bits.DB7
\r
6526 #define CANTXDSR4_DB _CANTXDSR4.MergedBits.grpDB
\r
6529 /*** CANTXDSR5 - MSCAN Transmit Data Segment Register 5; 0x00000179 ***/
\r
6533 byte DB0 :1; /* Data Bit 0 */
\r
6534 byte DB1 :1; /* Data Bit 1 */
\r
6535 byte DB2 :1; /* Data Bit 2 */
\r
6536 byte DB3 :1; /* Data Bit 3 */
\r
6537 byte DB4 :1; /* Data Bit 4 */
\r
6538 byte DB5 :1; /* Data Bit 5 */
\r
6539 byte DB6 :1; /* Data Bit 6 */
\r
6540 byte DB7 :1; /* Data Bit 7 */
\r
6546 extern volatile CANTXDSR5STR _CANTXDSR5 @(REG_BASE + 0x00000179);
\r
6547 #define CANTXDSR5 _CANTXDSR5.Byte
\r
6548 #define CANTXDSR5_DB0 _CANTXDSR5.Bits.DB0
\r
6549 #define CANTXDSR5_DB1 _CANTXDSR5.Bits.DB1
\r
6550 #define CANTXDSR5_DB2 _CANTXDSR5.Bits.DB2
\r
6551 #define CANTXDSR5_DB3 _CANTXDSR5.Bits.DB3
\r
6552 #define CANTXDSR5_DB4 _CANTXDSR5.Bits.DB4
\r
6553 #define CANTXDSR5_DB5 _CANTXDSR5.Bits.DB5
\r
6554 #define CANTXDSR5_DB6 _CANTXDSR5.Bits.DB6
\r
6555 #define CANTXDSR5_DB7 _CANTXDSR5.Bits.DB7
\r
6556 #define CANTXDSR5_DB _CANTXDSR5.MergedBits.grpDB
\r
6559 /*** CANTXDSR6 - MSCAN Transmit Data Segment Register 6; 0x0000017A ***/
\r
6563 byte DB0 :1; /* Data Bit 0 */
\r
6564 byte DB1 :1; /* Data Bit 1 */
\r
6565 byte DB2 :1; /* Data Bit 2 */
\r
6566 byte DB3 :1; /* Data Bit 3 */
\r
6567 byte DB4 :1; /* Data Bit 4 */
\r
6568 byte DB5 :1; /* Data Bit 5 */
\r
6569 byte DB6 :1; /* Data Bit 6 */
\r
6570 byte DB7 :1; /* Data Bit 7 */
\r
6576 extern volatile CANTXDSR6STR _CANTXDSR6 @(REG_BASE + 0x0000017A);
\r
6577 #define CANTXDSR6 _CANTXDSR6.Byte
\r
6578 #define CANTXDSR6_DB0 _CANTXDSR6.Bits.DB0
\r
6579 #define CANTXDSR6_DB1 _CANTXDSR6.Bits.DB1
\r
6580 #define CANTXDSR6_DB2 _CANTXDSR6.Bits.DB2
\r
6581 #define CANTXDSR6_DB3 _CANTXDSR6.Bits.DB3
\r
6582 #define CANTXDSR6_DB4 _CANTXDSR6.Bits.DB4
\r
6583 #define CANTXDSR6_DB5 _CANTXDSR6.Bits.DB5
\r
6584 #define CANTXDSR6_DB6 _CANTXDSR6.Bits.DB6
\r
6585 #define CANTXDSR6_DB7 _CANTXDSR6.Bits.DB7
\r
6586 #define CANTXDSR6_DB _CANTXDSR6.MergedBits.grpDB
\r
6589 /*** CANTXDSR7 - MSCAN Transmit Data Segment Register 7; 0x0000017B ***/
\r
6593 byte DB0 :1; /* Data Bit 0 */
\r
6594 byte DB1 :1; /* Data Bit 1 */
\r
6595 byte DB2 :1; /* Data Bit 2 */
\r
6596 byte DB3 :1; /* Data Bit 3 */
\r
6597 byte DB4 :1; /* Data Bit 4 */
\r
6598 byte DB5 :1; /* Data Bit 5 */
\r
6599 byte DB6 :1; /* Data Bit 6 */
\r
6600 byte DB7 :1; /* Data Bit 7 */
\r
6606 extern volatile CANTXDSR7STR _CANTXDSR7 @(REG_BASE + 0x0000017B);
\r
6607 #define CANTXDSR7 _CANTXDSR7.Byte
\r
6608 #define CANTXDSR7_DB0 _CANTXDSR7.Bits.DB0
\r
6609 #define CANTXDSR7_DB1 _CANTXDSR7.Bits.DB1
\r
6610 #define CANTXDSR7_DB2 _CANTXDSR7.Bits.DB2
\r
6611 #define CANTXDSR7_DB3 _CANTXDSR7.Bits.DB3
\r
6612 #define CANTXDSR7_DB4 _CANTXDSR7.Bits.DB4
\r
6613 #define CANTXDSR7_DB5 _CANTXDSR7.Bits.DB5
\r
6614 #define CANTXDSR7_DB6 _CANTXDSR7.Bits.DB6
\r
6615 #define CANTXDSR7_DB7 _CANTXDSR7.Bits.DB7
\r
6616 #define CANTXDSR7_DB _CANTXDSR7.MergedBits.grpDB
\r
6619 /*** CANTXDLR - MSCAN Transmit Data Length Register; 0x0000017C ***/
\r
6623 byte DLC0 :1; /* Data Length Code Bit 0 */
\r
6624 byte DLC1 :1; /* Data Length Code Bit 1 */
\r
6625 byte DLC2 :1; /* Data Length Code Bit 2 */
\r
6626 byte DLC3 :1; /* Data Length Code Bit 3 */
\r
6640 extern volatile CANTXDLRSTR _CANTXDLR @(REG_BASE + 0x0000017C);
\r
6641 #define CANTXDLR _CANTXDLR.Byte
\r
6642 #define CANTXDLR_DLC0 _CANTXDLR.Bits.DLC0
\r
6643 #define CANTXDLR_DLC1 _CANTXDLR.Bits.DLC1
\r
6644 #define CANTXDLR_DLC2 _CANTXDLR.Bits.DLC2
\r
6645 #define CANTXDLR_DLC3 _CANTXDLR.Bits.DLC3
\r
6646 #define CANTXDLR_DLC _CANTXDLR.MergedBits.grpDLC
\r
6649 /*** CANTXTBPR - MSCAN Transmit Buffer Priority; 0x0000017F ***/
\r
6653 byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */
\r
6654 byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */
\r
6655 byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */
\r
6656 byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */
\r
6657 byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */
\r
6658 byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */
\r
6659 byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */
\r
6660 byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */
\r
6666 extern volatile CANTXTBPRSTR _CANTXTBPR @(REG_BASE + 0x0000017F);
\r
6667 #define CANTXTBPR _CANTXTBPR.Byte
\r
6668 #define CANTXTBPR_PRIO0 _CANTXTBPR.Bits.PRIO0
\r
6669 #define CANTXTBPR_PRIO1 _CANTXTBPR.Bits.PRIO1
\r
6670 #define CANTXTBPR_PRIO2 _CANTXTBPR.Bits.PRIO2
\r
6671 #define CANTXTBPR_PRIO3 _CANTXTBPR.Bits.PRIO3
\r
6672 #define CANTXTBPR_PRIO4 _CANTXTBPR.Bits.PRIO4
\r
6673 #define CANTXTBPR_PRIO5 _CANTXTBPR.Bits.PRIO5
\r
6674 #define CANTXTBPR_PRIO6 _CANTXTBPR.Bits.PRIO6
\r
6675 #define CANTXTBPR_PRIO7 _CANTXTBPR.Bits.PRIO7
\r
6676 #define CANTXTBPR_PRIO _CANTXTBPR.MergedBits.grpPRIO
\r
6679 /*** PTT - Port T I/O Register; 0x00000240 ***/
\r
6683 byte PTT0 :1; /* Port T Bit 0 */
\r
6684 byte PTT1 :1; /* Port T Bit 1 */
\r
6685 byte PTT2 :1; /* Port T Bit 2 */
\r
6686 byte PTT3 :1; /* Port T Bit 3 */
\r
6687 byte PTT4 :1; /* Port T Bit 4 */
\r
6688 byte PTT5 :1; /* Port T Bit 5 */
\r
6689 byte PTT6 :1; /* Port T Bit 6 */
\r
6690 byte PTT7 :1; /* Port T Bit 7 */
\r
6696 extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240);
\r
6697 #define PTT _PTT.Byte
\r
6698 #define PTT_PTT0 _PTT.Bits.PTT0
\r
6699 #define PTT_PTT1 _PTT.Bits.PTT1
\r
6700 #define PTT_PTT2 _PTT.Bits.PTT2
\r
6701 #define PTT_PTT3 _PTT.Bits.PTT3
\r
6702 #define PTT_PTT4 _PTT.Bits.PTT4
\r
6703 #define PTT_PTT5 _PTT.Bits.PTT5
\r
6704 #define PTT_PTT6 _PTT.Bits.PTT6
\r
6705 #define PTT_PTT7 _PTT.Bits.PTT7
\r
6706 #define PTT_PTT _PTT.MergedBits.grpPTT
\r
6709 /*** PTIT - Port T Input; 0x00000241 ***/
\r
6713 byte PTIT0 :1; /* Port T Bit 0 */
\r
6714 byte PTIT1 :1; /* Port T Bit 1 */
\r
6715 byte PTIT2 :1; /* Port T Bit 2 */
\r
6716 byte PTIT3 :1; /* Port T Bit 3 */
\r
6717 byte PTIT4 :1; /* Port T Bit 4 */
\r
6718 byte PTIT5 :1; /* Port T Bit 5 */
\r
6719 byte PTIT6 :1; /* Port T Bit 6 */
\r
6720 byte PTIT7 :1; /* Port T Bit 7 */
\r
6726 extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241);
\r
6727 #define PTIT _PTIT.Byte
\r
6728 #define PTIT_PTIT0 _PTIT.Bits.PTIT0
\r
6729 #define PTIT_PTIT1 _PTIT.Bits.PTIT1
\r
6730 #define PTIT_PTIT2 _PTIT.Bits.PTIT2
\r
6731 #define PTIT_PTIT3 _PTIT.Bits.PTIT3
\r
6732 #define PTIT_PTIT4 _PTIT.Bits.PTIT4
\r
6733 #define PTIT_PTIT5 _PTIT.Bits.PTIT5
\r
6734 #define PTIT_PTIT6 _PTIT.Bits.PTIT6
\r
6735 #define PTIT_PTIT7 _PTIT.Bits.PTIT7
\r
6736 #define PTIT_PTIT _PTIT.MergedBits.grpPTIT
\r
6739 /*** DDRT - Port T Data Direction Register; 0x00000242 ***/
\r
6743 byte DDRT0 :1; /* Data Direction Port T Bit 0 */
\r
6744 byte DDRT1 :1; /* Data Direction Port T Bit 1 */
\r
6745 byte DDRT2 :1; /* Data Direction Port T Bit 2 */
\r
6746 byte DDRT3 :1; /* Data Direction Port T Bit 3 */
\r
6747 byte DDRT4 :1; /* Data Direction Port T Bit 4 */
\r
6748 byte DDRT5 :1; /* Data Direction Port T Bit 5 */
\r
6749 byte DDRT6 :1; /* Data Direction Port T Bit 6 */
\r
6750 byte DDRT7 :1; /* Data Direction Port T Bit 7 */
\r
6756 extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242);
\r
6757 #define DDRT _DDRT.Byte
\r
6758 #define DDRT_DDRT0 _DDRT.Bits.DDRT0
\r
6759 #define DDRT_DDRT1 _DDRT.Bits.DDRT1
\r
6760 #define DDRT_DDRT2 _DDRT.Bits.DDRT2
\r
6761 #define DDRT_DDRT3 _DDRT.Bits.DDRT3
\r
6762 #define DDRT_DDRT4 _DDRT.Bits.DDRT4
\r
6763 #define DDRT_DDRT5 _DDRT.Bits.DDRT5
\r
6764 #define DDRT_DDRT6 _DDRT.Bits.DDRT6
\r
6765 #define DDRT_DDRT7 _DDRT.Bits.DDRT7
\r
6766 #define DDRT_DDRT _DDRT.MergedBits.grpDDRT
\r
6769 /*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/
\r
6773 byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */
\r
6774 byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */
\r
6775 byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */
\r
6776 byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */
\r
6777 byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */
\r
6778 byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */
\r
6779 byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */
\r
6780 byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */
\r
6786 extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243);
\r
6787 #define RDRT _RDRT.Byte
\r
6788 #define RDRT_RDRT0 _RDRT.Bits.RDRT0
\r
6789 #define RDRT_RDRT1 _RDRT.Bits.RDRT1
\r
6790 #define RDRT_RDRT2 _RDRT.Bits.RDRT2
\r
6791 #define RDRT_RDRT3 _RDRT.Bits.RDRT3
\r
6792 #define RDRT_RDRT4 _RDRT.Bits.RDRT4
\r
6793 #define RDRT_RDRT5 _RDRT.Bits.RDRT5
\r
6794 #define RDRT_RDRT6 _RDRT.Bits.RDRT6
\r
6795 #define RDRT_RDRT7 _RDRT.Bits.RDRT7
\r
6796 #define RDRT_RDRT _RDRT.MergedBits.grpRDRT
\r
6799 /*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/
\r
6803 byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */
\r
6804 byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */
\r
6805 byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */
\r
6806 byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */
\r
6807 byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */
\r
6808 byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */
\r
6809 byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */
\r
6810 byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */
\r
6816 extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244);
\r
6817 #define PERT _PERT.Byte
\r
6818 #define PERT_PERT0 _PERT.Bits.PERT0
\r
6819 #define PERT_PERT1 _PERT.Bits.PERT1
\r
6820 #define PERT_PERT2 _PERT.Bits.PERT2
\r
6821 #define PERT_PERT3 _PERT.Bits.PERT3
\r
6822 #define PERT_PERT4 _PERT.Bits.PERT4
\r
6823 #define PERT_PERT5 _PERT.Bits.PERT5
\r
6824 #define PERT_PERT6 _PERT.Bits.PERT6
\r
6825 #define PERT_PERT7 _PERT.Bits.PERT7
\r
6826 #define PERT_PERT _PERT.MergedBits.grpPERT
\r
6829 /*** PPST - Port T Polarity Select Register; 0x00000245 ***/
\r
6833 byte PPST0 :1; /* Pull Select Port T Bit 0 */
\r
6834 byte PPST1 :1; /* Pull Select Port T Bit 1 */
\r
6835 byte PPST2 :1; /* Pull Select Port T Bit 2 */
\r
6836 byte PPST3 :1; /* Pull Select Port T Bit 3 */
\r
6837 byte PPST4 :1; /* Pull Select Port T Bit 4 */
\r
6838 byte PPST5 :1; /* Pull Select Port T Bit 5 */
\r
6839 byte PPST6 :1; /* Pull Select Port T Bit 6 */
\r
6840 byte PPST7 :1; /* Pull Select Port T Bit 7 */
\r
6846 extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245);
\r
6847 #define PPST _PPST.Byte
\r
6848 #define PPST_PPST0 _PPST.Bits.PPST0
\r
6849 #define PPST_PPST1 _PPST.Bits.PPST1
\r
6850 #define PPST_PPST2 _PPST.Bits.PPST2
\r
6851 #define PPST_PPST3 _PPST.Bits.PPST3
\r
6852 #define PPST_PPST4 _PPST.Bits.PPST4
\r
6853 #define PPST_PPST5 _PPST.Bits.PPST5
\r
6854 #define PPST_PPST6 _PPST.Bits.PPST6
\r
6855 #define PPST_PPST7 _PPST.Bits.PPST7
\r
6856 #define PPST_PPST _PPST.MergedBits.grpPPST
\r
6859 /*** MODRR - Module Routing Register; 0x00000247 ***/
\r
6863 byte MODRR0 :1; /* Module Routing Bit 0 */
\r
6864 byte MODRR1 :1; /* Module Routing Bit 1 */
\r
6865 byte MODRR2 :1; /* Module Routing Bit 2 */
\r
6866 byte MODRR3 :1; /* Module Routing Bit 3 */
\r
6867 byte MODRR4 :1; /* Module Routing Bit 4 */
\r
6879 extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000247);
\r
6880 #define MODRR _MODRR.Byte
\r
6881 #define MODRR_MODRR0 _MODRR.Bits.MODRR0
\r
6882 #define MODRR_MODRR1 _MODRR.Bits.MODRR1
\r
6883 #define MODRR_MODRR2 _MODRR.Bits.MODRR2
\r
6884 #define MODRR_MODRR3 _MODRR.Bits.MODRR3
\r
6885 #define MODRR_MODRR4 _MODRR.Bits.MODRR4
\r
6886 #define MODRR_MODRR _MODRR.MergedBits.grpMODRR
\r
6889 /*** PTS - Port S I/O Register; 0x00000248 ***/
\r
6893 byte PTS0 :1; /* Port S Bit 0 */
\r
6894 byte PTS1 :1; /* Port S Bit 1 */
\r
6895 byte PTS2 :1; /* Port S Bit 2 */
\r
6896 byte PTS3 :1; /* Port S Bit 3 */
\r
6910 extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248);
\r
6911 #define PTS _PTS.Byte
\r
6912 #define PTS_PTS0 _PTS.Bits.PTS0
\r
6913 #define PTS_PTS1 _PTS.Bits.PTS1
\r
6914 #define PTS_PTS2 _PTS.Bits.PTS2
\r
6915 #define PTS_PTS3 _PTS.Bits.PTS3
\r
6916 #define PTS_PTS _PTS.MergedBits.grpPTS
\r
6919 /*** PTIS - Port S Input; 0x00000249 ***/
\r
6923 byte PTIS0 :1; /* Port S Bit 0 */
\r
6924 byte PTIS1 :1; /* Port S Bit 1 */
\r
6925 byte PTIS2 :1; /* Port S Bit 2 */
\r
6926 byte PTIS3 :1; /* Port S Bit 3 */
\r
6940 extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249);
\r
6941 #define PTIS _PTIS.Byte
\r
6942 #define PTIS_PTIS0 _PTIS.Bits.PTIS0
\r
6943 #define PTIS_PTIS1 _PTIS.Bits.PTIS1
\r
6944 #define PTIS_PTIS2 _PTIS.Bits.PTIS2
\r
6945 #define PTIS_PTIS3 _PTIS.Bits.PTIS3
\r
6946 #define PTIS_PTIS _PTIS.MergedBits.grpPTIS
\r
6949 /*** DDRS - Port S Data Direction Register; 0x0000024A ***/
\r
6953 byte DDRS0 :1; /* Data Direction Port S Bit 0 */
\r
6954 byte DDRS1 :1; /* Data Direction Port S Bit 1 */
\r
6955 byte DDRS2 :1; /* Data Direction Port S Bit 2 */
\r
6956 byte DDRS3 :1; /* Data Direction Port S Bit 3 */
\r
6970 extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024A);
\r
6971 #define DDRS _DDRS.Byte
\r
6972 #define DDRS_DDRS0 _DDRS.Bits.DDRS0
\r
6973 #define DDRS_DDRS1 _DDRS.Bits.DDRS1
\r
6974 #define DDRS_DDRS2 _DDRS.Bits.DDRS2
\r
6975 #define DDRS_DDRS3 _DDRS.Bits.DDRS3
\r
6976 #define DDRS_DDRS _DDRS.MergedBits.grpDDRS
\r
6979 /*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/
\r
6983 byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */
\r
6984 byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */
\r
6985 byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */
\r
6986 byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */
\r
7000 extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024B);
\r
7001 #define RDRS _RDRS.Byte
\r
7002 #define RDRS_RDRS0 _RDRS.Bits.RDRS0
\r
7003 #define RDRS_RDRS1 _RDRS.Bits.RDRS1
\r
7004 #define RDRS_RDRS2 _RDRS.Bits.RDRS2
\r
7005 #define RDRS_RDRS3 _RDRS.Bits.RDRS3
\r
7006 #define RDRS_RDRS _RDRS.MergedBits.grpRDRS
\r
7009 /*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/
\r
7013 byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */
\r
7014 byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */
\r
7015 byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */
\r
7016 byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */
\r
7030 extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024C);
\r
7031 #define PERS _PERS.Byte
\r
7032 #define PERS_PERS0 _PERS.Bits.PERS0
\r
7033 #define PERS_PERS1 _PERS.Bits.PERS1
\r
7034 #define PERS_PERS2 _PERS.Bits.PERS2
\r
7035 #define PERS_PERS3 _PERS.Bits.PERS3
\r
7036 #define PERS_PERS _PERS.MergedBits.grpPERS
\r
7039 /*** PPSS - Port S Polarity Select Register; 0x0000024D ***/
\r
7043 byte PPSS0 :1; /* Pull Select Port S Bit 0 */
\r
7044 byte PPSS1 :1; /* Pull Select Port S Bit 1 */
\r
7045 byte PPSS2 :1; /* Pull Select Port S Bit 2 */
\r
7046 byte PPSS3 :1; /* Pull Select Port S Bit 3 */
\r
7060 extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024D);
\r
7061 #define PPSS _PPSS.Byte
\r
7062 #define PPSS_PPSS0 _PPSS.Bits.PPSS0
\r
7063 #define PPSS_PPSS1 _PPSS.Bits.PPSS1
\r
7064 #define PPSS_PPSS2 _PPSS.Bits.PPSS2
\r
7065 #define PPSS_PPSS3 _PPSS.Bits.PPSS3
\r
7066 #define PPSS_PPSS _PPSS.MergedBits.grpPPSS
\r
7069 /*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/
\r
7073 byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */
\r
7074 byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */
\r
7075 byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */
\r
7076 byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */
\r
7090 extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024E);
\r
7091 #define WOMS _WOMS.Byte
\r
7092 #define WOMS_WOMS0 _WOMS.Bits.WOMS0
\r
7093 #define WOMS_WOMS1 _WOMS.Bits.WOMS1
\r
7094 #define WOMS_WOMS2 _WOMS.Bits.WOMS2
\r
7095 #define WOMS_WOMS3 _WOMS.Bits.WOMS3
\r
7096 #define WOMS_WOMS _WOMS.MergedBits.grpWOMS
\r
7099 /*** PTM - Port M I/O Register; 0x00000250 ***/
\r
7103 byte PTM0 :1; /* Port T Bit 0 */
\r
7104 byte PTM1 :1; /* Port T Bit 1 */
\r
7105 byte PTM2 :1; /* Port T Bit 2 */
\r
7106 byte PTM3 :1; /* Port T Bit 3 */
\r
7107 byte PTM4 :1; /* Port T Bit 4 */
\r
7108 byte PTM5 :1; /* Port T Bit 5 */
\r
7118 extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250);
\r
7119 #define PTM _PTM.Byte
\r
7120 #define PTM_PTM0 _PTM.Bits.PTM0
\r
7121 #define PTM_PTM1 _PTM.Bits.PTM1
\r
7122 #define PTM_PTM2 _PTM.Bits.PTM2
\r
7123 #define PTM_PTM3 _PTM.Bits.PTM3
\r
7124 #define PTM_PTM4 _PTM.Bits.PTM4
\r
7125 #define PTM_PTM5 _PTM.Bits.PTM5
\r
7126 #define PTM_PTM _PTM.MergedBits.grpPTM
\r
7129 /*** PTIM - Port M Input; 0x00000251 ***/
\r
7133 byte PTIM0 :1; /* Port M Bit 0 */
\r
7134 byte PTIM1 :1; /* Port M Bit 1 */
\r
7135 byte PTIM2 :1; /* Port M Bit 2 */
\r
7136 byte PTIM3 :1; /* Port M Bit 3 */
\r
7137 byte PTIM4 :1; /* Port M Bit 4 */
\r
7138 byte PTIM5 :1; /* Port M Bit 5 */
\r
7148 extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251);
\r
7149 #define PTIM _PTIM.Byte
\r
7150 #define PTIM_PTIM0 _PTIM.Bits.PTIM0
\r
7151 #define PTIM_PTIM1 _PTIM.Bits.PTIM1
\r
7152 #define PTIM_PTIM2 _PTIM.Bits.PTIM2
\r
7153 #define PTIM_PTIM3 _PTIM.Bits.PTIM3
\r
7154 #define PTIM_PTIM4 _PTIM.Bits.PTIM4
\r
7155 #define PTIM_PTIM5 _PTIM.Bits.PTIM5
\r
7156 #define PTIM_PTIM _PTIM.MergedBits.grpPTIM
\r
7159 /*** DDRM - Port M Data Direction Register; 0x00000252 ***/
\r
7163 byte DDRM0 :1; /* Data Direction Port M Bit 0 */
\r
7164 byte DDRM1 :1; /* Data Direction Port M Bit 1 */
\r
7165 byte DDRM2 :1; /* Data Direction Port M Bit 2 */
\r
7166 byte DDRM3 :1; /* Data Direction Port M Bit 3 */
\r
7167 byte DDRM4 :1; /* Data Direction Port M Bit 4 */
\r
7168 byte DDRM5 :1; /* Data Direction Port M Bit 5 */
\r
7178 extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252);
\r
7179 #define DDRM _DDRM.Byte
\r
7180 #define DDRM_DDRM0 _DDRM.Bits.DDRM0
\r
7181 #define DDRM_DDRM1 _DDRM.Bits.DDRM1
\r
7182 #define DDRM_DDRM2 _DDRM.Bits.DDRM2
\r
7183 #define DDRM_DDRM3 _DDRM.Bits.DDRM3
\r
7184 #define DDRM_DDRM4 _DDRM.Bits.DDRM4
\r
7185 #define DDRM_DDRM5 _DDRM.Bits.DDRM5
\r
7186 #define DDRM_DDRM _DDRM.MergedBits.grpDDRM
\r
7189 /*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/
\r
7193 byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */
\r
7194 byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */
\r
7195 byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */
\r
7196 byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */
\r
7197 byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */
\r
7198 byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */
\r
7208 extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253);
\r
7209 #define RDRM _RDRM.Byte
\r
7210 #define RDRM_RDRM0 _RDRM.Bits.RDRM0
\r
7211 #define RDRM_RDRM1 _RDRM.Bits.RDRM1
\r
7212 #define RDRM_RDRM2 _RDRM.Bits.RDRM2
\r
7213 #define RDRM_RDRM3 _RDRM.Bits.RDRM3
\r
7214 #define RDRM_RDRM4 _RDRM.Bits.RDRM4
\r
7215 #define RDRM_RDRM5 _RDRM.Bits.RDRM5
\r
7216 #define RDRM_RDRM _RDRM.MergedBits.grpRDRM
\r
7219 /*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/
\r
7223 byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */
\r
7224 byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */
\r
7225 byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */
\r
7226 byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */
\r
7227 byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */
\r
7228 byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */
\r
7238 extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254);
\r
7239 #define PERM _PERM.Byte
\r
7240 #define PERM_PERM0 _PERM.Bits.PERM0
\r
7241 #define PERM_PERM1 _PERM.Bits.PERM1
\r
7242 #define PERM_PERM2 _PERM.Bits.PERM2
\r
7243 #define PERM_PERM3 _PERM.Bits.PERM3
\r
7244 #define PERM_PERM4 _PERM.Bits.PERM4
\r
7245 #define PERM_PERM5 _PERM.Bits.PERM5
\r
7246 #define PERM_PERM _PERM.MergedBits.grpPERM
\r
7249 /*** PPSM - Port M Polarity Select Register; 0x00000255 ***/
\r
7253 byte PPSM0 :1; /* Pull Select Port M Bit 0 */
\r
7254 byte PPSM1 :1; /* Pull Select Port M Bit 1 */
\r
7255 byte PPSM2 :1; /* Pull Select Port M Bit 2 */
\r
7256 byte PPSM3 :1; /* Pull Select Port M Bit 3 */
\r
7257 byte PPSM4 :1; /* Pull Select Port M Bit 4 */
\r
7258 byte PPSM5 :1; /* Pull Select Port M Bit 5 */
\r
7268 extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255);
\r
7269 #define PPSM _PPSM.Byte
\r
7270 #define PPSM_PPSM0 _PPSM.Bits.PPSM0
\r
7271 #define PPSM_PPSM1 _PPSM.Bits.PPSM1
\r
7272 #define PPSM_PPSM2 _PPSM.Bits.PPSM2
\r
7273 #define PPSM_PPSM3 _PPSM.Bits.PPSM3
\r
7274 #define PPSM_PPSM4 _PPSM.Bits.PPSM4
\r
7275 #define PPSM_PPSM5 _PPSM.Bits.PPSM5
\r
7276 #define PPSM_PPSM _PPSM.MergedBits.grpPPSM
\r
7279 /*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/
\r
7283 byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */
\r
7284 byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */
\r
7285 byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */
\r
7286 byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */
\r
7287 byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */
\r
7288 byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */
\r
7298 extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256);
\r
7299 #define WOMM _WOMM.Byte
\r
7300 #define WOMM_WOMM0 _WOMM.Bits.WOMM0
\r
7301 #define WOMM_WOMM1 _WOMM.Bits.WOMM1
\r
7302 #define WOMM_WOMM2 _WOMM.Bits.WOMM2
\r
7303 #define WOMM_WOMM3 _WOMM.Bits.WOMM3
\r
7304 #define WOMM_WOMM4 _WOMM.Bits.WOMM4
\r
7305 #define WOMM_WOMM5 _WOMM.Bits.WOMM5
\r
7306 #define WOMM_WOMM _WOMM.MergedBits.grpWOMM
\r
7309 /*** PTP - Port P I/O Register; 0x00000258 ***/
\r
7313 byte PTP0 :1; /* Port P Bit 0 */
\r
7314 byte PTP1 :1; /* Port P Bit 1 */
\r
7315 byte PTP2 :1; /* Port P Bit 2 */
\r
7316 byte PTP3 :1; /* Port P Bit 3 */
\r
7317 byte PTP4 :1; /* Port P Bit 4 */
\r
7318 byte PTP5 :1; /* Port P Bit 5 */
\r
7319 byte PTP6 :1; /* Port P Bit 6 */
\r
7320 byte PTP7 :1; /* Port P Bit 7 */
\r
7326 extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258);
\r
7327 #define PTP _PTP.Byte
\r
7328 #define PTP_PTP0 _PTP.Bits.PTP0
\r
7329 #define PTP_PTP1 _PTP.Bits.PTP1
\r
7330 #define PTP_PTP2 _PTP.Bits.PTP2
\r
7331 #define PTP_PTP3 _PTP.Bits.PTP3
\r
7332 #define PTP_PTP4 _PTP.Bits.PTP4
\r
7333 #define PTP_PTP5 _PTP.Bits.PTP5
\r
7334 #define PTP_PTP6 _PTP.Bits.PTP6
\r
7335 #define PTP_PTP7 _PTP.Bits.PTP7
\r
7336 #define PTP_PTP _PTP.MergedBits.grpPTP
\r
7339 /*** PTIP - Port P Input; 0x00000259 ***/
\r
7343 byte PTIP0 :1; /* Port P Bit 0 */
\r
7344 byte PTIP1 :1; /* Port P Bit 1 */
\r
7345 byte PTIP2 :1; /* Port P Bit 2 */
\r
7346 byte PTIP3 :1; /* Port P Bit 3 */
\r
7347 byte PTIP4 :1; /* Port P Bit 4 */
\r
7348 byte PTIP5 :1; /* Port P Bit 5 */
\r
7349 byte PTIP6 :1; /* Port P Bit 6 */
\r
7350 byte PTIP7 :1; /* Port P Bit 7 */
\r
7356 extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259);
\r
7357 #define PTIP _PTIP.Byte
\r
7358 #define PTIP_PTIP0 _PTIP.Bits.PTIP0
\r
7359 #define PTIP_PTIP1 _PTIP.Bits.PTIP1
\r
7360 #define PTIP_PTIP2 _PTIP.Bits.PTIP2
\r
7361 #define PTIP_PTIP3 _PTIP.Bits.PTIP3
\r
7362 #define PTIP_PTIP4 _PTIP.Bits.PTIP4
\r
7363 #define PTIP_PTIP5 _PTIP.Bits.PTIP5
\r
7364 #define PTIP_PTIP6 _PTIP.Bits.PTIP6
\r
7365 #define PTIP_PTIP7 _PTIP.Bits.PTIP7
\r
7366 #define PTIP_PTIP _PTIP.MergedBits.grpPTIP
\r
7369 /*** DDRP - Port P Data Direction Register; 0x0000025A ***/
\r
7373 byte DDRP0 :1; /* Data Direction Port P Bit 0 */
\r
7374 byte DDRP1 :1; /* Data Direction Port P Bit 1 */
\r
7375 byte DDRP2 :1; /* Data Direction Port P Bit 2 */
\r
7376 byte DDRP3 :1; /* Data Direction Port P Bit 3 */
\r
7377 byte DDRP4 :1; /* Data Direction Port P Bit 4 */
\r
7378 byte DDRP5 :1; /* Data Direction Port P Bit 5 */
\r
7379 byte DDRP6 :1; /* Data Direction Port P Bit 6 */
\r
7380 byte DDRP7 :1; /* Data Direction Port P Bit 7 */
\r
7386 extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025A);
\r
7387 #define DDRP _DDRP.Byte
\r
7388 #define DDRP_DDRP0 _DDRP.Bits.DDRP0
\r
7389 #define DDRP_DDRP1 _DDRP.Bits.DDRP1
\r
7390 #define DDRP_DDRP2 _DDRP.Bits.DDRP2
\r
7391 #define DDRP_DDRP3 _DDRP.Bits.DDRP3
\r
7392 #define DDRP_DDRP4 _DDRP.Bits.DDRP4
\r
7393 #define DDRP_DDRP5 _DDRP.Bits.DDRP5
\r
7394 #define DDRP_DDRP6 _DDRP.Bits.DDRP6
\r
7395 #define DDRP_DDRP7 _DDRP.Bits.DDRP7
\r
7396 #define DDRP_DDRP _DDRP.MergedBits.grpDDRP
\r
7399 /*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/
\r
7403 byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */
\r
7404 byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */
\r
7405 byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */
\r
7406 byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */
\r
7407 byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */
\r
7408 byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */
\r
7409 byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */
\r
7410 byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */
\r
7416 extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025B);
\r
7417 #define RDRP _RDRP.Byte
\r
7418 #define RDRP_RDRP0 _RDRP.Bits.RDRP0
\r
7419 #define RDRP_RDRP1 _RDRP.Bits.RDRP1
\r
7420 #define RDRP_RDRP2 _RDRP.Bits.RDRP2
\r
7421 #define RDRP_RDRP3 _RDRP.Bits.RDRP3
\r
7422 #define RDRP_RDRP4 _RDRP.Bits.RDRP4
\r
7423 #define RDRP_RDRP5 _RDRP.Bits.RDRP5
\r
7424 #define RDRP_RDRP6 _RDRP.Bits.RDRP6
\r
7425 #define RDRP_RDRP7 _RDRP.Bits.RDRP7
\r
7426 #define RDRP_RDRP _RDRP.MergedBits.grpRDRP
\r
7429 /*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/
\r
7433 byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */
\r
7434 byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */
\r
7435 byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */
\r
7436 byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */
\r
7437 byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */
\r
7438 byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */
\r
7439 byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */
\r
7440 byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */
\r
7446 extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025C);
\r
7447 #define PERP _PERP.Byte
\r
7448 #define PERP_PERP0 _PERP.Bits.PERP0
\r
7449 #define PERP_PERP1 _PERP.Bits.PERP1
\r
7450 #define PERP_PERP2 _PERP.Bits.PERP2
\r
7451 #define PERP_PERP3 _PERP.Bits.PERP3
\r
7452 #define PERP_PERP4 _PERP.Bits.PERP4
\r
7453 #define PERP_PERP5 _PERP.Bits.PERP5
\r
7454 #define PERP_PERP6 _PERP.Bits.PERP6
\r
7455 #define PERP_PERP7 _PERP.Bits.PERP7
\r
7456 #define PERP_PERP _PERP.MergedBits.grpPERP
\r
7459 /*** PPSP - Port P Polarity Select Register; 0x0000025D ***/
\r
7463 byte PPSP0 :1; /* Pull Select Port P Bit 0 */
\r
7464 byte PPSP1 :1; /* Pull Select Port P Bit 1 */
\r
7465 byte PPSP2 :1; /* Pull Select Port P Bit 2 */
\r
7466 byte PPSP3 :1; /* Pull Select Port P Bit 3 */
\r
7467 byte PPSP4 :1; /* Pull Select Port P Bit 4 */
\r
7468 byte PPSP5 :1; /* Pull Select Port P Bit 5 */
\r
7469 byte PPSP6 :1; /* Pull Select Port P Bit 6 */
\r
7470 byte PPSP7 :1; /* Pull Select Port P Bit 7 */
\r
7476 extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025D);
\r
7477 #define PPSP _PPSP.Byte
\r
7478 #define PPSP_PPSP0 _PPSP.Bits.PPSP0
\r
7479 #define PPSP_PPSP1 _PPSP.Bits.PPSP1
\r
7480 #define PPSP_PPSP2 _PPSP.Bits.PPSP2
\r
7481 #define PPSP_PPSP3 _PPSP.Bits.PPSP3
\r
7482 #define PPSP_PPSP4 _PPSP.Bits.PPSP4
\r
7483 #define PPSP_PPSP5 _PPSP.Bits.PPSP5
\r
7484 #define PPSP_PPSP6 _PPSP.Bits.PPSP6
\r
7485 #define PPSP_PPSP7 _PPSP.Bits.PPSP7
\r
7486 #define PPSP_PPSP _PPSP.MergedBits.grpPPSP
\r
7489 /*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/
\r
7493 byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */
\r
7494 byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */
\r
7495 byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */
\r
7496 byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */
\r
7497 byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */
\r
7498 byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */
\r
7499 byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */
\r
7500 byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */
\r
7506 extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025E);
\r
7507 #define PIEP _PIEP.Byte
\r
7508 #define PIEP_PIEP0 _PIEP.Bits.PIEP0
\r
7509 #define PIEP_PIEP1 _PIEP.Bits.PIEP1
\r
7510 #define PIEP_PIEP2 _PIEP.Bits.PIEP2
\r
7511 #define PIEP_PIEP3 _PIEP.Bits.PIEP3
\r
7512 #define PIEP_PIEP4 _PIEP.Bits.PIEP4
\r
7513 #define PIEP_PIEP5 _PIEP.Bits.PIEP5
\r
7514 #define PIEP_PIEP6 _PIEP.Bits.PIEP6
\r
7515 #define PIEP_PIEP7 _PIEP.Bits.PIEP7
\r
7516 #define PIEP_PIEP _PIEP.MergedBits.grpPIEP
\r
7519 /*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/
\r
7523 byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */
\r
7524 byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */
\r
7525 byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */
\r
7526 byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */
\r
7527 byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */
\r
7528 byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */
\r
7529 byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */
\r
7530 byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */
\r
7536 extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025F);
\r
7537 #define PIFP _PIFP.Byte
\r
7538 #define PIFP_PIFP0 _PIFP.Bits.PIFP0
\r
7539 #define PIFP_PIFP1 _PIFP.Bits.PIFP1
\r
7540 #define PIFP_PIFP2 _PIFP.Bits.PIFP2
\r
7541 #define PIFP_PIFP3 _PIFP.Bits.PIFP3
\r
7542 #define PIFP_PIFP4 _PIFP.Bits.PIFP4
\r
7543 #define PIFP_PIFP5 _PIFP.Bits.PIFP5
\r
7544 #define PIFP_PIFP6 _PIFP.Bits.PIFP6
\r
7545 #define PIFP_PIFP7 _PIFP.Bits.PIFP7
\r
7546 #define PIFP_PIFP _PIFP.MergedBits.grpPIFP
\r
7549 /*** PTJ - Port J I/O Register; 0x00000268 ***/
\r
7559 byte PTJ6 :1; /* Port J Bit 6 */
\r
7560 byte PTJ7 :1; /* Port J Bit 7 */
\r
7572 extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268);
\r
7573 #define PTJ _PTJ.Byte
\r
7574 #define PTJ_PTJ6 _PTJ.Bits.PTJ6
\r
7575 #define PTJ_PTJ7 _PTJ.Bits.PTJ7
\r
7576 #define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6
\r
7579 /*** PTIJ - Port J Input Register; 0x00000269 ***/
\r
7589 byte PTIJ6 :1; /* Port J Bit 6 */
\r
7590 byte PTIJ7 :1; /* Port J Bit 7 */
\r
7599 byte grpPTIJ_6 :2;
\r
7602 extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269);
\r
7603 #define PTIJ _PTIJ.Byte
\r
7604 #define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6
\r
7605 #define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7
\r
7606 #define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6
\r
7609 /*** DDRJ - Port J Data Direction Register; 0x0000026A ***/
\r
7619 byte DDRJ6 :1; /* Data Direction Port J Bit 6 */
\r
7620 byte DDRJ7 :1; /* Data Direction Port J Bit 7 */
\r
7629 byte grpDDRJ_6 :2;
\r
7632 extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026A);
\r
7633 #define DDRJ _DDRJ.Byte
\r
7634 #define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6
\r
7635 #define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7
\r
7636 #define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6
\r
7639 /*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/
\r
7649 byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */
\r
7650 byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */
\r
7659 byte grpRDRJ_6 :2;
\r
7662 extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026B);
\r
7663 #define RDRJ _RDRJ.Byte
\r
7664 #define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6
\r
7665 #define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7
\r
7666 #define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6
\r
7669 /*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/
\r
7679 byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */
\r
7680 byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */
\r
7689 byte grpPERJ_6 :2;
\r
7692 extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026C);
\r
7693 #define PERJ _PERJ.Byte
\r
7694 #define PERJ_PERJ6 _PERJ.Bits.PERJ6
\r
7695 #define PERJ_PERJ7 _PERJ.Bits.PERJ7
\r
7696 #define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6
\r
7699 /*** PPSJ - PortJP Polarity Select Register; 0x0000026D ***/
\r
7709 byte PPSJ6 :1; /* Pull Select Port J Bit 6 */
\r
7710 byte PPSJ7 :1; /* Pull Select Port J Bit 7 */
\r
7719 byte grpPPSJ_6 :2;
\r
7722 extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026D);
\r
7723 #define PPSJ _PPSJ.Byte
\r
7724 #define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6
\r
7725 #define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7
\r
7726 #define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6
\r
7729 /*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/
\r
7739 byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */
\r
7740 byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */
\r
7749 byte grpPIEJ_6 :2;
\r
7752 extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026E);
\r
7753 #define PIEJ _PIEJ.Byte
\r
7754 #define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6
\r
7755 #define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7
\r
7756 #define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6
\r
7759 /*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/
\r
7769 byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */
\r
7770 byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */
\r
7779 byte grpPIFJ_6 :2;
\r
7782 extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026F);
\r
7783 #define PIFJ _PIFJ.Byte
\r
7784 #define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6
\r
7785 #define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7
\r
7786 #define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6
\r
7789 /*** PTAD - Port AD I/O Register; 0x00000270 ***/
\r
7793 byte PTAD0 :1; /* Port AD Bit 0 */
\r
7794 byte PTAD1 :1; /* Port AD Bit 1 */
\r
7795 byte PTAD2 :1; /* Port AD Bit 2 */
\r
7796 byte PTAD3 :1; /* Port AD Bit 3 */
\r
7797 byte PTAD4 :1; /* Port AD Bit 4 */
\r
7798 byte PTAD5 :1; /* Port AD Bit 5 */
\r
7799 byte PTAD6 :1; /* Port AD Bit 6 */
\r
7800 byte PTAD7 :1; /* Port AD Bit 7 */
\r
7806 extern volatile PTADSTR _PTAD @(REG_BASE + 0x00000270);
\r
7807 #define PTAD _PTAD.Byte
\r
7808 #define PTAD_PTAD0 _PTAD.Bits.PTAD0
\r
7809 #define PTAD_PTAD1 _PTAD.Bits.PTAD1
\r
7810 #define PTAD_PTAD2 _PTAD.Bits.PTAD2
\r
7811 #define PTAD_PTAD3 _PTAD.Bits.PTAD3
\r
7812 #define PTAD_PTAD4 _PTAD.Bits.PTAD4
\r
7813 #define PTAD_PTAD5 _PTAD.Bits.PTAD5
\r
7814 #define PTAD_PTAD6 _PTAD.Bits.PTAD6
\r
7815 #define PTAD_PTAD7 _PTAD.Bits.PTAD7
\r
7816 #define PTAD_PTAD _PTAD.MergedBits.grpPTAD
\r
7819 /*** PTIAD - Port AD Input Register; 0x00000271 ***/
\r
7823 byte PTIAD0 :1; /* Port AD Bit 0 */
\r
7824 byte PTIAD1 :1; /* Port AD Bit 1 */
\r
7825 byte PTIAD2 :1; /* Port AD Bit 2 */
\r
7826 byte PTIAD3 :1; /* Port AD Bit 3 */
\r
7827 byte PTIAD4 :1; /* Port AD Bit 4 */
\r
7828 byte PTIAD5 :1; /* Port AD Bit 5 */
\r
7829 byte PTIAD6 :1; /* Port AD Bit 6 */
\r
7830 byte PTIAD7 :1; /* Port AD Bit 7 */
\r
7836 extern volatile PTIADSTR _PTIAD @(REG_BASE + 0x00000271);
\r
7837 #define PTIAD _PTIAD.Byte
\r
7838 #define PTIAD_PTIAD0 _PTIAD.Bits.PTIAD0
\r
7839 #define PTIAD_PTIAD1 _PTIAD.Bits.PTIAD1
\r
7840 #define PTIAD_PTIAD2 _PTIAD.Bits.PTIAD2
\r
7841 #define PTIAD_PTIAD3 _PTIAD.Bits.PTIAD3
\r
7842 #define PTIAD_PTIAD4 _PTIAD.Bits.PTIAD4
\r
7843 #define PTIAD_PTIAD5 _PTIAD.Bits.PTIAD5
\r
7844 #define PTIAD_PTIAD6 _PTIAD.Bits.PTIAD6
\r
7845 #define PTIAD_PTIAD7 _PTIAD.Bits.PTIAD7
\r
7846 #define PTIAD_PTIAD _PTIAD.MergedBits.grpPTIAD
\r
7849 /*** DDRAD - Port AD Data Direction Register; 0x00000272 ***/
\r
7853 byte DDRAD0 :1; /* Port AD Data Direction Bit 0 */
\r
7854 byte DDRAD1 :1; /* Port AD Data Direction Bit 1 */
\r
7855 byte DDRAD2 :1; /* Port AD Data Direction Bit 2 */
\r
7856 byte DDRAD3 :1; /* Port AD Data Direction Bit 3 */
\r
7857 byte DDRAD4 :1; /* Port AD Data Direction Bit 4 */
\r
7858 byte DDRAD5 :1; /* Port AD Data Direction Bit 5 */
\r
7859 byte DDRAD6 :1; /* Port AD Data Direction Bit 6 */
\r
7860 byte DDRAD7 :1; /* Port AD Data Direction Bit 7 */
\r
7866 extern volatile DDRADSTR _DDRAD @(REG_BASE + 0x00000272);
\r
7867 #define DDRAD _DDRAD.Byte
\r
7868 #define DDRAD_DDRAD0 _DDRAD.Bits.DDRAD0
\r
7869 #define DDRAD_DDRAD1 _DDRAD.Bits.DDRAD1
\r
7870 #define DDRAD_DDRAD2 _DDRAD.Bits.DDRAD2
\r
7871 #define DDRAD_DDRAD3 _DDRAD.Bits.DDRAD3
\r
7872 #define DDRAD_DDRAD4 _DDRAD.Bits.DDRAD4
\r
7873 #define DDRAD_DDRAD5 _DDRAD.Bits.DDRAD5
\r
7874 #define DDRAD_DDRAD6 _DDRAD.Bits.DDRAD6
\r
7875 #define DDRAD_DDRAD7 _DDRAD.Bits.DDRAD7
\r
7876 #define DDRAD_DDRAD _DDRAD.MergedBits.grpDDRAD
\r
7879 /*** RDRAD - Port AD Reduced Drive Register; 0x00000273 ***/
\r
7883 byte RDRAD0 :1; /* Port AD Reduced Drive Bit 0 */
\r
7884 byte RDRAD1 :1; /* Port AD Reduced Drive Bit 1 */
\r
7885 byte RDRAD2 :1; /* Port AD Reduced Drive Bit 2 */
\r
7886 byte RDRAD3 :1; /* Port AD Reduced Drive Bit 3 */
\r
7887 byte RDRAD4 :1; /* Port AD Reduced Drive Bit 4 */
\r
7888 byte RDRAD5 :1; /* Port AD Reduced Drive Bit 5 */
\r
7889 byte RDRAD6 :1; /* Port AD Reduced Drive Bit 6 */
\r
7890 byte RDRAD7 :1; /* Port AD Reduced Drive Bit 7 */
\r
7896 extern volatile RDRADSTR _RDRAD @(REG_BASE + 0x00000273);
\r
7897 #define RDRAD _RDRAD.Byte
\r
7898 #define RDRAD_RDRAD0 _RDRAD.Bits.RDRAD0
\r
7899 #define RDRAD_RDRAD1 _RDRAD.Bits.RDRAD1
\r
7900 #define RDRAD_RDRAD2 _RDRAD.Bits.RDRAD2
\r
7901 #define RDRAD_RDRAD3 _RDRAD.Bits.RDRAD3
\r
7902 #define RDRAD_RDRAD4 _RDRAD.Bits.RDRAD4
\r
7903 #define RDRAD_RDRAD5 _RDRAD.Bits.RDRAD5
\r
7904 #define RDRAD_RDRAD6 _RDRAD.Bits.RDRAD6
\r
7905 #define RDRAD_RDRAD7 _RDRAD.Bits.RDRAD7
\r
7906 #define RDRAD_RDRAD _RDRAD.MergedBits.grpRDRAD
\r
7909 /*** PERAD - Port AD Pull Device Enable Register; 0x00000274 ***/
\r
7913 byte PERAD0 :1; /* Port AD Pull Device Enable Bit 0 */
\r
7914 byte PERAD1 :1; /* Port AD Pull Device Enable Bit 1 */
\r
7915 byte PERAD2 :1; /* Port AD Pull Device Enable Bit 2 */
\r
7916 byte PERAD3 :1; /* Port AD Pull Device Enable Bit 3 */
\r
7917 byte PERAD4 :1; /* Port AD Pull Device Enable Bit 4 */
\r
7918 byte PERAD5 :1; /* Port AD Pull Device Enable Bit 5 */
\r
7919 byte PERAD6 :1; /* Port AD Pull Device Enable Bit 6 */
\r
7920 byte PERAD7 :1; /* Port AD Pull Device Enable Bit 7 */
\r
7926 extern volatile PERADSTR _PERAD @(REG_BASE + 0x00000274);
\r
7927 #define PERAD _PERAD.Byte
\r
7928 #define PERAD_PERAD0 _PERAD.Bits.PERAD0
\r
7929 #define PERAD_PERAD1 _PERAD.Bits.PERAD1
\r
7930 #define PERAD_PERAD2 _PERAD.Bits.PERAD2
\r
7931 #define PERAD_PERAD3 _PERAD.Bits.PERAD3
\r
7932 #define PERAD_PERAD4 _PERAD.Bits.PERAD4
\r
7933 #define PERAD_PERAD5 _PERAD.Bits.PERAD5
\r
7934 #define PERAD_PERAD6 _PERAD.Bits.PERAD6
\r
7935 #define PERAD_PERAD7 _PERAD.Bits.PERAD7
\r
7936 #define PERAD_PERAD _PERAD.MergedBits.grpPERAD
\r
7939 /*** PPSAD - Port AD Polarity Select Register; 0x00000275 ***/
\r
7943 byte PPSAD0 :1; /* Port AD Polarity Select Bit 0 */
\r
7944 byte PPSAD1 :1; /* Port AD Polarity Select Bit 1 */
\r
7945 byte PPSAD2 :1; /* Port AD Polarity Select Bit 2 */
\r
7946 byte PPSAD3 :1; /* Port AD Polarity Select Bit 3 */
\r
7947 byte PPSAD4 :1; /* Port AD Polarity Select Bit 4 */
\r
7948 byte PPSAD5 :1; /* Port AD Polarity Select Bit 5 */
\r
7949 byte PPSAD6 :1; /* Port AD Polarity Select Bit 6 */
\r
7950 byte PPSAD7 :1; /* Port AD Polarity Select Bit 7 */
\r
7956 extern volatile PPSADSTR _PPSAD @(REG_BASE + 0x00000275);
\r
7957 #define PPSAD _PPSAD.Byte
\r
7958 #define PPSAD_PPSAD0 _PPSAD.Bits.PPSAD0
\r
7959 #define PPSAD_PPSAD1 _PPSAD.Bits.PPSAD1
\r
7960 #define PPSAD_PPSAD2 _PPSAD.Bits.PPSAD2
\r
7961 #define PPSAD_PPSAD3 _PPSAD.Bits.PPSAD3
\r
7962 #define PPSAD_PPSAD4 _PPSAD.Bits.PPSAD4
\r
7963 #define PPSAD_PPSAD5 _PPSAD.Bits.PPSAD5
\r
7964 #define PPSAD_PPSAD6 _PPSAD.Bits.PPSAD6
\r
7965 #define PPSAD_PPSAD7 _PPSAD.Bits.PPSAD7
\r
7966 #define PPSAD_PPSAD _PPSAD.MergedBits.grpPPSAD
\r
7969 /*** BDMSTS - BDM Status Register; 0x0000FF01 ***/
\r
7974 byte UNSEC :1; /* Unsecure */
\r
7975 byte CLKSW :1; /* Clock switch */
\r
7976 byte TRACE :1; /* TRACE1 BDM firmware command is being executed */
\r
7977 byte SDV :1; /* Shift data valid */
\r
7978 byte ENTAG :1; /* Tagging enable */
\r
7979 byte BDMACT :1; /* BDM active status */
\r
7980 byte ENBDM :1; /* Enable BDM */
\r
7983 extern volatile BDMSTSSTR _BDMSTS @(0x0000FF01);
\r
7984 #define BDMSTS _BDMSTS.Byte
\r
7985 #define BDMSTS_UNSEC _BDMSTS.Bits.UNSEC
\r
7986 #define BDMSTS_CLKSW _BDMSTS.Bits.CLKSW
\r
7987 #define BDMSTS_TRACE _BDMSTS.Bits.TRACE
\r
7988 #define BDMSTS_SDV _BDMSTS.Bits.SDV
\r
7989 #define BDMSTS_ENTAG _BDMSTS.Bits.ENTAG
\r
7990 #define BDMSTS_BDMACT _BDMSTS.Bits.BDMACT
\r
7991 #define BDMSTS_ENBDM _BDMSTS.Bits.ENBDM
\r
7994 /*** BDMCCR - BDM CCR Holding Register; 0x0000FF06 ***/
\r
7998 byte CCR0 :1; /* BDM CCR Holding Bit 0 */
\r
7999 byte CCR1 :1; /* BDM CCR Holding Bit 1 */
\r
8000 byte CCR2 :1; /* BDM CCR Holding Bit 2 */
\r
8001 byte CCR3 :1; /* BDM CCR Holding Bit 3 */
\r
8002 byte CCR4 :1; /* BDM CCR Holding Bit 4 */
\r
8003 byte CCR5 :1; /* BDM CCR Holding Bit 5 */
\r
8004 byte CCR6 :1; /* BDM CCR Holding Bit 6 */
\r
8005 byte CCR7 :1; /* BDM CCR Holding Bit 7 */
\r
8011 extern volatile BDMCCRSTR _BDMCCR @(0x0000FF06);
\r
8012 #define BDMCCR _BDMCCR.Byte
\r
8013 #define BDMCCR_CCR0 _BDMCCR.Bits.CCR0
\r
8014 #define BDMCCR_CCR1 _BDMCCR.Bits.CCR1
\r
8015 #define BDMCCR_CCR2 _BDMCCR.Bits.CCR2
\r
8016 #define BDMCCR_CCR3 _BDMCCR.Bits.CCR3
\r
8017 #define BDMCCR_CCR4 _BDMCCR.Bits.CCR4
\r
8018 #define BDMCCR_CCR5 _BDMCCR.Bits.CCR5
\r
8019 #define BDMCCR_CCR6 _BDMCCR.Bits.CCR6
\r
8020 #define BDMCCR_CCR7 _BDMCCR.Bits.CCR7
\r
8021 #define BDMCCR_CCR _BDMCCR.MergedBits.grpCCR
\r
8024 /*** BDMINR - BDM Internal Register Position Register; 0x0000FF07 ***/
\r
8031 byte REG11 :1; /* Internal register map position */
\r
8032 byte REG12 :1; /* Internal register map position */
\r
8033 byte REG13 :1; /* Internal register map position */
\r
8034 byte REG14 :1; /* Internal register map position */
\r
8035 byte REG15 :1; /* Internal register map position */
\r
8041 byte grpREG_11 :5;
\r
8044 extern volatile BDMINRSTR _BDMINR @(0x0000FF07);
\r
8045 #define BDMINR _BDMINR.Byte
\r
8046 #define BDMINR_REG11 _BDMINR.Bits.REG11
\r
8047 #define BDMINR_REG12 _BDMINR.Bits.REG12
\r
8048 #define BDMINR_REG13 _BDMINR.Bits.REG13
\r
8049 #define BDMINR_REG14 _BDMINR.Bits.REG14
\r
8050 #define BDMINR_REG15 _BDMINR.Bits.REG15
\r
8051 #define BDMINR_REG_11 _BDMINR.MergedBits.grpREG_11
\r
8052 #define BDMINR_REG BDMINR_REG_11
\r
8055 /* Watchdog reset macro */
\r
8057 #define __RESET_WATCHDOG() /* empty */
\r
8059 #define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */
\r
8065 ** ###################################################################
\r
8067 ** This file was created by UNIS Processor Expert 03.33 for
\r
8068 ** the Motorola HCS12 series of microcontrollers.
\r
8070 ** ###################################################################
\r