2 * These files are taken from the MCF523X source code example package
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3 * which is available on the Freescale website. Freescale explicitly
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4 * grants the redistribution and modification of these source files.
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5 * The complete licensing information is available in the file
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6 * LICENSE_FREESCALE.TXT.
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8 * File: mcf523x_etpu.h
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9 * Purpose: Register and bit definitions for the MCF523X
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15 #ifndef __MCF523X_ETPU_H__
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16 #define __MCF523X_ETPU_H__
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18 /*********************************************************************
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20 * enhanced Time Processor Unit (ETPU)
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22 *********************************************************************/
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24 /* Register read/write macros */
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25 #define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000]))
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26 #define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004]))
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27 #define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C]))
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28 #define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010]))
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29 #define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014]))
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30 #define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020]))
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31 #define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024]))
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32 #define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028]))
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33 #define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C]))
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34 #define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200]))
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35 #define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210]))
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36 #define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220]))
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37 #define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230]))
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38 #define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240]))
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39 #define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250]))
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40 #define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280]))
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41 #define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290]))
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42 #define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404]))
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43 #define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414]))
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44 #define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424]))
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45 #define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434]))
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46 #define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444]))
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47 #define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454]))
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48 #define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464]))
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49 #define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474]))
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50 #define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484]))
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51 #define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494]))
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52 #define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4]))
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53 #define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4]))
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54 #define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4]))
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55 #define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4]))
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56 #define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4]))
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57 #define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4]))
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58 #define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504]))
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59 #define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514]))
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60 #define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524]))
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61 #define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534]))
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62 #define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544]))
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63 #define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554]))
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64 #define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564]))
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65 #define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574]))
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66 #define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584]))
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67 #define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594]))
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68 #define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4]))
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69 #define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4]))
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70 #define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4]))
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71 #define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4]))
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72 #define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4]))
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73 #define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4]))
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74 #define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)]))
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75 #define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400]))
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76 #define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410]))
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77 #define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420]))
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78 #define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430]))
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79 #define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440]))
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80 #define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450]))
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81 #define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460]))
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82 #define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470]))
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83 #define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480]))
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84 #define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490]))
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85 #define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0]))
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86 #define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0]))
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87 #define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0]))
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88 #define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0]))
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89 #define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0]))
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90 #define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0]))
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91 #define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500]))
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92 #define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510]))
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93 #define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520]))
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94 #define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530]))
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95 #define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540]))
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96 #define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550]))
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97 #define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560]))
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98 #define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570]))
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99 #define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580]))
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100 #define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590]))
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101 #define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0]))
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102 #define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0]))
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103 #define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0]))
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104 #define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0]))
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105 #define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0]))
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106 #define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0]))
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107 #define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)]))
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108 #define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408]))
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109 #define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418]))
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110 #define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428]))
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111 #define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438]))
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112 #define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448]))
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113 #define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458]))
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114 #define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468]))
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115 #define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478]))
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116 #define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488]))
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117 #define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498]))
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118 #define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8]))
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119 #define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8]))
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120 #define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8]))
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121 #define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8]))
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122 #define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8]))
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123 #define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8]))
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124 #define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508]))
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125 #define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518]))
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126 #define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528]))
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127 #define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538]))
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128 #define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548]))
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129 #define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558]))
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130 #define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568]))
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131 #define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578]))
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132 #define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588]))
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133 #define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598]))
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134 #define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8]))
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135 #define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8]))
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136 #define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8]))
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137 #define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8]))
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138 #define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8]))
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139 #define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8]))
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140 #define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)]))
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142 /* Bit definitions and macros for MCF_ETPU_EMCR */
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143 #define MCF_ETPU_EMCR_GTBE (0x00000001)
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144 #define MCF_ETPU_EMCR_VIS (0x00000040)
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145 #define MCF_ETPU_EMCR_SCMMISEN (0x00000200)
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146 #define MCF_ETPU_EMCR_SCMMISF (0x00000400)
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147 #define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16)
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148 #define MCF_ETPU_EMCR_ILF2 (0x01000000)
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149 #define MCF_ETPU_EMCR_ILF1 (0x02000000)
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150 #define MCF_ETPU_EMCR_MGE2 (0x04000000)
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151 #define MCF_ETPU_EMCR_MGE1 (0x08000000)
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152 #define MCF_ETPU_EMCR_GEC (0x80000000)
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154 /* Bit definitions and macros for MCF_ETPU_ECDCR */
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155 #define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0)
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156 #define MCF_ETPU_ECDCR_WR (0x00000080)
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157 #define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8)
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158 #define MCF_ETPU_ECDCR_PWIDTH (0x00008000)
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159 #define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16)
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160 #define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26)
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161 #define MCF_ETPU_ECDCR_STS (0x80000000)
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163 /* Bit definitions and macros for MCF_ETPU_EECR */
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164 #define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0)
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165 #define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14)
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166 #define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16)
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167 #define MCF_ETPU_EECR_HLTF (0x00800000)
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168 #define MCF_ETPU_EECR_STF (0x10000000)
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169 #define MCF_ETPU_EECR_MDIS (0x40000000)
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170 #define MCF_ETPU_EECR_FEND (0x80000000)
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172 /* Bit definitions and macros for MCF_ETPU_ETBCR */
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173 #define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0)
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174 #define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14)
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175 #define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16)
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176 #define MCF_ETPU_ETBCR_AM (0x02000000)
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177 #define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27)
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178 #define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29)
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180 /* Bit definitions and macros for MCF_ETPU_ETB1R */
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181 #define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0)
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183 /* Bit definitions and macros for MCF_ETPU_ETB2R */
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184 #define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0)
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186 /* Bit definitions and macros for MCF_ETPU_EREDCR */
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187 #define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0)
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188 #define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8)
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189 #define MCF_ETPU_EREDCR_RSC2 (0x00004000)
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190 #define MCF_ETPU_EREDCR_REN2 (0x00008000)
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191 #define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16)
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192 #define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24)
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193 #define MCF_ETPU_EREDCR_RSC1 (0x40000000)
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194 #define MCF_ETPU_EREDCR_REN1 (0x80000000)
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196 /* Bit definitions and macros for MCF_ETPU_ECISR */
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197 #define MCF_ETPU_ECISR_CIS0 (0x00000001)
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198 #define MCF_ETPU_ECISR_CIS1 (0x00000002)
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199 #define MCF_ETPU_ECISR_CIS2 (0x00000004)
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200 #define MCF_ETPU_ECISR_CIS3 (0x00000008)
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201 #define MCF_ETPU_ECISR_CIS4 (0x00000010)
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202 #define MCF_ETPU_ECISR_CIS5 (0x00000020)
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203 #define MCF_ETPU_ECISR_CIS6 (0x00000040)
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204 #define MCF_ETPU_ECISR_CIS7 (0x00000080)
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205 #define MCF_ETPU_ECISR_CIS8 (0x00000100)
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206 #define MCF_ETPU_ECISR_CIS9 (0x00000200)
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207 #define MCF_ETPU_ECISR_CIS10 (0x00000400)
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208 #define MCF_ETPU_ECISR_CIS11 (0x00000800)
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209 #define MCF_ETPU_ECISR_CIS12 (0x00001000)
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210 #define MCF_ETPU_ECISR_CIS13 (0x00002000)
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211 #define MCF_ETPU_ECISR_CIS14 (0x00004000)
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212 #define MCF_ETPU_ECISR_CIS15 (0x00008000)
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213 #define MCF_ETPU_ECISR_CIS16 (0x00010000)
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214 #define MCF_ETPU_ECISR_CIS17 (0x00020000)
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215 #define MCF_ETPU_ECISR_CIS18 (0x00040000)
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216 #define MCF_ETPU_ECISR_CIS19 (0x00080000)
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217 #define MCF_ETPU_ECISR_CIS20 (0x00100000)
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218 #define MCF_ETPU_ECISR_CIS21 (0x00200000)
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219 #define MCF_ETPU_ECISR_CIS22 (0x00400000)
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220 #define MCF_ETPU_ECISR_CIS23 (0x00800000)
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221 #define MCF_ETPU_ECISR_CIS24 (0x01000000)
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222 #define MCF_ETPU_ECISR_CIS25 (0x02000000)
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223 #define MCF_ETPU_ECISR_CIS26 (0x04000000)
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224 #define MCF_ETPU_ECISR_CIS27 (0x08000000)
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225 #define MCF_ETPU_ECISR_CIS28 (0x10000000)
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226 #define MCF_ETPU_ECISR_CIS29 (0x20000000)
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227 #define MCF_ETPU_ECISR_CIS30 (0x40000000)
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228 #define MCF_ETPU_ECISR_CIS31 (0x80000000)
\r
230 /* Bit definitions and macros for MCF_ETPU_ECDTRSR */
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231 #define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001)
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232 #define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002)
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233 #define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004)
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234 #define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008)
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235 #define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010)
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236 #define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020)
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237 #define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040)
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238 #define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080)
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239 #define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100)
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240 #define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200)
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241 #define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400)
\r
242 #define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800)
\r
243 #define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000)
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244 #define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000)
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245 #define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000)
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246 #define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000)
\r
247 #define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000)
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248 #define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000)
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249 #define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000)
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250 #define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000)
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251 #define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000)
\r
252 #define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000)
\r
253 #define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000)
\r
254 #define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000)
\r
255 #define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000)
\r
256 #define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000)
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257 #define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000)
\r
258 #define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000)
\r
259 #define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000)
\r
260 #define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000)
\r
261 #define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000)
\r
262 #define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000)
\r
264 /* Bit definitions and macros for MCF_ETPU_ECIOSR */
\r
265 #define MCF_ETPU_ECIOSR_CIOS0 (0x00000001)
\r
266 #define MCF_ETPU_ECIOSR_CIOS1 (0x00000002)
\r
267 #define MCF_ETPU_ECIOSR_CIOS2 (0x00000004)
\r
268 #define MCF_ETPU_ECIOSR_CIOS3 (0x00000008)
\r
269 #define MCF_ETPU_ECIOSR_CIOS4 (0x00000010)
\r
270 #define MCF_ETPU_ECIOSR_CIOS5 (0x00000020)
\r
271 #define MCF_ETPU_ECIOSR_CIOS6 (0x00000040)
\r
272 #define MCF_ETPU_ECIOSR_CIOS7 (0x00000080)
\r
273 #define MCF_ETPU_ECIOSR_CIOS8 (0x00000100)
\r
274 #define MCF_ETPU_ECIOSR_CIOS9 (0x00000200)
\r
275 #define MCF_ETPU_ECIOSR_CIOS10 (0x00000400)
\r
276 #define MCF_ETPU_ECIOSR_CIOS11 (0x00000800)
\r
277 #define MCF_ETPU_ECIOSR_CIOS12 (0x00001000)
\r
278 #define MCF_ETPU_ECIOSR_CIOS13 (0x00002000)
\r
279 #define MCF_ETPU_ECIOSR_CIOS14 (0x00004000)
\r
280 #define MCF_ETPU_ECIOSR_CIOS15 (0x00008000)
\r
281 #define MCF_ETPU_ECIOSR_CIOS16 (0x00010000)
\r
282 #define MCF_ETPU_ECIOSR_CIOS17 (0x00020000)
\r
283 #define MCF_ETPU_ECIOSR_CIOS18 (0x00040000)
\r
284 #define MCF_ETPU_ECIOSR_CIOS19 (0x00080000)
\r
285 #define MCF_ETPU_ECIOSR_CIOS20 (0x00100000)
\r
286 #define MCF_ETPU_ECIOSR_CIOS21 (0x00200000)
\r
287 #define MCF_ETPU_ECIOSR_CIOS22 (0x00400000)
\r
288 #define MCF_ETPU_ECIOSR_CIOS23 (0x00800000)
\r
289 #define MCF_ETPU_ECIOSR_CIOS24 (0x01000000)
\r
290 #define MCF_ETPU_ECIOSR_CIOS25 (0x02000000)
\r
291 #define MCF_ETPU_ECIOSR_CIOS26 (0x04000000)
\r
292 #define MCF_ETPU_ECIOSR_CIOS27 (0x08000000)
\r
293 #define MCF_ETPU_ECIOSR_CIOS28 (0x10000000)
\r
294 #define MCF_ETPU_ECIOSR_CIOS29 (0x20000000)
\r
295 #define MCF_ETPU_ECIOSR_CIOS30 (0x40000000)
\r
296 #define MCF_ETPU_ECIOSR_CIOS31 (0x80000000)
\r
298 /* Bit definitions and macros for MCF_ETPU_ECDTROSR */
\r
299 #define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001)
\r
300 #define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002)
\r
301 #define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004)
\r
302 #define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008)
\r
303 #define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010)
\r
304 #define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020)
\r
305 #define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040)
\r
306 #define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080)
\r
307 #define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100)
\r
308 #define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200)
\r
309 #define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400)
\r
310 #define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800)
\r
311 #define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000)
\r
312 #define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000)
\r
313 #define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000)
\r
314 #define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000)
\r
315 #define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000)
\r
316 #define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000)
\r
317 #define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000)
\r
318 #define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000)
\r
319 #define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000)
\r
320 #define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000)
\r
321 #define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000)
\r
322 #define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000)
\r
323 #define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000)
\r
324 #define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000)
\r
325 #define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000)
\r
326 #define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000)
\r
327 #define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000)
\r
328 #define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000)
\r
329 #define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000)
\r
330 #define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000)
\r
332 /* Bit definitions and macros for MCF_ETPU_ECIER */
\r
333 #define MCF_ETPU_ECIER_CIE0 (0x00000001)
\r
334 #define MCF_ETPU_ECIER_CIE1 (0x00000002)
\r
335 #define MCF_ETPU_ECIER_CIE2 (0x00000004)
\r
336 #define MCF_ETPU_ECIER_CIE3 (0x00000008)
\r
337 #define MCF_ETPU_ECIER_CIE4 (0x00000010)
\r
338 #define MCF_ETPU_ECIER_CIE5 (0x00000020)
\r
339 #define MCF_ETPU_ECIER_CIE6 (0x00000040)
\r
340 #define MCF_ETPU_ECIER_CIE7 (0x00000080)
\r
341 #define MCF_ETPU_ECIER_CIE8 (0x00000100)
\r
342 #define MCF_ETPU_ECIER_CIE9 (0x00000200)
\r
343 #define MCF_ETPU_ECIER_CIE10 (0x00000400)
\r
344 #define MCF_ETPU_ECIER_CIE11 (0x00000800)
\r
345 #define MCF_ETPU_ECIER_CIE12 (0x00001000)
\r
346 #define MCF_ETPU_ECIER_CIE13 (0x00002000)
\r
347 #define MCF_ETPU_ECIER_CIE14 (0x00004000)
\r
348 #define MCF_ETPU_ECIER_CIE15 (0x00008000)
\r
349 #define MCF_ETPU_ECIER_CIE16 (0x00010000)
\r
350 #define MCF_ETPU_ECIER_CIE17 (0x00020000)
\r
351 #define MCF_ETPU_ECIER_CIE18 (0x00040000)
\r
352 #define MCF_ETPU_ECIER_CIE19 (0x00080000)
\r
353 #define MCF_ETPU_ECIER_CIE20 (0x00100000)
\r
354 #define MCF_ETPU_ECIER_CIE21 (0x00200000)
\r
355 #define MCF_ETPU_ECIER_CIE22 (0x00400000)
\r
356 #define MCF_ETPU_ECIER_CIE23 (0x00800000)
\r
357 #define MCF_ETPU_ECIER_CIE24 (0x01000000)
\r
358 #define MCF_ETPU_ECIER_CIE25 (0x02000000)
\r
359 #define MCF_ETPU_ECIER_CIE26 (0x04000000)
\r
360 #define MCF_ETPU_ECIER_CIE27 (0x08000000)
\r
361 #define MCF_ETPU_ECIER_CIE28 (0x10000000)
\r
362 #define MCF_ETPU_ECIER_CIE29 (0x20000000)
\r
363 #define MCF_ETPU_ECIER_CIE30 (0x40000000)
\r
364 #define MCF_ETPU_ECIER_CIE31 (0x80000000)
\r
366 /* Bit definitions and macros for MCF_ETPU_ECDTRER */
\r
367 #define MCF_ETPU_ECDTRER_DTRE0 (0x00000001)
\r
368 #define MCF_ETPU_ECDTRER_DTRE1 (0x00000002)
\r
369 #define MCF_ETPU_ECDTRER_DTRE2 (0x00000004)
\r
370 #define MCF_ETPU_ECDTRER_DTRE3 (0x00000008)
\r
371 #define MCF_ETPU_ECDTRER_DTRE4 (0x00000010)
\r
372 #define MCF_ETPU_ECDTRER_DTRE5 (0x00000020)
\r
373 #define MCF_ETPU_ECDTRER_DTRE6 (0x00000040)
\r
374 #define MCF_ETPU_ECDTRER_DTRE7 (0x00000080)
\r
375 #define MCF_ETPU_ECDTRER_DTRE8 (0x00000100)
\r
376 #define MCF_ETPU_ECDTRER_DTRE9 (0x00000200)
\r
377 #define MCF_ETPU_ECDTRER_DTRE10 (0x00000400)
\r
378 #define MCF_ETPU_ECDTRER_DTRE11 (0x00000800)
\r
379 #define MCF_ETPU_ECDTRER_DTRE12 (0x00001000)
\r
380 #define MCF_ETPU_ECDTRER_DTRE13 (0x00002000)
\r
381 #define MCF_ETPU_ECDTRER_DTRE14 (0x00004000)
\r
382 #define MCF_ETPU_ECDTRER_DTRE15 (0x00008000)
\r
383 #define MCF_ETPU_ECDTRER_DTRE16 (0x00010000)
\r
384 #define MCF_ETPU_ECDTRER_DTRE17 (0x00020000)
\r
385 #define MCF_ETPU_ECDTRER_DTRE18 (0x00040000)
\r
386 #define MCF_ETPU_ECDTRER_DTRE19 (0x00080000)
\r
387 #define MCF_ETPU_ECDTRER_DTRE20 (0x00100000)
\r
388 #define MCF_ETPU_ECDTRER_DTRE21 (0x00200000)
\r
389 #define MCF_ETPU_ECDTRER_DTRE22 (0x00400000)
\r
390 #define MCF_ETPU_ECDTRER_DTRE23 (0x00800000)
\r
391 #define MCF_ETPU_ECDTRER_DTRE24 (0x01000000)
\r
392 #define MCF_ETPU_ECDTRER_DTRE25 (0x02000000)
\r
393 #define MCF_ETPU_ECDTRER_DTRE26 (0x04000000)
\r
394 #define MCF_ETPU_ECDTRER_DTRE27 (0x08000000)
\r
395 #define MCF_ETPU_ECDTRER_DTRE28 (0x10000000)
\r
396 #define MCF_ETPU_ECDTRER_DTRE29 (0x20000000)
\r
397 #define MCF_ETPU_ECDTRER_DTRE30 (0x40000000)
\r
398 #define MCF_ETPU_ECDTRER_DTRE31 (0x80000000)
\r
400 /* Bit definitions and macros for MCF_ETPU_ECPSSR */
\r
401 #define MCF_ETPU_ECPSSR_SR0 (0x00000001)
\r
402 #define MCF_ETPU_ECPSSR_SR1 (0x00000002)
\r
403 #define MCF_ETPU_ECPSSR_SR2 (0x00000004)
\r
404 #define MCF_ETPU_ECPSSR_SR3 (0x00000008)
\r
405 #define MCF_ETPU_ECPSSR_SR4 (0x00000010)
\r
406 #define MCF_ETPU_ECPSSR_SR5 (0x00000020)
\r
407 #define MCF_ETPU_ECPSSR_SR6 (0x00000040)
\r
408 #define MCF_ETPU_ECPSSR_SR7 (0x00000080)
\r
409 #define MCF_ETPU_ECPSSR_SR8 (0x00000100)
\r
410 #define MCF_ETPU_ECPSSR_SR9 (0x00000200)
\r
411 #define MCF_ETPU_ECPSSR_SR10 (0x00000400)
\r
412 #define MCF_ETPU_ECPSSR_SR11 (0x00000800)
\r
413 #define MCF_ETPU_ECPSSR_SR12 (0x00001000)
\r
414 #define MCF_ETPU_ECPSSR_SR13 (0x00002000)
\r
415 #define MCF_ETPU_ECPSSR_SR14 (0x00004000)
\r
416 #define MCF_ETPU_ECPSSR_SR15 (0x00008000)
\r
417 #define MCF_ETPU_ECPSSR_SR16 (0x00010000)
\r
418 #define MCF_ETPU_ECPSSR_SR17 (0x00020000)
\r
419 #define MCF_ETPU_ECPSSR_SR18 (0x00040000)
\r
420 #define MCF_ETPU_ECPSSR_SR19 (0x00080000)
\r
421 #define MCF_ETPU_ECPSSR_SR20 (0x00100000)
\r
422 #define MCF_ETPU_ECPSSR_SR21 (0x00200000)
\r
423 #define MCF_ETPU_ECPSSR_SR22 (0x00400000)
\r
424 #define MCF_ETPU_ECPSSR_SR23 (0x00800000)
\r
425 #define MCF_ETPU_ECPSSR_SR24 (0x01000000)
\r
426 #define MCF_ETPU_ECPSSR_SR25 (0x02000000)
\r
427 #define MCF_ETPU_ECPSSR_SR26 (0x04000000)
\r
428 #define MCF_ETPU_ECPSSR_SR27 (0x08000000)
\r
429 #define MCF_ETPU_ECPSSR_SR28 (0x10000000)
\r
430 #define MCF_ETPU_ECPSSR_SR29 (0x20000000)
\r
431 #define MCF_ETPU_ECPSSR_SR30 (0x40000000)
\r
432 #define MCF_ETPU_ECPSSR_SR31 (0x80000000)
\r
434 /* Bit definitions and macros for MCF_ETPU_ECSSR */
\r
435 #define MCF_ETPU_ECSSR_SS0 (0x00000001)
\r
436 #define MCF_ETPU_ECSSR_SS1 (0x00000002)
\r
437 #define MCF_ETPU_ECSSR_SS2 (0x00000004)
\r
438 #define MCF_ETPU_ECSSR_SS3 (0x00000008)
\r
439 #define MCF_ETPU_ECSSR_SS4 (0x00000010)
\r
440 #define MCF_ETPU_ECSSR_SS5 (0x00000020)
\r
441 #define MCF_ETPU_ECSSR_SS6 (0x00000040)
\r
442 #define MCF_ETPU_ECSSR_SS7 (0x00000080)
\r
443 #define MCF_ETPU_ECSSR_SS8 (0x00000100)
\r
444 #define MCF_ETPU_ECSSR_SS9 (0x00000200)
\r
445 #define MCF_ETPU_ECSSR_SS10 (0x00000400)
\r
446 #define MCF_ETPU_ECSSR_SS11 (0x00000800)
\r
447 #define MCF_ETPU_ECSSR_SS12 (0x00001000)
\r
448 #define MCF_ETPU_ECSSR_SS13 (0x00002000)
\r
449 #define MCF_ETPU_ECSSR_SS14 (0x00004000)
\r
450 #define MCF_ETPU_ECSSR_SS15 (0x00008000)
\r
451 #define MCF_ETPU_ECSSR_SS16 (0x00010000)
\r
452 #define MCF_ETPU_ECSSR_SS17 (0x00020000)
\r
453 #define MCF_ETPU_ECSSR_SS18 (0x00040000)
\r
454 #define MCF_ETPU_ECSSR_SS19 (0x00080000)
\r
455 #define MCF_ETPU_ECSSR_SS20 (0x00100000)
\r
456 #define MCF_ETPU_ECSSR_SS21 (0x00200000)
\r
457 #define MCF_ETPU_ECSSR_SS22 (0x00400000)
\r
458 #define MCF_ETPU_ECSSR_SS23 (0x00800000)
\r
459 #define MCF_ETPU_ECSSR_SS24 (0x01000000)
\r
460 #define MCF_ETPU_ECSSR_SS25 (0x02000000)
\r
461 #define MCF_ETPU_ECSSR_SS26 (0x04000000)
\r
462 #define MCF_ETPU_ECSSR_SS27 (0x08000000)
\r
463 #define MCF_ETPU_ECSSR_SS28 (0x10000000)
\r
464 #define MCF_ETPU_ECSSR_SS29 (0x20000000)
\r
465 #define MCF_ETPU_ECSSR_SS30 (0x40000000)
\r
466 #define MCF_ETPU_ECSSR_SS31 (0x80000000)
\r
468 /* Bit definitions and macros for MCF_ETPU_ECnSCR */
\r
469 #define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0)
\r
470 #define MCF_ETPU_ECnSCR_OBE (0x00002000)
\r
471 #define MCF_ETPU_ECnSCR_OPS (0x00004000)
\r
472 #define MCF_ETPU_ECnSCR_IPS (0x00008000)
\r
473 #define MCF_ETPU_ECnSCR_DTROS (0x00400000)
\r
474 #define MCF_ETPU_ECnSCR_DTRS (0x00800000)
\r
475 #define MCF_ETPU_ECnSCR_CIOS (0x40000000)
\r
476 #define MCF_ETPU_ECnSCR_CIS (0x80000000)
\r
478 /* Bit definitions and macros for MCF_ETPU_ECnCR */
\r
479 #define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0)
\r
480 #define MCF_ETPU_ECnCR_OPOL (0x00004000)
\r
481 #define MCF_ETPU_ECnCR_ODIS (0x00008000)
\r
482 #define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16)
\r
483 #define MCF_ETPU_ECnCR_ETCS (0x01000000)
\r
484 #define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28)
\r
485 #define MCF_ETPU_ECnCR_DTRE (0x40000000)
\r
486 #define MCF_ETPU_ECnCR_CIE (0x80000000)
\r
488 /* Bit definitions and macros for MCF_ETPU_ECnHSSR */
\r
489 #define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0)
\r
491 /********************************************************************/
\r
493 #endif /* __MCF523X_ETPU_H__ */
\r
projects / freertos / blob