2 * These files are taken from the MCF523X source code example package
3 * which is available on the Freescale website. Freescale explicitly
4 * grants the redistribution and modification of these source files.
5 * The complete licensing information is available in the file
6 * LICENSE_FREESCALE.TXT.
9 * Purpose: Register and bit definitions for the MCF523X
15 #ifndef __MCF523X_ETPU_H__
16 #define __MCF523X_ETPU_H__
18 /*********************************************************************
20 * enhanced Time Processor Unit (ETPU)
22 *********************************************************************/
24 /* Register read/write macros */
25 #define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000]))
26 #define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004]))
27 #define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C]))
28 #define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010]))
29 #define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014]))
30 #define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020]))
31 #define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024]))
32 #define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028]))
33 #define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C]))
34 #define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200]))
35 #define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210]))
36 #define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220]))
37 #define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230]))
38 #define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240]))
39 #define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250]))
40 #define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280]))
41 #define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290]))
42 #define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404]))
43 #define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414]))
44 #define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424]))
45 #define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434]))
46 #define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444]))
47 #define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454]))
48 #define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464]))
49 #define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474]))
50 #define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484]))
51 #define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494]))
52 #define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4]))
53 #define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4]))
54 #define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4]))
55 #define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4]))
56 #define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4]))
57 #define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4]))
58 #define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504]))
59 #define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514]))
60 #define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524]))
61 #define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534]))
62 #define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544]))
63 #define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554]))
64 #define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564]))
65 #define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574]))
66 #define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584]))
67 #define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594]))
68 #define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4]))
69 #define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4]))
70 #define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4]))
71 #define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4]))
72 #define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4]))
73 #define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4]))
74 #define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)]))
75 #define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400]))
76 #define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410]))
77 #define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420]))
78 #define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430]))
79 #define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440]))
80 #define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450]))
81 #define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460]))
82 #define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470]))
83 #define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480]))
84 #define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490]))
85 #define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0]))
86 #define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0]))
87 #define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0]))
88 #define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0]))
89 #define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0]))
90 #define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0]))
91 #define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500]))
92 #define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510]))
93 #define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520]))
94 #define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530]))
95 #define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540]))
96 #define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550]))
97 #define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560]))
98 #define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570]))
99 #define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580]))
100 #define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590]))
101 #define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0]))
102 #define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0]))
103 #define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0]))
104 #define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0]))
105 #define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0]))
106 #define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0]))
107 #define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)]))
108 #define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408]))
109 #define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418]))
110 #define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428]))
111 #define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438]))
112 #define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448]))
113 #define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458]))
114 #define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468]))
115 #define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478]))
116 #define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488]))
117 #define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498]))
118 #define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8]))
119 #define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8]))
120 #define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8]))
121 #define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8]))
122 #define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8]))
123 #define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8]))
124 #define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508]))
125 #define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518]))
126 #define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528]))
127 #define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538]))
128 #define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548]))
129 #define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558]))
130 #define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568]))
131 #define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578]))
132 #define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588]))
133 #define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598]))
134 #define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8]))
135 #define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8]))
136 #define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8]))
137 #define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8]))
138 #define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8]))
139 #define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8]))
140 #define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)]))
142 /* Bit definitions and macros for MCF_ETPU_EMCR */
143 #define MCF_ETPU_EMCR_GTBE (0x00000001)
144 #define MCF_ETPU_EMCR_VIS (0x00000040)
145 #define MCF_ETPU_EMCR_SCMMISEN (0x00000200)
146 #define MCF_ETPU_EMCR_SCMMISF (0x00000400)
147 #define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16)
148 #define MCF_ETPU_EMCR_ILF2 (0x01000000)
149 #define MCF_ETPU_EMCR_ILF1 (0x02000000)
150 #define MCF_ETPU_EMCR_MGE2 (0x04000000)
151 #define MCF_ETPU_EMCR_MGE1 (0x08000000)
152 #define MCF_ETPU_EMCR_GEC (0x80000000)
154 /* Bit definitions and macros for MCF_ETPU_ECDCR */
155 #define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0)
156 #define MCF_ETPU_ECDCR_WR (0x00000080)
157 #define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8)
158 #define MCF_ETPU_ECDCR_PWIDTH (0x00008000)
159 #define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16)
160 #define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26)
161 #define MCF_ETPU_ECDCR_STS (0x80000000)
163 /* Bit definitions and macros for MCF_ETPU_EECR */
164 #define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0)
165 #define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14)
166 #define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16)
167 #define MCF_ETPU_EECR_HLTF (0x00800000)
168 #define MCF_ETPU_EECR_STF (0x10000000)
169 #define MCF_ETPU_EECR_MDIS (0x40000000)
170 #define MCF_ETPU_EECR_FEND (0x80000000)
172 /* Bit definitions and macros for MCF_ETPU_ETBCR */
173 #define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0)
174 #define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14)
175 #define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16)
176 #define MCF_ETPU_ETBCR_AM (0x02000000)
177 #define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27)
178 #define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29)
180 /* Bit definitions and macros for MCF_ETPU_ETB1R */
181 #define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0)
183 /* Bit definitions and macros for MCF_ETPU_ETB2R */
184 #define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0)
186 /* Bit definitions and macros for MCF_ETPU_EREDCR */
187 #define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0)
188 #define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8)
189 #define MCF_ETPU_EREDCR_RSC2 (0x00004000)
190 #define MCF_ETPU_EREDCR_REN2 (0x00008000)
191 #define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16)
192 #define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24)
193 #define MCF_ETPU_EREDCR_RSC1 (0x40000000)
194 #define MCF_ETPU_EREDCR_REN1 (0x80000000)
196 /* Bit definitions and macros for MCF_ETPU_ECISR */
197 #define MCF_ETPU_ECISR_CIS0 (0x00000001)
198 #define MCF_ETPU_ECISR_CIS1 (0x00000002)
199 #define MCF_ETPU_ECISR_CIS2 (0x00000004)
200 #define MCF_ETPU_ECISR_CIS3 (0x00000008)
201 #define MCF_ETPU_ECISR_CIS4 (0x00000010)
202 #define MCF_ETPU_ECISR_CIS5 (0x00000020)
203 #define MCF_ETPU_ECISR_CIS6 (0x00000040)
204 #define MCF_ETPU_ECISR_CIS7 (0x00000080)
205 #define MCF_ETPU_ECISR_CIS8 (0x00000100)
206 #define MCF_ETPU_ECISR_CIS9 (0x00000200)
207 #define MCF_ETPU_ECISR_CIS10 (0x00000400)
208 #define MCF_ETPU_ECISR_CIS11 (0x00000800)
209 #define MCF_ETPU_ECISR_CIS12 (0x00001000)
210 #define MCF_ETPU_ECISR_CIS13 (0x00002000)
211 #define MCF_ETPU_ECISR_CIS14 (0x00004000)
212 #define MCF_ETPU_ECISR_CIS15 (0x00008000)
213 #define MCF_ETPU_ECISR_CIS16 (0x00010000)
214 #define MCF_ETPU_ECISR_CIS17 (0x00020000)
215 #define MCF_ETPU_ECISR_CIS18 (0x00040000)
216 #define MCF_ETPU_ECISR_CIS19 (0x00080000)
217 #define MCF_ETPU_ECISR_CIS20 (0x00100000)
218 #define MCF_ETPU_ECISR_CIS21 (0x00200000)
219 #define MCF_ETPU_ECISR_CIS22 (0x00400000)
220 #define MCF_ETPU_ECISR_CIS23 (0x00800000)
221 #define MCF_ETPU_ECISR_CIS24 (0x01000000)
222 #define MCF_ETPU_ECISR_CIS25 (0x02000000)
223 #define MCF_ETPU_ECISR_CIS26 (0x04000000)
224 #define MCF_ETPU_ECISR_CIS27 (0x08000000)
225 #define MCF_ETPU_ECISR_CIS28 (0x10000000)
226 #define MCF_ETPU_ECISR_CIS29 (0x20000000)
227 #define MCF_ETPU_ECISR_CIS30 (0x40000000)
228 #define MCF_ETPU_ECISR_CIS31 (0x80000000)
230 /* Bit definitions and macros for MCF_ETPU_ECDTRSR */
231 #define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001)
232 #define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002)
233 #define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004)
234 #define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008)
235 #define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010)
236 #define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020)
237 #define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040)
238 #define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080)
239 #define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100)
240 #define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200)
241 #define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400)
242 #define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800)
243 #define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000)
244 #define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000)
245 #define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000)
246 #define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000)
247 #define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000)
248 #define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000)
249 #define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000)
250 #define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000)
251 #define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000)
252 #define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000)
253 #define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000)
254 #define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000)
255 #define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000)
256 #define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000)
257 #define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000)
258 #define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000)
259 #define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000)
260 #define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000)
261 #define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000)
262 #define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000)
264 /* Bit definitions and macros for MCF_ETPU_ECIOSR */
265 #define MCF_ETPU_ECIOSR_CIOS0 (0x00000001)
266 #define MCF_ETPU_ECIOSR_CIOS1 (0x00000002)
267 #define MCF_ETPU_ECIOSR_CIOS2 (0x00000004)
268 #define MCF_ETPU_ECIOSR_CIOS3 (0x00000008)
269 #define MCF_ETPU_ECIOSR_CIOS4 (0x00000010)
270 #define MCF_ETPU_ECIOSR_CIOS5 (0x00000020)
271 #define MCF_ETPU_ECIOSR_CIOS6 (0x00000040)
272 #define MCF_ETPU_ECIOSR_CIOS7 (0x00000080)
273 #define MCF_ETPU_ECIOSR_CIOS8 (0x00000100)
274 #define MCF_ETPU_ECIOSR_CIOS9 (0x00000200)
275 #define MCF_ETPU_ECIOSR_CIOS10 (0x00000400)
276 #define MCF_ETPU_ECIOSR_CIOS11 (0x00000800)
277 #define MCF_ETPU_ECIOSR_CIOS12 (0x00001000)
278 #define MCF_ETPU_ECIOSR_CIOS13 (0x00002000)
279 #define MCF_ETPU_ECIOSR_CIOS14 (0x00004000)
280 #define MCF_ETPU_ECIOSR_CIOS15 (0x00008000)
281 #define MCF_ETPU_ECIOSR_CIOS16 (0x00010000)
282 #define MCF_ETPU_ECIOSR_CIOS17 (0x00020000)
283 #define MCF_ETPU_ECIOSR_CIOS18 (0x00040000)
284 #define MCF_ETPU_ECIOSR_CIOS19 (0x00080000)
285 #define MCF_ETPU_ECIOSR_CIOS20 (0x00100000)
286 #define MCF_ETPU_ECIOSR_CIOS21 (0x00200000)
287 #define MCF_ETPU_ECIOSR_CIOS22 (0x00400000)
288 #define MCF_ETPU_ECIOSR_CIOS23 (0x00800000)
289 #define MCF_ETPU_ECIOSR_CIOS24 (0x01000000)
290 #define MCF_ETPU_ECIOSR_CIOS25 (0x02000000)
291 #define MCF_ETPU_ECIOSR_CIOS26 (0x04000000)
292 #define MCF_ETPU_ECIOSR_CIOS27 (0x08000000)
293 #define MCF_ETPU_ECIOSR_CIOS28 (0x10000000)
294 #define MCF_ETPU_ECIOSR_CIOS29 (0x20000000)
295 #define MCF_ETPU_ECIOSR_CIOS30 (0x40000000)
296 #define MCF_ETPU_ECIOSR_CIOS31 (0x80000000)
298 /* Bit definitions and macros for MCF_ETPU_ECDTROSR */
299 #define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001)
300 #define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002)
301 #define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004)
302 #define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008)
303 #define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010)
304 #define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020)
305 #define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040)
306 #define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080)
307 #define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100)
308 #define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200)
309 #define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400)
310 #define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800)
311 #define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000)
312 #define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000)
313 #define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000)
314 #define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000)
315 #define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000)
316 #define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000)
317 #define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000)
318 #define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000)
319 #define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000)
320 #define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000)
321 #define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000)
322 #define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000)
323 #define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000)
324 #define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000)
325 #define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000)
326 #define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000)
327 #define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000)
328 #define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000)
329 #define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000)
330 #define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000)
332 /* Bit definitions and macros for MCF_ETPU_ECIER */
333 #define MCF_ETPU_ECIER_CIE0 (0x00000001)
334 #define MCF_ETPU_ECIER_CIE1 (0x00000002)
335 #define MCF_ETPU_ECIER_CIE2 (0x00000004)
336 #define MCF_ETPU_ECIER_CIE3 (0x00000008)
337 #define MCF_ETPU_ECIER_CIE4 (0x00000010)
338 #define MCF_ETPU_ECIER_CIE5 (0x00000020)
339 #define MCF_ETPU_ECIER_CIE6 (0x00000040)
340 #define MCF_ETPU_ECIER_CIE7 (0x00000080)
341 #define MCF_ETPU_ECIER_CIE8 (0x00000100)
342 #define MCF_ETPU_ECIER_CIE9 (0x00000200)
343 #define MCF_ETPU_ECIER_CIE10 (0x00000400)
344 #define MCF_ETPU_ECIER_CIE11 (0x00000800)
345 #define MCF_ETPU_ECIER_CIE12 (0x00001000)
346 #define MCF_ETPU_ECIER_CIE13 (0x00002000)
347 #define MCF_ETPU_ECIER_CIE14 (0x00004000)
348 #define MCF_ETPU_ECIER_CIE15 (0x00008000)
349 #define MCF_ETPU_ECIER_CIE16 (0x00010000)
350 #define MCF_ETPU_ECIER_CIE17 (0x00020000)
351 #define MCF_ETPU_ECIER_CIE18 (0x00040000)
352 #define MCF_ETPU_ECIER_CIE19 (0x00080000)
353 #define MCF_ETPU_ECIER_CIE20 (0x00100000)
354 #define MCF_ETPU_ECIER_CIE21 (0x00200000)
355 #define MCF_ETPU_ECIER_CIE22 (0x00400000)
356 #define MCF_ETPU_ECIER_CIE23 (0x00800000)
357 #define MCF_ETPU_ECIER_CIE24 (0x01000000)
358 #define MCF_ETPU_ECIER_CIE25 (0x02000000)
359 #define MCF_ETPU_ECIER_CIE26 (0x04000000)
360 #define MCF_ETPU_ECIER_CIE27 (0x08000000)
361 #define MCF_ETPU_ECIER_CIE28 (0x10000000)
362 #define MCF_ETPU_ECIER_CIE29 (0x20000000)
363 #define MCF_ETPU_ECIER_CIE30 (0x40000000)
364 #define MCF_ETPU_ECIER_CIE31 (0x80000000)
366 /* Bit definitions and macros for MCF_ETPU_ECDTRER */
367 #define MCF_ETPU_ECDTRER_DTRE0 (0x00000001)
368 #define MCF_ETPU_ECDTRER_DTRE1 (0x00000002)
369 #define MCF_ETPU_ECDTRER_DTRE2 (0x00000004)
370 #define MCF_ETPU_ECDTRER_DTRE3 (0x00000008)
371 #define MCF_ETPU_ECDTRER_DTRE4 (0x00000010)
372 #define MCF_ETPU_ECDTRER_DTRE5 (0x00000020)
373 #define MCF_ETPU_ECDTRER_DTRE6 (0x00000040)
374 #define MCF_ETPU_ECDTRER_DTRE7 (0x00000080)
375 #define MCF_ETPU_ECDTRER_DTRE8 (0x00000100)
376 #define MCF_ETPU_ECDTRER_DTRE9 (0x00000200)
377 #define MCF_ETPU_ECDTRER_DTRE10 (0x00000400)
378 #define MCF_ETPU_ECDTRER_DTRE11 (0x00000800)
379 #define MCF_ETPU_ECDTRER_DTRE12 (0x00001000)
380 #define MCF_ETPU_ECDTRER_DTRE13 (0x00002000)
381 #define MCF_ETPU_ECDTRER_DTRE14 (0x00004000)
382 #define MCF_ETPU_ECDTRER_DTRE15 (0x00008000)
383 #define MCF_ETPU_ECDTRER_DTRE16 (0x00010000)
384 #define MCF_ETPU_ECDTRER_DTRE17 (0x00020000)
385 #define MCF_ETPU_ECDTRER_DTRE18 (0x00040000)
386 #define MCF_ETPU_ECDTRER_DTRE19 (0x00080000)
387 #define MCF_ETPU_ECDTRER_DTRE20 (0x00100000)
388 #define MCF_ETPU_ECDTRER_DTRE21 (0x00200000)
389 #define MCF_ETPU_ECDTRER_DTRE22 (0x00400000)
390 #define MCF_ETPU_ECDTRER_DTRE23 (0x00800000)
391 #define MCF_ETPU_ECDTRER_DTRE24 (0x01000000)
392 #define MCF_ETPU_ECDTRER_DTRE25 (0x02000000)
393 #define MCF_ETPU_ECDTRER_DTRE26 (0x04000000)
394 #define MCF_ETPU_ECDTRER_DTRE27 (0x08000000)
395 #define MCF_ETPU_ECDTRER_DTRE28 (0x10000000)
396 #define MCF_ETPU_ECDTRER_DTRE29 (0x20000000)
397 #define MCF_ETPU_ECDTRER_DTRE30 (0x40000000)
398 #define MCF_ETPU_ECDTRER_DTRE31 (0x80000000)
400 /* Bit definitions and macros for MCF_ETPU_ECPSSR */
401 #define MCF_ETPU_ECPSSR_SR0 (0x00000001)
402 #define MCF_ETPU_ECPSSR_SR1 (0x00000002)
403 #define MCF_ETPU_ECPSSR_SR2 (0x00000004)
404 #define MCF_ETPU_ECPSSR_SR3 (0x00000008)
405 #define MCF_ETPU_ECPSSR_SR4 (0x00000010)
406 #define MCF_ETPU_ECPSSR_SR5 (0x00000020)
407 #define MCF_ETPU_ECPSSR_SR6 (0x00000040)
408 #define MCF_ETPU_ECPSSR_SR7 (0x00000080)
409 #define MCF_ETPU_ECPSSR_SR8 (0x00000100)
410 #define MCF_ETPU_ECPSSR_SR9 (0x00000200)
411 #define MCF_ETPU_ECPSSR_SR10 (0x00000400)
412 #define MCF_ETPU_ECPSSR_SR11 (0x00000800)
413 #define MCF_ETPU_ECPSSR_SR12 (0x00001000)
414 #define MCF_ETPU_ECPSSR_SR13 (0x00002000)
415 #define MCF_ETPU_ECPSSR_SR14 (0x00004000)
416 #define MCF_ETPU_ECPSSR_SR15 (0x00008000)
417 #define MCF_ETPU_ECPSSR_SR16 (0x00010000)
418 #define MCF_ETPU_ECPSSR_SR17 (0x00020000)
419 #define MCF_ETPU_ECPSSR_SR18 (0x00040000)
420 #define MCF_ETPU_ECPSSR_SR19 (0x00080000)
421 #define MCF_ETPU_ECPSSR_SR20 (0x00100000)
422 #define MCF_ETPU_ECPSSR_SR21 (0x00200000)
423 #define MCF_ETPU_ECPSSR_SR22 (0x00400000)
424 #define MCF_ETPU_ECPSSR_SR23 (0x00800000)
425 #define MCF_ETPU_ECPSSR_SR24 (0x01000000)
426 #define MCF_ETPU_ECPSSR_SR25 (0x02000000)
427 #define MCF_ETPU_ECPSSR_SR26 (0x04000000)
428 #define MCF_ETPU_ECPSSR_SR27 (0x08000000)
429 #define MCF_ETPU_ECPSSR_SR28 (0x10000000)
430 #define MCF_ETPU_ECPSSR_SR29 (0x20000000)
431 #define MCF_ETPU_ECPSSR_SR30 (0x40000000)
432 #define MCF_ETPU_ECPSSR_SR31 (0x80000000)
434 /* Bit definitions and macros for MCF_ETPU_ECSSR */
435 #define MCF_ETPU_ECSSR_SS0 (0x00000001)
436 #define MCF_ETPU_ECSSR_SS1 (0x00000002)
437 #define MCF_ETPU_ECSSR_SS2 (0x00000004)
438 #define MCF_ETPU_ECSSR_SS3 (0x00000008)
439 #define MCF_ETPU_ECSSR_SS4 (0x00000010)
440 #define MCF_ETPU_ECSSR_SS5 (0x00000020)
441 #define MCF_ETPU_ECSSR_SS6 (0x00000040)
442 #define MCF_ETPU_ECSSR_SS7 (0x00000080)
443 #define MCF_ETPU_ECSSR_SS8 (0x00000100)
444 #define MCF_ETPU_ECSSR_SS9 (0x00000200)
445 #define MCF_ETPU_ECSSR_SS10 (0x00000400)
446 #define MCF_ETPU_ECSSR_SS11 (0x00000800)
447 #define MCF_ETPU_ECSSR_SS12 (0x00001000)
448 #define MCF_ETPU_ECSSR_SS13 (0x00002000)
449 #define MCF_ETPU_ECSSR_SS14 (0x00004000)
450 #define MCF_ETPU_ECSSR_SS15 (0x00008000)
451 #define MCF_ETPU_ECSSR_SS16 (0x00010000)
452 #define MCF_ETPU_ECSSR_SS17 (0x00020000)
453 #define MCF_ETPU_ECSSR_SS18 (0x00040000)
454 #define MCF_ETPU_ECSSR_SS19 (0x00080000)
455 #define MCF_ETPU_ECSSR_SS20 (0x00100000)
456 #define MCF_ETPU_ECSSR_SS21 (0x00200000)
457 #define MCF_ETPU_ECSSR_SS22 (0x00400000)
458 #define MCF_ETPU_ECSSR_SS23 (0x00800000)
459 #define MCF_ETPU_ECSSR_SS24 (0x01000000)
460 #define MCF_ETPU_ECSSR_SS25 (0x02000000)
461 #define MCF_ETPU_ECSSR_SS26 (0x04000000)
462 #define MCF_ETPU_ECSSR_SS27 (0x08000000)
463 #define MCF_ETPU_ECSSR_SS28 (0x10000000)
464 #define MCF_ETPU_ECSSR_SS29 (0x20000000)
465 #define MCF_ETPU_ECSSR_SS30 (0x40000000)
466 #define MCF_ETPU_ECSSR_SS31 (0x80000000)
468 /* Bit definitions and macros for MCF_ETPU_ECnSCR */
469 #define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0)
470 #define MCF_ETPU_ECnSCR_OBE (0x00002000)
471 #define MCF_ETPU_ECnSCR_OPS (0x00004000)
472 #define MCF_ETPU_ECnSCR_IPS (0x00008000)
473 #define MCF_ETPU_ECnSCR_DTROS (0x00400000)
474 #define MCF_ETPU_ECnSCR_DTRS (0x00800000)
475 #define MCF_ETPU_ECnSCR_CIOS (0x40000000)
476 #define MCF_ETPU_ECnSCR_CIS (0x80000000)
478 /* Bit definitions and macros for MCF_ETPU_ECnCR */
479 #define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0)
480 #define MCF_ETPU_ECnCR_OPOL (0x00004000)
481 #define MCF_ETPU_ECnCR_ODIS (0x00008000)
482 #define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16)
483 #define MCF_ETPU_ECnCR_ETCS (0x01000000)
484 #define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28)
485 #define MCF_ETPU_ECnCR_DTRE (0x40000000)
486 #define MCF_ETPU_ECnCR_CIE (0x80000000)
488 /* Bit definitions and macros for MCF_ETPU_ECnHSSR */
489 #define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0)
491 /********************************************************************/
493 #endif /* __MCF523X_ETPU_H__ */