2 * These files are taken from the MCF523X source code example package
3 * which is available on the Freescale website. Freescale explicitly
4 * grants the redistribution and modification of these source files.
5 * The complete licensing information is available in the file
6 * LICENSE_FREESCALE.TXT.
9 * Purpose: Register and bit definitions for the MCF523X
15 #ifndef __MCF523X_FEC_H__
16 #define __MCF523X_FEC_H__
18 /*********************************************************************
20 * Fast Ethernet Controller (FEC)
22 *********************************************************************/
24 /* Register read/write macros */
25 #define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004]))
26 #define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008]))
27 #define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010]))
28 #define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014]))
29 #define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024]))
30 #define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040]))
31 #define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044]))
32 #define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064]))
33 #define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084]))
34 #define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4]))
35 #define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4]))
36 #define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8]))
37 #define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC]))
38 #define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118]))
39 #define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C]))
40 #define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120]))
41 #define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124]))
42 #define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144]))
43 #define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C]))
44 #define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150]))
45 #define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180]))
46 #define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184]))
47 #define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188]))
48 #define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200]))
49 #define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204]))
50 #define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208]))
51 #define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C]))
52 #define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210]))
53 #define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214]))
54 #define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218]))
55 #define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C]))
56 #define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220]))
57 #define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224]))
58 #define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228]))
59 #define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C]))
60 #define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230]))
61 #define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234]))
62 #define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238]))
63 #define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C]))
64 #define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240]))
65 #define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244]))
66 #define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248]))
67 #define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C]))
68 #define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250]))
69 #define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254]))
70 #define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258]))
71 #define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C]))
72 #define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260]))
73 #define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264]))
74 #define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268]))
75 #define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C]))
76 #define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270]))
77 #define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274]))
78 #define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284]))
79 #define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288]))
80 #define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C]))
81 #define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290]))
82 #define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294]))
83 #define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298]))
84 #define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C]))
85 #define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0]))
86 #define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4]))
87 #define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8]))
88 #define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC]))
89 #define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0]))
90 #define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4]))
91 #define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8]))
92 #define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0]))
93 #define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC]))
94 #define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4]))
95 #define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8]))
96 #define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC]))
97 #define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0]))
98 #define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4]))
99 #define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8]))
100 #define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC]))
101 #define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0]))
103 /* Bit definitions and macros for MCF_FEC_EIR */
104 #define MCF_FEC_EIR_UN (0x00080000)
105 #define MCF_FEC_EIR_RL (0x00100000)
106 #define MCF_FEC_EIR_LC (0x00200000)
107 #define MCF_FEC_EIR_EBERR (0x00400000)
108 #define MCF_FEC_EIR_MII (0x00800000)
109 #define MCF_FEC_EIR_RXB (0x01000000)
110 #define MCF_FEC_EIR_RXF (0x02000000)
111 #define MCF_FEC_EIR_TXB (0x04000000)
112 #define MCF_FEC_EIR_TXF (0x08000000)
113 #define MCF_FEC_EIR_GRA (0x10000000)
114 #define MCF_FEC_EIR_BABT (0x20000000)
115 #define MCF_FEC_EIR_BABR (0x40000000)
116 #define MCF_FEC_EIR_HBERR (0x80000000)
118 /* Bit definitions and macros for MCF_FEC_EIMR */
119 #define MCF_FEC_EIMR_UN (0x00080000)
120 #define MCF_FEC_EIMR_RL (0x00100000)
121 #define MCF_FEC_EIMR_LC (0x00200000)
122 #define MCF_FEC_EIMR_EBERR (0x00400000)
123 #define MCF_FEC_EIMR_MII (0x00800000)
124 #define MCF_FEC_EIMR_RXB (0x01000000)
125 #define MCF_FEC_EIMR_RXF (0x02000000)
126 #define MCF_FEC_EIMR_TXB (0x04000000)
127 #define MCF_FEC_EIMR_TXF (0x08000000)
128 #define MCF_FEC_EIMR_GRA (0x10000000)
129 #define MCF_FEC_EIMR_BABT (0x20000000)
130 #define MCF_FEC_EIMR_BABR (0x40000000)
131 #define MCF_FEC_EIMR_HBERR (0x80000000)
133 /* Bit definitions and macros for MCF_FEC_RDAR */
134 #define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000)
136 /* Bit definitions and macros for MCF_FEC_TDAR */
137 #define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000)
139 /* Bit definitions and macros for MCF_FEC_ECR */
140 #define MCF_FEC_ECR_RESET (0x00000001)
141 #define MCF_FEC_ECR_ETHER_EN (0x00000002)
143 /* Bit definitions and macros for MCF_FEC_MMFR */
144 #define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
145 #define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
146 #define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
147 #define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
148 #define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
149 #define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
150 #define MCF_FEC_MMFR_ST_01 (0x40000000)
151 #define MCF_FEC_MMFR_OP_READ (0x20000000)
152 #define MCF_FEC_MMFR_OP_WRITE (0x10000000)
153 #define MCF_FEC_MMFR_TA_10 (0x00020000)
156 /* Bit definitions and macros for MCF_FEC_MSCR */
157 #define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
158 #define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
160 /* Bit definitions and macros for MCF_FEC_MIBC */
161 #define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
162 #define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
164 /* Bit definitions and macros for MCF_FEC_RCR */
165 #define MCF_FEC_RCR_LOOP (0x00000001)
166 #define MCF_FEC_RCR_DRT (0x00000002)
167 #define MCF_FEC_RCR_MII_MODE (0x00000004)
168 #define MCF_FEC_RCR_PROM (0x00000008)
169 #define MCF_FEC_RCR_BC_REJ (0x00000010)
170 #define MCF_FEC_RCR_FCE (0x00000020)
171 #define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
173 /* Bit definitions and macros for MCF_FEC_TCR */
174 #define MCF_FEC_TCR_GTS (0x00000001)
175 #define MCF_FEC_TCR_HBC (0x00000002)
176 #define MCF_FEC_TCR_FDEN (0x00000004)
177 #define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
178 #define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
180 /* Bit definitions and macros for MCF_FEC_PAUR */
181 #define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
182 #define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
184 /* Bit definitions and macros for MCF_FEC_OPD */
185 #define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
186 #define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
188 /* Bit definitions and macros for MCF_FEC_TFWR */
189 #define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
191 /* Bit definitions and macros for MCF_FEC_FRBR */
192 #define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
194 /* Bit definitions and macros for MCF_FEC_FRSR */
195 #define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
197 /* Bit definitions and macros for MCF_FEC_ERDSR */
198 #define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
200 /* Bit definitions and macros for MCF_FEC_ETDSR */
201 #define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
203 /* Bit definitions and macros for MCF_FEC_EMRBR */
204 #define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
206 /********************************************************************/
208 #endif /* __MCF523X_FEC_H__ */