2 * These files are taken from the MCF523X source code example package
3 * which is available on the Freescale website. Freescale explicitly
4 * grants the redistribution and modification of these source files.
5 * The complete licensing information is available in the file
6 * LICENSE_FREESCALE.TXT.
8 * File: mcf523x_sdramc.h
9 * Purpose: Register and bit definitions for the MCF523X
15 #ifndef __MCF523X_SDRAMC_H__
16 #define __MCF523X_SDRAMC_H__
18 /*********************************************************************
20 * SDRAM Controller (SDRAMC)
22 *********************************************************************/
24 /* Register read/write macros */
25 #define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040]))
26 #define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
27 #define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
28 #define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
29 #define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
31 /* Bit definitions and macros for MCF_SDRAMC_DCR */
32 #define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
33 #define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
34 #define MCF_SDRAMC_DCR_IS (0x0800)
35 #define MCF_SDRAMC_DCR_COC (0x1000)
36 #define MCF_SDRAMC_DCR_NAM (0x2000)
38 /* Bit definitions and macros for MCF_SDRAMC_DACR0 */
39 #define MCF_SDRAMC_DACR0_IP (0x00000008)
40 #define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4)
41 #define MCF_SDRAMC_DACR0_MRS (0x00000040)
42 #define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8)
43 #define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12)
44 #define MCF_SDRAMC_DACR0_RE (0x00008000)
45 #define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18)
47 /* Bit definitions and macros for MCF_SDRAMC_DMR0 */
48 #define MCF_SDRAMC_DMR0_V (0x00000001)
49 #define MCF_SDRAMC_DMR0_WP (0x00000100)
50 #define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18)
52 /* Bit definitions and macros for MCF_SDRAMC_DACR1 */
53 #define MCF_SDRAMC_DACR1_IP (0x00000008)
54 #define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4)
55 #define MCF_SDRAMC_DACR1_MRS (0x00000040)
56 #define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8)
57 #define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12)
58 #define MCF_SDRAMC_DACR1_RE (0x00008000)
59 #define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18)
61 /* Bit definitions and macros for MCF_SDRAMC_DMR1 */
62 #define MCF_SDRAMC_DMR1_V (0x00000001)
63 #define MCF_SDRAMC_DMR1_WP (0x00000100)
64 #define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18)
66 /********************************************************************/
68 #define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000)
69 #define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000)
70 #define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000)
71 #define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000)
72 #define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000)
73 #define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000)
74 #define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000)
75 #define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000)
76 #define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000)
77 #define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000)
78 #define MCF_SDRAMC_DMR_BAM_8M (0x007C0000)
79 #define MCF_SDRAMC_DMR_BAM_4M (0x003C0000)
80 #define MCF_SDRAMC_DMR_BAM_2M (0x001C0000)
81 #define MCF_SDRAMC_DMR_BAM_1M (0x000C0000)
82 #define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000)
83 #define MCF_SDRAMC_DMR_BAM_512K (0x00040000)
84 #define MCF_SDRAMC_DMR_BAM_256K (0x00000000)
85 #define MCF_SDRAMC_DMR_WP (0x00000100)
86 #define MCF_SDRAMC_DMR_CI (0x00000040)
87 #define MCF_SDRAMC_DMR_AM (0x00000020)
88 #define MCF_SDRAMC_DMR_SC (0x00000010)
89 #define MCF_SDRAMC_DMR_SD (0x00000008)
90 #define MCF_SDRAMC_DMR_UC (0x00000004)
91 #define MCF_SDRAMC_DMR_UD (0x00000002)
92 #define MCF_SDRAMC_DMR_V (0x00000001)
94 #endif /* __MCF523X_SDRAMC_H__ */