2 * These files are taken from the MCF523X source code example package
3 * which is available on the Freescale website. Freescale explicitly
4 * grants the redistribution and modification of these source files.
5 * The complete licensing information is available in the file
6 * LICENSE_FREESCALE.TXT.
9 * Purpose: Definitions common to all ColdFire processors
14 #ifndef _CPU_MCF5XXX_H
15 #define _CPU_MCF5XXX_H
17 /***********************************************************************/
37 /***********************************************************************/
39 * The basic data types
42 typedef unsigned char uint8; /* 8 bits */
43 typedef unsigned short int uint16; /* 16 bits */
44 typedef unsigned long int uint32; /* 32 bits */
46 typedef signed char int8; /* 8 bits */
47 typedef signed short int int16; /* 16 bits */
48 typedef signed long int int32; /* 32 bits */
50 typedef volatile uint8 vuint8; /* 8 bits */
51 typedef volatile uint16 vuint16; /* 16 bits */
52 typedef volatile uint32 vuint32; /* 32 bits */
54 /***********************************************************************/
56 * Common M68K & ColdFire definitions
59 #define ADDRESS uint32
60 #define INSTRUCTION uint16
61 #define ILLEGAL 0x4AFC
62 #define CPU_WORD_SIZE 16
64 #define MCF5XXX_SR_T (0x8000)
65 #define MCF5XXX_SR_S (0x2000)
66 #define MCF5XXX_SR_M (0x1000)
67 #define MCF5XXX_SR_IPL (0x0700)
68 #define MCF5XXX_SR_IPL_0 (0x0000)
69 #define MCF5XXX_SR_IPL_1 (0x0100)
70 #define MCF5XXX_SR_IPL_2 (0x0200)
71 #define MCF5XXX_SR_IPL_3 (0x0300)
72 #define MCF5XXX_SR_IPL_4 (0x0400)
73 #define MCF5XXX_SR_IPL_5 (0x0500)
74 #define MCF5XXX_SR_IPL_6 (0x0600)
75 #define MCF5XXX_SR_IPL_7 (0x0700)
76 #define MCF5XXX_SR_X (0x0010)
77 #define MCF5XXX_SR_N (0x0008)
78 #define MCF5XXX_SR_Z (0x0004)
79 #define MCF5XXX_SR_V (0x0002)
80 #define MCF5XXX_SR_C (0x0001)
82 #define MCF5XXX_CACR_CENB (0x80000000)
83 #define MCF5XXX_CACR_CPDI (0x10000000)
84 #define MCF5XXX_CACR_CPD (0x10000000)
85 #define MCF5XXX_CACR_CFRZ (0x08000000)
86 #define MCF5XXX_CACR_CINV (0x01000000)
87 #define MCF5XXX_CACR_DIDI (0x00800000)
88 #define MCF5XXX_CACR_DISD (0x00400000)
89 #define MCF5XXX_CACR_INVI (0x00200000)
90 #define MCF5XXX_CACR_INVD (0x00100000)
91 #define MCF5XXX_CACR_CEIB (0x00000400)
92 #define MCF5XXX_CACR_DCM_WR (0x00000000)
93 #define MCF5XXX_CACR_DCM_CB (0x00000100)
94 #define MCF5XXX_CACR_DCM_IP (0x00000200)
95 #define MCF5XXX_CACR_DCM (0x00000200)
96 #define MCF5XXX_CACR_DCM_II (0x00000300)
97 #define MCF5XXX_CACR_DBWE (0x00000100)
98 #define MCF5XXX_CACR_DWP (0x00000020)
99 #define MCF5XXX_CACR_EUST (0x00000010)
100 #define MCF5XXX_CACR_CLNF_00 (0x00000000)
101 #define MCF5XXX_CACR_CLNF_01 (0x00000002)
102 #define MCF5XXX_CACR_CLNF_10 (0x00000004)
103 #define MCF5XXX_CACR_CLNF_11 (0x00000006)
105 #define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
106 #define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
107 #define MCF5XXX_ACR_EN (0x00008000)
108 #define MCF5XXX_ACR_SM_USER (0x00000000)
109 #define MCF5XXX_ACR_SM_SUPER (0x00002000)
110 #define MCF5XXX_ACR_SM_IGNORE (0x00006000)
111 #define MCF5XXX_ACR_ENIB (0x00000080)
112 #define MCF5XXX_ACR_CM (0x00000040)
113 #define MCF5XXX_ACR_DCM_WR (0x00000000)
114 #define MCF5XXX_ACR_DCM_CB (0x00000020)
115 #define MCF5XXX_ACR_DCM_IP (0x00000040)
116 #define MCF5XXX_ACR_DCM_II (0x00000060)
117 #define MCF5XXX_ACR_CM (0x00000040)
118 #define MCF5XXX_ACR_BWE (0x00000020)
119 #define MCF5XXX_ACR_WP (0x00000004)
121 #define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
122 #define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
123 #define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
124 #define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
125 #define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
126 #define MCF5XXX_RAMBAR_WP (0x00000100)
127 #define MCF5XXX_RAMBAR_CI (0x00000020)
128 #define MCF5XXX_RAMBAR_SC (0x00000010)
129 #define MCF5XXX_RAMBAR_SD (0x00000008)
130 #define MCF5XXX_RAMBAR_UC (0x00000004)
131 #define MCF5XXX_RAMBAR_UD (0x00000002)
132 #define MCF5XXX_RAMBAR_V (0x00000001)
134 /***********************************************************************/
136 * The ColdFire family of processors has a simplified exception stack
137 * frame that looks like the following:
139 * 3322222222221111 111111
140 * 1098765432109876 5432109876543210
141 * 8 +----------------+----------------+
142 * | Program Counter |
143 * 4 +----------------+----------------+
144 * |FS/Fmt/Vector/FS| SR |
145 * SP --> 0 +----------------+----------------+
147 * The stack self-aligns to a 4-byte boundary at an exception, with
148 * the FS/Fmt/Vector/FS field indicating the size of the adjustment
149 * (SP += 0,1,2,3 bytes).
152 #define MCF5XXX_RD_SF_FORMAT(PTR) \
153 ((*((uint16 *)(PTR)) >> 12) & 0x00FF)
155 #define MCF5XXX_RD_SF_VECTOR(PTR) \
156 ((*((uint16 *)(PTR)) >> 2) & 0x00FF)
158 #define MCF5XXX_RD_SF_FS(PTR) \
159 ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
161 #define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
162 #define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
164 /********************************************************************/
166 * Functions provided by mcf5xxx.s
169 int asm_set_ipl (uint32);
170 void mcf5xxx_wr_cacr (uint32);
171 void mcf5xxx_wr_acr0 (uint32);
172 void mcf5xxx_wr_acr1 (uint32);
173 void mcf5xxx_wr_acr2 (uint32);
174 void mcf5xxx_wr_acr3 (uint32);
175 void mcf5xxx_wr_other_a7 (uint32);
176 void mcf5xxx_wr_other_sp (uint32);
177 void mcf5xxx_wr_vbr (uint32);
178 void mcf5xxx_wr_macsr (uint32);
179 void mcf5xxx_wr_mask (uint32);
180 void mcf5xxx_wr_acc0 (uint32);
181 void mcf5xxx_wr_accext01 (uint32);
182 void mcf5xxx_wr_accext23 (uint32);
183 void mcf5xxx_wr_acc1 (uint32);
184 void mcf5xxx_wr_acc2 (uint32);
185 void mcf5xxx_wr_acc3 (uint32);
186 void mcf5xxx_wr_sr (uint32);
187 void mcf5xxx_wr_rambar0 (uint32);
188 void mcf5xxx_wr_rambar1 (uint32);
189 void mcf5xxx_wr_mbar (uint32);
190 void mcf5xxx_wr_mbar0 (uint32);
191 void mcf5xxx_wr_mbar1 (uint32);
193 /********************************************************************/
195 #endif /* _CPU_MCF5XXX_H */