2 FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
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4 This file is part of the FreeRTOS distribution.
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6 FreeRTOS is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License** as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 ***************************************************************************
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29 * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
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31 * This is a concise, step by step, 'hands on' guide that describes both *
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32 * general multitasking concepts and FreeRTOS specifics. It presents and *
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33 * explains numerous examples that are written using the FreeRTOS API. *
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34 * Full source code for all the examples is provided in an accompanying *
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37 ***************************************************************************
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38 ***************************************************************************
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40 Please ensure to read the configuration and relevant port sections of the
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41 online documentation.
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43 http://www.FreeRTOS.org - Documentation, latest information, license and
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46 http://www.SafeRTOS.com - A version that is certified for use in safety
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49 http://www.OpenRTOS.com - Commercial support, development, porting,
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50 licensing and training services.
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53 #include "mcf5xxx.h"
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54 #include "mcf523x.h"
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56 /* Function prototypes */
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57 void init_main( void );
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58 static void disable_interrupts( void );
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59 static void disable_watchdog_timer( void );
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60 static void disable_cache( void );
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61 static void init_ipsbar( void );
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62 static void init_basics( void );
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63 static void init_clock_config( void );
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64 static void init_chip_selects( void );
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65 static void init_bus_config( void );
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66 static void init_cache( void );
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67 static void init_eport( void );
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68 static void init_flexcan( void );
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69 static void init_power_management( void );
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70 static void init_dma_timers( void );
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71 static void init_interrupt_timers( void );
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72 static void init_watchdog_timers( void );
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73 static void init_pin_assignments( void );
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74 static void init_sdram_controller( void );
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75 static void init_interrupt_controller( void );
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78 /*********************************************************************
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79 * init_main - Main entry point for initialisation code *
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80 **********************************************************************/
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85 /* Initialise base address of peripherals, VBR, etc */
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88 init_clock_config( );
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90 /* Disable interrupts, watchdog timer, cache */
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91 disable_interrupts( );
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92 disable_watchdog_timer( );
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95 /* Initialise individual modules */
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96 init_chip_selects( );
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101 init_power_management( );
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102 init_dma_timers( );
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103 init_interrupt_timers( );
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104 init_watchdog_timers( );
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105 init_pin_assignments( );
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106 init_sdram_controller( );
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108 /* Initialise interrupt controller */
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109 init_interrupt_controller( );
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112 /*********************************************************************
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113 * disable_interrupts - Disable all interrupt sources *
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114 **********************************************************************/
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116 disable_interrupts( void )
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122 /* Set ICR008-ICR063 to 0x0 */
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123 p = ( vuint8 * ) & MCF_INTC0_ICR8;
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124 for( i = 8; i <= 63; i++ )
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127 /* Set ICR108-ICR163 to 0x0 */
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128 p = ( vuint8 * ) & MCF_INTC1_ICR8;
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129 for( i = 108; i <= 163; i++ )
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134 /*********************************************************************
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135 * disable_watchdog_timer - Disable system watchdog timer *
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136 **********************************************************************/
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138 disable_watchdog_timer( void )
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141 /* Disable Core Watchdog Timer */
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145 /*********************************************************************
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146 * disable_cache - Disable and invalidate cache *
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147 **********************************************************************/
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149 disable_cache( void )
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151 asm ( "move.l #0x01000000, %d0" );
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152 asm ( "movec %d0, %CACR" );
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155 /*********************************************************************
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156 * init_basics - Configuration Information & VBR *
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157 **********************************************************************/
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159 init_basics( void )
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162 extern uint32 __RAMVEC[];
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163 extern uint32 __ROMVEC[];
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165 /* Transfer size not driven on SIZ[1:0] pins during external cycles
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166 Processor Status (PST) and Debug Data (DDATA) functions disabled
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167 Bus monitor disabled
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168 Output pads configured for full strength
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170 MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME;
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172 /* Set up RAM vectors */
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173 for( i = 0; i < 256; i++ )
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176 __RAMVEC[i] = __ROMVEC[i];
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178 asm( "move.l %0,%%d0": :"i"( __RAMVEC ) );
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179 asm( "movec %d0,%vbr" );
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183 /*********************************************************************
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184 * init_clock_config - Clock Module *
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185 **********************************************************************/
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187 init_clock_config( void )
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189 /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)
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191 Bus clock frequency = 25.00 MHz
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192 Processor clock frequency = 2 x bus clock = 50.00 MHz
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193 Frequency Modulation disabled
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194 Loss of clock detection disabled
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195 Reset/Interrupt on loss of lock disabled
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197 MCF_FMPLL_SYNCR = 0x00100000; /* Set RFD=RFD+1 to avoid frequency overshoot */
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198 while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
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200 MCF_FMPLL_SYNCR = 0x00080000; /* Set desired RFD */
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201 while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
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206 /*********************************************************************
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207 * init_ipsbar - Internal Peripheral System Base Address (IPSBAR) *
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208 **********************************************************************/
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210 init_ipsbar( void )
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214 /* Base address of internal peripherals (IPSBAR) = 0x40000000
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216 Note: Processor powers up with IPS base address = 0x40000000
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217 Write to IPS base + 0x00000000 to set new value
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219 *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1;
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221 /* Configure RAMBAR in SCM module and allow dual-ported access. */
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222 MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE;
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225 /*********************************************************************
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226 * init_chip_selects - Chip Select Module *
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227 **********************************************************************/
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229 init_chip_selects( void )
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231 extern void __FLASH;
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232 uint32 FLASH_ADDR = (uint32)&__FLASH;
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234 /* Chip Select 0 - External Flash */
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235 MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR );
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237 | MCF_CS_CSCR_IWS( 6 )
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238 | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 );
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239 MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
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241 /* Chip Select 1 disabled (CSMR1[V] = 0) */
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246 /* Chip Select 2 disabled (CSMR2[V] = 0) */
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251 /* Chip Select 3 disabled (CSMR3[V] = 0) */
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256 /* Chip Select 4 disabled (CSMR4[V] = 0) */
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261 /* Chip Select 5 disabled (CSMR5[V] = 0) */
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266 /* Chip Select 6 disabled (CSMR6[V] = 0) */
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271 /* Chip Select 7 disabled (CSMR7[V] = 0) */
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277 /*********************************************************************
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278 * init_bus_config - Internal Bus Arbitration *
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279 **********************************************************************/
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281 init_bus_config( void )
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284 /* Use round robin arbitration scheme
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285 Assigned priorities (highest first):
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289 DMA bandwidth control disabled
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290 Park on last active bus master
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293 MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) |
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294 MCF_SCM_MPARK_M1_PRTY( 0x1 );
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297 /*********************************************************************
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298 * init_cache - Instruction/Data Cache *
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299 **********************************************************************/
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303 /* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache
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304 ACR0: Don't cache accesses to 16 MB memory region at address $20000000
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305 ACR1: Don't cache accesses to 1 GB memory region at address $40000000
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306 CACR: Cache accesses to the rest of memory
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308 asm("move.l #0x80000000,%d0");
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309 asm("movec %d0,%CACR");
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310 asm("move.l #0x2000c040,%d0");
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311 asm("movec %d0,%ACR0");
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312 asm("move.l #0x403fc040,%d0");
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313 asm("movec %d0,%ACR1");
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315 /* Instruction/Data cache disabled. */
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316 //asm( "move.l #0x00000000, %d0" );
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317 //asm( "movec %d0,%cacr" );
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320 /*********************************************************************
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321 * init_eport - Edge Port Module (EPORT) *
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322 **********************************************************************/
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327 /* Pins 1-7 configured as GPIO inputs */
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328 MCF_EPORT_EPPAR = 0;
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329 MCF_EPORT_EPDDR = 0;
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330 MCF_EPORT_EPIER = 0;
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333 /*********************************************************************
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334 * init_flexcan - FlexCAN Module *
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335 **********************************************************************/
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337 init_flexcan( void )
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340 /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */
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341 MCF_CAN_IMASK0 = 0;
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342 MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
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343 MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
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344 MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
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345 MCF_CAN_CANCTRL0 = 0;
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347 MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
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348 MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
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350 /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */
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351 MCF_CAN_IMASK1 = 0;
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352 MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
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353 MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
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354 MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
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355 MCF_CAN_CANCTRL1 = 0;
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357 MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
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358 MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
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361 /*********************************************************************
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362 * init_power_management - Power Management *
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363 **********************************************************************/
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365 init_power_management( void )
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368 /* On executing STOP instruction, processor enters RUN mode
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369 Mode is exited when an interrupt of level 1 or higher is received
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371 MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;
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375 /*********************************************************************
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376 * init_sdram_controller - SDRAM Controller *
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377 **********************************************************************/
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379 init_sdram_controller( void )
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381 extern void __SDRAM;
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382 uint32 SDRAM_ADDR = (uint32)&__SDRAM;
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387 * Check to see if the SDRAM has already been initialized
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388 * by a run control tool
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390 if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) )
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392 /* Initialize DRAM Control Register: DCR */
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393 MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) |
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394 MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) );
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396 /* Initialize DACR0 */
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397 MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) |
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398 MCF_SDRAMC_DACR0_CASL( 1 ) |
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399 MCF_SDRAMC_DACR0_CBM( 3 ) |
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400 MCF_SDRAMC_DACR0_PS( 0 ) );
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402 /* Initialize DMR0 */
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403 MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V );
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405 /* Set IP (bit 3) in DACR */
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406 MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP;
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408 /* Wait 30ns to allow banks to precharge */
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409 for( i = 0; i < 5; i++ )
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411 asm volatile ( " nop" );
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413 /* Write to this block to initiate precharge */
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414 *( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696;
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416 /* Set RE (bit 15) in DACR */
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417 MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE;
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419 /* Wait for at least 8 auto refresh cycles to occur */
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420 for( i = 0; i < 2000; i++ )
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422 asm volatile ( "nop" );
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424 /* Finish the configuration by issuing the IMRS. */
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425 MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS;
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427 /* Write to the SDRAM Mode Register */
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428 *( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696;
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432 /*********************************************************************
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433 * init_dma_timers - DMA Timer Modules *
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434 **********************************************************************/
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436 init_dma_timers( void )
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439 /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
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440 MCF_TIMER_DTMR0 = 0;
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441 MCF_TIMER_DTXMR0 = 0;
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442 MCF_TIMER_DTRR0 = 0xffffffff;
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444 /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
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445 MCF_TIMER_DTMR1 = 0;
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446 MCF_TIMER_DTXMR1 = 0;
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447 MCF_TIMER_DTRR1 = 0xffffffff;
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449 /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
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450 MCF_TIMER_DTMR2 = 0;
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451 MCF_TIMER_DTXMR2 = 0;
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452 MCF_TIMER_DTRR2 = 0xffffffff;
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454 /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
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455 MCF_TIMER_DTMR3 = 0;
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456 MCF_TIMER_DTXMR3 = 0;
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457 MCF_TIMER_DTRR3 = 0xffffffff;
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460 /**********************************************************************
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461 * init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules *
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462 ***********************************************************************/
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464 init_interrupt_timers( void )
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467 /* PIT0 disabled (PCSR0[EN]=0) */
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470 /* PIT1 disabled (PCSR1[EN]=0) */
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473 /* PIT2 disabled (PCSR2[EN]=0) */
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476 /* PIT3 disabled (PCSR3[EN]=0) */
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480 /*********************************************************************
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481 * init_watchdog_timers - Watchdog Timer Modules *
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482 **********************************************************************/
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484 init_watchdog_timers( void )
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487 /* Watchdog Timer disabled (WCR[EN]=0)
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488 NOTE: WCR and WMR cannot be written again until after the
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489 processor is reset.
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491 MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
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492 MCF_WTM_WMR = 0xffff;
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494 /* Core Watchdog Timer disabled (CWCR[CWE]=0) */
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498 /*********************************************************************
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499 * init_interrupt_controller - Interrupt Controller *
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500 **********************************************************************/
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502 init_interrupt_controller( void )
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505 /* Configured interrupt sources in order of priority...
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506 Level 7: External interrupt /IRQ7, (initially masked)
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507 Level 6: External interrupt /IRQ6, (initially masked)
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508 Level 5: External interrupt /IRQ5, (initially masked)
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509 Level 4: External interrupt /IRQ4, (initially masked)
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510 Level 3: External interrupt /IRQ3, (initially masked)
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511 Level 2: External interrupt /IRQ2, (initially masked)
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512 Level 1: External interrupt /IRQ1, (initially masked)
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514 MCF_INTC0_ICR1 = 0;
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515 MCF_INTC0_ICR2 = 0;
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516 MCF_INTC0_ICR3 = 0;
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517 MCF_INTC0_ICR4 = 0;
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518 MCF_INTC0_ICR5 = 0;
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519 MCF_INTC0_ICR6 = 0;
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520 MCF_INTC0_ICR7 = 0;
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521 MCF_INTC0_ICR8 = 0;
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522 MCF_INTC0_ICR9 = 0;
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523 MCF_INTC0_ICR10 = 0;
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524 MCF_INTC0_ICR11 = 0;
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525 MCF_INTC0_ICR12 = 0;
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526 MCF_INTC0_ICR13 = 0;
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527 MCF_INTC0_ICR14 = 0;
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528 MCF_INTC0_ICR15 = 0;
\r
529 MCF_INTC0_ICR17 = 0;
\r
530 MCF_INTC0_ICR18 = 0;
\r
531 MCF_INTC0_ICR19 = 0;
\r
532 MCF_INTC0_ICR20 = 0;
\r
533 MCF_INTC0_ICR21 = 0;
\r
534 MCF_INTC0_ICR22 = 0;
\r
535 MCF_INTC0_ICR23 = 0;
\r
536 MCF_INTC0_ICR24 = 0;
\r
537 MCF_INTC0_ICR25 = 0;
\r
538 MCF_INTC0_ICR26 = 0;
\r
539 MCF_INTC0_ICR27 = 0;
\r
540 MCF_INTC0_ICR28 = 0;
\r
541 MCF_INTC0_ICR29 = 0;
\r
542 MCF_INTC0_ICR30 = 0;
\r
543 MCF_INTC0_ICR31 = 0;
\r
544 MCF_INTC0_ICR32 = 0;
\r
545 MCF_INTC0_ICR33 = 0;
\r
546 MCF_INTC0_ICR34 = 0;
\r
547 MCF_INTC0_ICR35 = 0;
\r
548 MCF_INTC0_ICR36 = 0;
\r
549 MCF_INTC0_ICR37 = 0;
\r
550 MCF_INTC0_ICR38 = 0;
\r
551 MCF_INTC0_ICR39 = 0;
\r
552 MCF_INTC0_ICR40 = 0;
\r
553 MCF_INTC0_ICR41 = 0;
\r
554 MCF_INTC0_ICR42 = 0;
\r
555 MCF_INTC0_ICR43 = 0;
\r
556 MCF_INTC0_ICR44 = 0;
\r
557 MCF_INTC0_ICR45 = 0;
\r
558 MCF_INTC0_ICR46 = 0;
\r
559 MCF_INTC0_ICR47 = 0;
\r
560 MCF_INTC0_ICR48 = 0;
\r
561 MCF_INTC0_ICR49 = 0;
\r
562 MCF_INTC0_ICR50 = 0;
\r
563 MCF_INTC0_ICR51 = 0;
\r
564 MCF_INTC0_ICR52 = 0;
\r
565 MCF_INTC0_ICR53 = 0;
\r
566 MCF_INTC0_ICR54 = 0;
\r
567 MCF_INTC0_ICR55 = 0;
\r
568 MCF_INTC0_ICR56 = 0;
\r
569 MCF_INTC0_ICR57 = 0;
\r
570 MCF_INTC0_ICR58 = 0;
\r
571 MCF_INTC0_ICR59 = 0;
\r
572 MCF_INTC0_ICR60 = 0;
\r
573 MCF_INTC1_ICR8 = 0;
\r
574 MCF_INTC1_ICR9 = 0;
\r
575 MCF_INTC1_ICR10 = 0;
\r
576 MCF_INTC1_ICR11 = 0;
\r
577 MCF_INTC1_ICR12 = 0;
\r
578 MCF_INTC1_ICR13 = 0;
\r
579 MCF_INTC1_ICR14 = 0;
\r
580 MCF_INTC1_ICR15 = 0;
\r
581 MCF_INTC1_ICR16 = 0;
\r
582 MCF_INTC1_ICR17 = 0;
\r
583 MCF_INTC1_ICR18 = 0;
\r
584 MCF_INTC1_ICR19 = 0;
\r
585 MCF_INTC1_ICR20 = 0;
\r
586 MCF_INTC1_ICR21 = 0;
\r
587 MCF_INTC1_ICR22 = 0;
\r
588 MCF_INTC1_ICR23 = 0;
\r
589 MCF_INTC1_ICR24 = 0;
\r
590 MCF_INTC1_ICR25 = 0;
\r
591 MCF_INTC1_ICR27 = 0;
\r
592 MCF_INTC1_ICR28 = 0;
\r
593 MCF_INTC1_ICR29 = 0;
\r
594 MCF_INTC1_ICR30 = 0;
\r
595 MCF_INTC1_ICR31 = 0;
\r
596 MCF_INTC1_ICR32 = 0;
\r
597 MCF_INTC1_ICR33 = 0;
\r
598 MCF_INTC1_ICR34 = 0;
\r
599 MCF_INTC1_ICR35 = 0;
\r
600 MCF_INTC1_ICR36 = 0;
\r
601 MCF_INTC1_ICR37 = 0;
\r
602 MCF_INTC1_ICR38 = 0;
\r
603 MCF_INTC1_ICR39 = 0;
\r
604 MCF_INTC1_ICR40 = 0;
\r
605 MCF_INTC1_ICR41 = 0;
\r
606 MCF_INTC1_ICR42 = 0;
\r
607 MCF_INTC1_ICR59 = 0;
\r
608 MCF_INTC0_IMRH = 0xffffffff;
\r
610 MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 |
\r
611 MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 |
\r
612 MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 |
\r
613 MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 |
\r
614 MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 |
\r
615 MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 |
\r
616 MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 |
\r
617 MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 |
\r
618 MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 |
\r
619 MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 |
\r
620 MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 |
\r
621 MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 |
\r
622 MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 |
\r
623 MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 |
\r
624 MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 |
\r
625 MCF_INTC0_IMRL_INT_MASK1;
\r
626 MCF_INTC1_IMRH = 0xffffffff;
\r
628 MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 |
\r
629 MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 |
\r
630 MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 |
\r
631 MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 |
\r
632 MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 |
\r
633 MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 |
\r
634 MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 |
\r
635 MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 |
\r
636 MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 |
\r
637 MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 |
\r
638 MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 |
\r
639 MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 |
\r
640 MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 |
\r
641 MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 |
\r
642 MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 |
\r
643 MCF_INTC1_IMRL_INT_MASK1;
\r
646 /*********************************************************************
\r
647 * init_pin_assignments - Pin Assignment and General Purpose I/O *
\r
648 **********************************************************************/
\r
650 init_pin_assignments( void )
\r
653 /* Pin assignments for port ADDR
\r
654 Pins are all GPIO inputs
\r
656 MCF_GPIO_PDDR_APDDR = 0;
\r
657 MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23
\r
658 | MCF_GPIO_PAR_AD_PAR_ADDR22
\r
659 | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL;
\r
661 /* Pin assignments for ports DATAH and DATAL
\r
662 Pins are all GPIO inputs
\r
664 MCF_GPIO_PDDR_DATAH = 0;
\r
665 MCF_GPIO_PDDR_DATAL = 0;
\r
667 /* Pin assignments for port BUSCTL
\r
668 Pin /OE : External bus output enable, /OE
\r
669 Pin /TA : External bus transfer acknowledge, /TA
\r
670 Pin /TEA : External bus transfer error acknowledge, /TEA
\r
671 Pin R/W : External bus read/write indication, R/W
\r
672 Pin TSIZ1 : External bus transfer size TSIZ1 or DMA acknowledge /DACK1
\r
673 Pin TSIZ0 : External bus transfer size TSIZ0 or DMA acknowledge /DACK0
\r
674 Pin /TS : External bus transfer start, /TS
\r
675 Pin /TIP : External bus transfer in progess, /TIP
\r
677 MCF_GPIO_PDDR_BUSCTL = 0;
\r
678 MCF_GPIO_PAR_BUSCTL =
\r
679 MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA |
\r
680 MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB |
\r
681 MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 |
\r
682 MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) |
\r
683 MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 );
\r
685 /* Pin assignments for port BS
\r
686 Pin /BS3 : External byte strobe /BS3
\r
687 Pin /BS2 : External byte strobe /BS2
\r
688 Pin /BS1 : External byte strobe /BS1
\r
689 Pin /BS0 : External byte strobe /BS0
\r
691 MCF_GPIO_PDDR_BS = 0;
\r
693 MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 |
\r
694 MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0;
\r
696 /* Pin assignments for port CS
\r
697 Pin /CS7 : Chip select /CS7
\r
698 Pin /CS6 : Chip select /CS6
\r
699 Pin /CS5 : Chip select /CS5
\r
700 Pin /CS4 : Chip select /CS4
\r
701 Pin /CS3 : Chip select /CS3
\r
702 Pin /CS2 : Chip select /CS2
\r
703 Pin /CS1 : Chip select /CS1
\r
705 MCF_GPIO_PDDR_CS = 0;
\r
707 MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 |
\r
708 MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 |
\r
709 MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 |
\r
710 MCF_GPIO_PAR_CS_PAR_CS1;
\r
712 /* Pin assignments for port SDRAM
\r
713 Pin /SD_WE : SDRAM controller /SD_WE
\r
714 Pin /SD_SCAS : SDRAM controller /SD_SCAS
\r
715 Pin /SD_SRAS : SDRAM controller /SD_SRAS
\r
716 Pin /SD_SCKE : SDRAM controller /SD_SCKE
\r
717 Pin /SD_CS1 : SDRAM controller /SD_CS1
\r
718 Pin /SD_CS0 : SDRAM controller /SD_CS0
\r
720 MCF_GPIO_PDDR_SDRAM = 0;
\r
721 MCF_GPIO_PAR_SDRAM =
\r
722 MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS |
\r
723 MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE |
\r
724 MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0;
\r
726 /* Pin assignments for port FECI2C
\r
727 Pins are all GPIO inputs
\r
729 MCF_GPIO_PDDR_FECI2C = 0;
\r
730 MCF_GPIO_PAR_FECI2C =
\r
731 MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC;
\r
733 /* Pin assignments for port UARTL
\r
734 Pins are all GPIO inputs
\r
736 MCF_GPIO_PDDR_UARTL = 0;
\r
737 MCF_GPIO_PAR_UART = 0;
\r
739 /* Pin assignments for port UARTH
\r
740 Pin U2TXD : GPIO input
\r
741 Pin U2RXD : GPIO input
\r
742 Pin /IRQ2 : Interrupt request /IRQ2 or GPIO
\r
744 MCF_GPIO_PDDR_UARTH = 0;
\r
746 /* Pin assignments for port QSPI
\r
747 Pins are all GPIO inputs
\r
749 MCF_GPIO_PDDR_QSPI = 0;
\r
750 MCF_GPIO_PAR_QSPI = 0;
\r
752 /* Pin assignments for port TIMER
\r
753 Pins are all GPIO inputs
\r
755 MCF_GPIO_PDDR_TIMER = 0;
\r
756 MCF_GPIO_PAR_TIMER = 0;
\r
758 /* Pin assignments for port ETPU
\r
759 Pins are all GPIO inputs
\r
761 MCF_GPIO_PDDR_ETPU = 0;
\r
762 MCF_GPIO_PAR_ETPU = 0;
\r