2 * Lowest level routines for all ColdFire processors. Based on the
3 * MCF523x examples from Freescale.
5 * Freescale explicitly grants the redistribution and modification
6 * of these source files. The complete licensing information is
7 * available in the file LICENSE_FREESCALE.TXT.
9 * Modifications Copyright (c) 2006 Christian Walter <wolti@sil.at>
11 * File: $Id: mcf5xxx.S,v 1.2 2006/09/24 22:50:22 wolti Exp $
16 .global mcf5xxx_wr_cacr
17 .global _mcf5xxx_wr_cacr
18 .global mcf5xxx_wr_acr0
19 .global _mcf5xxx_wr_acr0
20 .global mcf5xxx_wr_acr1
21 .global _mcf5xxx_wr_acr1
22 .global mcf5xxx_wr_acr2
23 .global _mcf5xxx_wr_acr2
24 .global mcf5xxx_wr_acr3
25 .global _mcf5xxx_wr_acr3
26 .global mcf5xxx_wr_other_sp
27 .global _mcf5xxx_wr_other_sp
28 .global mcf5xxx_wr_other_a7
29 .global _mcf5xxx_wr_other_a7
30 .global mcf5xxx_wr_vbr
31 .global _mcf5xxx_wr_vbr
32 .global mcf5xxx_wr_macsr
33 .global _mcf5xxx_wr_macsr
34 .global mcf5xxx_wr_mask
35 .global _mcf5xxx_wr_mask
36 .global mcf5xxx_wr_acc0
37 .global _mcf5xxx_wr_acc0
38 .global mcf5xxx_wr_accext01
39 .global _mcf5xxx_wr_accext01
40 .global mcf5xxx_wr_accext23
41 .global _mcf5xxx_wr_accext23
42 .global mcf5xxx_wr_acc1
43 .global _mcf5xxx_wr_acc1
44 .global mcf5xxx_wr_acc2
45 .global _mcf5xxx_wr_acc2
46 .global mcf5xxx_wr_acc3
47 .global _mcf5xxx_wr_acc3
49 .global _mcf5xxx_wr_sr
50 .global mcf5xxx_wr_rambar0
51 .global _mcf5xxx_wr_rambar0
52 .global mcf5xxx_wr_rambar1
53 .global _mcf5xxx_wr_rambar1
54 .global mcf5xxx_wr_mbar
55 .global _mcf5xxx_wr_mbar
56 .global mcf5xxx_wr_mbar0
57 .global _mcf5xxx_wr_mbar0
58 .global mcf5xxx_wr_mbar1
59 .global _mcf5xxx_wr_mbar1
63 /********************************************************************/
65 * This routines changes the IPL to the value passed into the routine.
66 * It also returns the old IPL value back.
67 * Calling convention from C:
68 * old_ipl = asm_set_ipl(new_ipl);
69 * For the Diab Data C compiler, it passes return value thru D0.
70 * Note that only the least significant three bits of the passed
79 move.w sr,d7 /* current sr */
81 move.l d7,d0 /* prepare return value */
82 andi.l #0x0700,d0 /* mask out IPL */
85 move.l 8(a6),d6 /* get argument */
86 andi.l #0x07,d6 /* least significant three bits */
87 lsl.l #8,d6 /* move over to make mask */
89 andi.l #0x0000F8FF,d7 /* zero out current IPL */
90 or.l d6,d7 /* place new IPL in sr */
98 /********************************************************************/
100 * These routines write to the special purpose registers in the ColdFire
101 * core. Since these registers are write-only in the supervisor model,
102 * no corresponding read routines exist.
108 .long 0x4e7b0002 /* movec d0,cacr */
115 .long 0x4e7b0004 /* movec d0,ACR0 */
122 .long 0x4e7b0005 /* movec d0,ACR1 */
129 .long 0x4e7b0006 /* movec d0,ACR2 */
136 .long 0x4e7b0007 /* movec d0,ACR3 */
141 _mcf5xxx_wr_other_sp:
143 _mcf5xxx_wr_other_a7:
145 .long 0x4e7b0800 /* movec d0,OTHER_A7 */
152 .long 0x4e7b0801 /* movec d0,VBR */
159 .long 0x4e7b0804 /* movec d0,MACSR */
166 .long 0x4e7b0805 /* movec d0,MASK */
173 .long 0x4e7b0806 /* movec d0,ACC0 */
178 _mcf5xxx_wr_accext01:
180 .long 0x4e7b0807 /* movec d0,ACCEXT01 */
185 _mcf5xxx_wr_accext23:
187 .long 0x4e7b0808 /* movec d0,ACCEXT23 */
194 .long 0x4e7b0809 /* movec d0,ACC1 */
201 .long 0x4e7b080A /* movec d0,ACC2 */
208 .long 0x4e7b080B /* movec d0,ACC3 */
221 .long 0x4e7b0C04 /* movec d0,RAMBAR0 */
228 .long 0x4e7b0C05 /* movec d0,RAMBAR1 */
237 .long 0x4e7b0C0F /* movec d0,MBAR0 */
244 .long 0x4e7b0C0E /* movec d0,MBAR1 */
249 /********************************************************************/