2 FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 ***************************************************************************
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29 * SAVE TIME AND MONEY! Why not get us to quote to get FreeRTOS.org *
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30 * running on your hardware - or even write all or part of your application*
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31 * for you? See http://www.OpenRTOS.com for details. *
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33 ***************************************************************************
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34 ***************************************************************************
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36 Please ensure to read the configuration and relevant port sections of the
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37 online documentation.
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39 http://www.FreeRTOS.org - Documentation, latest information, license and
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42 http://www.SafeRTOS.com - A version that is certified for use in safety
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45 http://www.OpenRTOS.com - Commercial support, development, porting,
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46 licensing and training services.
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51 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
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54 /* Scheduler includes. */
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55 #include "FreeRTOS.h"
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59 /* Demo application includes. */
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62 /* Microblaze driver includes. */
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63 #include "xuartlite_l.h"
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64 #include "xintc_l.h"
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66 /*-----------------------------------------------------------*/
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68 /* Queues used to hold received characters, and characters waiting to be
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70 static xQueueHandle xRxedChars;
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71 static xQueueHandle xCharsForTx;
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73 /*-----------------------------------------------------------*/
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75 xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
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77 unsigned portLONG ulControlReg, ulMask;
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79 /* NOTE: The baud rate used by this driver is determined by the hardware
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80 parameterization of the UART Lite peripheral, and the baud value passed to
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81 this function has no effect. */
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83 /* Create the queues used to hold Rx and Tx characters. */
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84 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
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85 xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
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87 if( ( xRxedChars ) && ( xCharsForTx ) )
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89 /* Disable the interrupt. */
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90 XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );
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92 /* Flush the fifos. */
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93 ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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94 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );
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96 /* Enable the interrupt again. The interrupt controller has not yet been
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97 initialised so there is no chance of receiving an interrupt until the
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98 scheduler has been started. */
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99 XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );
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101 /* Enable the interrupt in the interrupt controller while maintaining
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102 all the other bit settings. */
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103 ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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104 ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;
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105 XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );
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106 XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );
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109 return ( xComPortHandle ) 0;
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111 /*-----------------------------------------------------------*/
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113 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
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115 /* The port handle is not required as this driver only supports one UART. */
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118 /* Get the next character from the buffer. Return false if no characters
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119 are available, or arrive before xBlockTime expires. */
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120 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
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129 /*-----------------------------------------------------------*/
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131 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
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133 portBASE_TYPE xReturn = pdTRUE;
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135 portENTER_CRITICAL();
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137 /* If the UART FIFO is full we can block posting the new data on the
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139 if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )
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141 if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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146 /* Otherwise, if there is data already in the queue we should add the
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147 new data to the back of the queue to ensure the sequencing is
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149 else if( uxQueueMessagesWaiting( xCharsForTx ) )
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151 if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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156 /* If the UART FIFO is not full and there is no data already in the
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157 queue we can write directly to the FIFO without disrupting the
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161 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
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164 portEXIT_CRITICAL();
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168 /*-----------------------------------------------------------*/
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170 void vSerialClose( xComPortHandle xPort )
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172 /* Not supported as not required by the demo application. */
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175 /*-----------------------------------------------------------*/
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177 void vSerialISR( void *pvBaseAddress )
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179 unsigned portLONG ulISRStatus;
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180 portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
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183 /* Determine the cause of the interrupt. */
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184 ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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186 if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 )
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188 /* A character is available - place it in the queue of received
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189 characters. This might wake a task that was blocked waiting for
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191 cChar = ( portCHAR )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );
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192 xTaskWokenByRx = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByRx );
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195 if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
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197 /* There is space in the FIFO - if there are any characters queue for
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198 transmission they can be send to the UART now. This might unblock a
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199 task that was waiting for space to become available on the Tx queue. */
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200 if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
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202 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
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206 /* If we woke any tasks we may require a context switch. */
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207 if( xTaskWokenByTx || xTaskWokenByRx )
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209 portYIELD_FROM_ISR();
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