2 FreeRTOS V6.0.1 - Copyright (C) 2009 Real Time Engineers Ltd.
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4 ***************************************************************************
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8 * + New to FreeRTOS, *
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9 * + Wanting to learn FreeRTOS or multitasking in general quickly *
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10 * + Looking for basic training, *
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11 * + Wanting to improve your FreeRTOS skills and productivity *
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13 * then take a look at the FreeRTOS eBook *
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15 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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16 * http://www.FreeRTOS.org/Documentation *
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18 * A pdf reference manual is also available. Both are usually delivered *
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20 * and 8pm GMT (although please allow up to 24 hours in case of *
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21 * exceptional circumstances). Thank you for your support! *
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23 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 ***NOTE*** The exception to the GPL is included to allow you to distribute
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31 a combined work that includes FreeRTOS without being obliged to provide the
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32 source code for proprietary components outside of the FreeRTOS kernel.
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33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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56 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
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59 /* Scheduler includes. */
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60 #include "FreeRTOS.h"
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64 /* Demo application includes. */
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67 /* Microblaze driver includes. */
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68 #include "xuartlite_l.h"
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69 #include "xintc_l.h"
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71 /*-----------------------------------------------------------*/
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73 /* Queues used to hold received characters, and characters waiting to be
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75 static xQueueHandle xRxedChars;
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76 static xQueueHandle xCharsForTx;
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78 /*-----------------------------------------------------------*/
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80 xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
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82 unsigned long ulControlReg, ulMask;
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84 /* NOTE: The baud rate used by this driver is determined by the hardware
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85 parameterization of the UART Lite peripheral, and the baud value passed to
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86 this function has no effect. */
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88 /* Create the queues used to hold Rx and Tx characters. */
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89 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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90 xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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92 if( ( xRxedChars ) && ( xCharsForTx ) )
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94 /* Disable the interrupt. */
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95 XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );
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97 /* Flush the fifos. */
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98 ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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99 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );
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101 /* Enable the interrupt again. The interrupt controller has not yet been
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102 initialised so there is no chance of receiving an interrupt until the
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103 scheduler has been started. */
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104 XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );
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106 /* Enable the interrupt in the interrupt controller while maintaining
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107 all the other bit settings. */
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108 ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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109 ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;
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110 XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );
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111 XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );
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114 return ( xComPortHandle ) 0;
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116 /*-----------------------------------------------------------*/
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118 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
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120 /* The port handle is not required as this driver only supports one UART. */
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123 /* Get the next character from the buffer. Return false if no characters
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124 are available, or arrive before xBlockTime expires. */
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125 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
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134 /*-----------------------------------------------------------*/
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136 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
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138 portBASE_TYPE xReturn = pdTRUE;
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140 portENTER_CRITICAL();
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142 /* If the UART FIFO is full we can block posting the new data on the
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144 if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )
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146 if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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151 /* Otherwise, if there is data already in the queue we should add the
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152 new data to the back of the queue to ensure the sequencing is
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154 else if( uxQueueMessagesWaiting( xCharsForTx ) )
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156 if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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161 /* If the UART FIFO is not full and there is no data already in the
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162 queue we can write directly to the FIFO without disrupting the
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166 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
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169 portEXIT_CRITICAL();
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173 /*-----------------------------------------------------------*/
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175 void vSerialClose( xComPortHandle xPort )
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177 /* Not supported as not required by the demo application. */
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180 /*-----------------------------------------------------------*/
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182 void vSerialISR( void *pvBaseAddress )
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184 unsigned long ulISRStatus;
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185 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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188 /* Determine the cause of the interrupt. */
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189 ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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191 if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 )
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193 /* A character is available - place it in the queue of received
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194 characters. This might wake a task that was blocked waiting for
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196 cChar = ( char )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );
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197 xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
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200 if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
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202 /* There is space in the FIFO - if there are any characters queue for
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203 transmission they can be send to the UART now. This might unblock a
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204 task that was waiting for space to become available on the Tx queue. */
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205 if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
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207 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
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211 /* If we woke any tasks we may require a context switch. */
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212 if( xHigherPriorityTaskWoken )
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214 portYIELD_FROM_ISR();
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