2 FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.
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4 This file is part of the FreeRTOS distribution.
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6 FreeRTOS is free software; you can redistribute it and/or modify it under
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7 the terms of the GNU General Public License (version 2) as published by the
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8 Free Software Foundation and modified by the FreeRTOS exception.
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9 **NOTE** The exception to the GPL is included to allow you to distribute a
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10 combined work that includes FreeRTOS without being obliged to provide the
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11 source code for proprietary components outside of the FreeRTOS kernel.
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12 Alternative commercial license and support terms are also available upon
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13 request. See the licensing section of http://www.FreeRTOS.org for full
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16 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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21 You should have received a copy of the GNU General Public License along
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22 with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
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23 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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26 ***************************************************************************
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28 * Looking for a quick start? Then check out the FreeRTOS eBook! *
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29 * See http://www.FreeRTOS.org/Documentation for details *
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31 ***************************************************************************
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35 Please ensure to read the configuration and relevant port sections of the
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36 online documentation.
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38 http://www.FreeRTOS.org - Documentation, latest information, license and
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41 http://www.SafeRTOS.com - A version that is certified for use in safety
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44 http://www.OpenRTOS.com - Commercial support, development, porting,
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45 licensing and training services.
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50 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
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53 /* Scheduler includes. */
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54 #include "FreeRTOS.h"
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58 /* Demo application includes. */
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61 /* Microblaze driver includes. */
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62 #include "xuartlite_l.h"
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63 #include "xintc_l.h"
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65 /*-----------------------------------------------------------*/
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67 /* Queues used to hold received characters, and characters waiting to be
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69 static xQueueHandle xRxedChars;
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70 static xQueueHandle xCharsForTx;
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72 /*-----------------------------------------------------------*/
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74 xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
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76 unsigned portLONG ulControlReg, ulMask;
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78 /* NOTE: The baud rate used by this driver is determined by the hardware
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79 parameterization of the UART Lite peripheral, and the baud value passed to
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80 this function has no effect. */
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82 /* Create the queues used to hold Rx and Tx characters. */
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83 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
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84 xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
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86 if( ( xRxedChars ) && ( xCharsForTx ) )
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88 /* Disable the interrupt. */
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89 XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );
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91 /* Flush the fifos. */
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92 ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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93 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );
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95 /* Enable the interrupt again. The interrupt controller has not yet been
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96 initialised so there is no chance of receiving an interrupt until the
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97 scheduler has been started. */
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98 XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );
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100 /* Enable the interrupt in the interrupt controller while maintaining
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101 all the other bit settings. */
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102 ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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103 ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;
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104 XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );
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105 XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );
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108 return ( xComPortHandle ) 0;
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110 /*-----------------------------------------------------------*/
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112 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
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114 /* The port handle is not required as this driver only supports one UART. */
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117 /* Get the next character from the buffer. Return false if no characters
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118 are available, or arrive before xBlockTime expires. */
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119 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
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128 /*-----------------------------------------------------------*/
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130 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
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132 portBASE_TYPE xReturn = pdTRUE;
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134 portENTER_CRITICAL();
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136 /* If the UART FIFO is full we can block posting the new data on the
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138 if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )
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140 if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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145 /* Otherwise, if there is data already in the queue we should add the
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146 new data to the back of the queue to ensure the sequencing is
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148 else if( uxQueueMessagesWaiting( xCharsForTx ) )
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150 if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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155 /* If the UART FIFO is not full and there is no data already in the
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156 queue we can write directly to the FIFO without disrupting the
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160 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
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163 portEXIT_CRITICAL();
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167 /*-----------------------------------------------------------*/
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169 void vSerialClose( xComPortHandle xPort )
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171 /* Not supported as not required by the demo application. */
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174 /*-----------------------------------------------------------*/
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176 void vSerialISR( void *pvBaseAddress )
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178 unsigned portLONG ulISRStatus;
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179 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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182 /* Determine the cause of the interrupt. */
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183 ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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185 if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 )
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187 /* A character is available - place it in the queue of received
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188 characters. This might wake a task that was blocked waiting for
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190 cChar = ( portCHAR )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );
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191 xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
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194 if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
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196 /* There is space in the FIFO - if there are any characters queue for
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197 transmission they can be send to the UART now. This might unblock a
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198 task that was waiting for space to become available on the Tx queue. */
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199 if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
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201 XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
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205 /* If we woke any tasks we may require a context switch. */
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206 if( xHigherPriorityTaskWoken )
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208 portYIELD_FROM_ISR();
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