1 <EDKSYSTEM EDKVERSION="13.1" EDWVERSION="1.2" TIMESTAMP="Mon May 30 20:51:59 2011">
3 <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/RTOSDemo.xmp" SPEEDGRADE="-3"/>
6 <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4_0" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="0" MODCLASS="BUS" MODTYPE="axi_interconnect">
7 <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
8 <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
10 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
13 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
14 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
15 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="2"/>
16 <PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1"/>
17 <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
18 <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
19 <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32"/>
20 <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
21 <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
22 <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
23 <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
24 <PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
25 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff00000000c4000000"/>
26 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c400ffff"/>
27 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000"/>
28 <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
29 <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
30 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e100"/>
31 <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
32 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100"/>
33 <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
34 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000"/>
35 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111101"/>
36 <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
37 <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
38 <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
39 <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/>
40 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5"/>
41 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5"/>
42 <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
43 <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
44 <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
45 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003"/>
46 <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
47 <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
48 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111100"/>
49 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
50 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000020"/>
51 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000200000002"/>
52 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000002"/>
53 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000002"/>
54 <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
55 <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
56 <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
57 <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
58 <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
59 <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
60 <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
61 <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
62 <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
63 <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
64 <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
65 <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
66 <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
67 <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
68 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
69 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
70 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
71 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
72 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000001"/>
73 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
74 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
75 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
76 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
77 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
78 <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/>
79 <PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1"/>
80 <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/>
81 <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/>
82 <PARAMETER MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/>
83 <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
84 <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
85 <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
86 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
87 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
88 <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/>
91 <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="interconnect_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
92 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
93 <PORT DEF_SIGNAME="axi4_0_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
94 <PORT DEF_SIGNAME="axi4_0_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
95 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
96 <PORT DEF_SIGNAME="axi4_0_S_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi4_0_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
97 <PORT DEF_SIGNAME="axi4_0_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi4_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
98 <PORT DEF_SIGNAME="axi4_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
99 <PORT DEF_SIGNAME="axi4_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
100 <PORT DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
101 <PORT DEF_SIGNAME="axi4_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
102 <PORT DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
103 <PORT DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
104 <PORT DEF_SIGNAME="axi4_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
105 <PORT DEF_SIGNAME="axi4_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
106 <PORT DEF_SIGNAME="axi4_0_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="15" MSB="9" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
107 <PORT DEF_SIGNAME="axi4_0_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi4_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
108 <PORT DEF_SIGNAME="axi4_0_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi4_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
109 <PORT DEF_SIGNAME="axi4_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
110 <PORT DEF_SIGNAME="axi4_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
111 <PORT DEF_SIGNAME="axi4_0_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi4_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
112 <PORT DEF_SIGNAME="axi4_0_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
113 <PORT DEF_SIGNAME="axi4_0_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi4_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
114 <PORT DEF_SIGNAME="axi4_0_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi4_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
115 <PORT DEF_SIGNAME="axi4_0_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi4_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
116 <PORT DEF_SIGNAME="axi4_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
117 <PORT DEF_SIGNAME="axi4_0_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
118 <PORT DEF_SIGNAME="axi4_0_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi4_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
119 <PORT DEF_SIGNAME="axi4_0_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi4_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
120 <PORT DEF_SIGNAME="axi4_0_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi4_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
121 <PORT DEF_SIGNAME="axi4_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
122 <PORT DEF_SIGNAME="axi4_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
123 <PORT DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
124 <PORT DEF_SIGNAME="axi4_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
125 <PORT DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
126 <PORT DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
127 <PORT DEF_SIGNAME="axi4_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
128 <PORT DEF_SIGNAME="axi4_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
129 <PORT DEF_SIGNAME="axi4_0_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="38" MSB="9" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
130 <PORT DEF_SIGNAME="axi4_0_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi4_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
131 <PORT DEF_SIGNAME="axi4_0_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi4_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
132 <PORT DEF_SIGNAME="axi4_0_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi4_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
133 <PORT DEF_SIGNAME="axi4_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
134 <PORT DEF_SIGNAME="axi4_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
135 <PORT DEF_SIGNAME="axi4_0_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi4_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
136 <PORT DEF_SIGNAME="axi4_0_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
137 <PORT DEF_SIGNAME="axi4_0_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi4_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
138 <PORT DEF_SIGNAME="axi4_0_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi4_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
139 <PORT DEF_SIGNAME="axi4_0_M_ACLK" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="axi4_0_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
140 <PORT DEF_SIGNAME="axi4_0_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="axi4_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
141 <PORT DEF_SIGNAME="axi4_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
142 <PORT DEF_SIGNAME="axi4_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
143 <PORT DEF_SIGNAME="axi4_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
144 <PORT DEF_SIGNAME="axi4_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
145 <PORT DEF_SIGNAME="axi4_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
146 <PORT DEF_SIGNAME="axi4_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
147 <PORT DEF_SIGNAME="axi4_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
148 <PORT DEF_SIGNAME="axi4_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
149 <PORT DEF_SIGNAME="axi4_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
150 <PORT DEF_SIGNAME="axi4_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="59" MSB="4" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
151 <PORT DEF_SIGNAME="axi4_0_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi4_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
152 <PORT DEF_SIGNAME="axi4_0_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi4_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
153 <PORT DEF_SIGNAME="axi4_0_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="axi4_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
154 <PORT DEF_SIGNAME="axi4_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
155 <PORT DEF_SIGNAME="axi4_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
156 <PORT DEF_SIGNAME="axi4_0_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi4_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
157 <PORT DEF_SIGNAME="axi4_0_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi4_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
158 <PORT DEF_SIGNAME="axi4_0_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi4_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
159 <PORT DEF_SIGNAME="axi4_0_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi4_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
160 <PORT DEF_SIGNAME="axi4_0_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="axi4_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
161 <PORT DEF_SIGNAME="axi4_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
162 <PORT DEF_SIGNAME="axi4_0_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi4_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
163 <PORT DEF_SIGNAME="axi4_0_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi4_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
164 <PORT DEF_SIGNAME="axi4_0_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi4_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
165 <PORT DEF_SIGNAME="axi4_0_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="axi4_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
166 <PORT DEF_SIGNAME="axi4_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
167 <PORT DEF_SIGNAME="axi4_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
168 <PORT DEF_SIGNAME="axi4_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
169 <PORT DEF_SIGNAME="axi4_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
170 <PORT DEF_SIGNAME="axi4_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
171 <PORT DEF_SIGNAME="axi4_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
172 <PORT DEF_SIGNAME="axi4_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
173 <PORT DEF_SIGNAME="axi4_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
174 <PORT DEF_SIGNAME="axi4_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
175 <PORT DEF_SIGNAME="axi4_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="84" MSB="4" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
176 <PORT DEF_SIGNAME="axi4_0_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi4_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
177 <PORT DEF_SIGNAME="axi4_0_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi4_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
178 <PORT DEF_SIGNAME="axi4_0_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="axi4_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
179 <PORT DEF_SIGNAME="axi4_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
180 <PORT DEF_SIGNAME="axi4_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
181 <PORT DEF_SIGNAME="axi4_0_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi4_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
182 <PORT DEF_SIGNAME="axi4_0_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi4_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
183 <PORT DEF_SIGNAME="axi4_0_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi4_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
184 <PORT DEF_SIGNAME="axi4_0_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi4_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
185 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
186 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
187 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
188 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
189 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
190 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
191 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
192 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
193 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
194 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
195 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
196 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
197 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
198 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
199 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
200 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
203 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
205 <PORTMAP DIR="I" PHYSICAL="interconnect_aclk"/>
206 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
207 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
208 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
209 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
210 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
211 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
212 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
213 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
214 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
215 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
216 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
217 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
218 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
219 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
220 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
221 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
226 <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
228 <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
232 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
234 <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.02.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="axi_interconnect">
235 <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
236 <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
238 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_02_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
241 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
242 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
243 <PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1"/>
244 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="7"/>
245 <PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
246 <PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
247 <PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32"/>
248 <PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
249 <PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
250 <PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
251 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002"/>
252 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000002000000020000000200000002000000020000000200000002"/>
253 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041200000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000041c00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040e00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040020000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000074800000"/>
254 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004120ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000041c0ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040e0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004002ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004060ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007480ffff"/>
255 <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
256 <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
257 <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
258 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100"/>
259 <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
260 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000102faf08002faf08002faf08002faf08002faf08002faf08002faf080"/>
261 <PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
262 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="50000000"/>
263 <PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
264 <PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
265 <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
266 <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
267 <PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/>
268 <PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
269 <PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
270 <PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
271 <PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
272 <PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
273 <PARAMETER MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"/>
274 <PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
275 <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
276 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
277 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111101111"/>
278 <PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
279 <PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
280 <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
281 <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
282 <PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
283 <PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
284 <PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
285 <PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
286 <PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
287 <PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
288 <PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
289 <PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
290 <PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
291 <PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
292 <PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
293 <PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
294 <PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
295 <PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
296 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
297 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
298 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
299 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
300 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
301 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
302 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
303 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
304 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
305 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000000100000001000000010000000100000001"/>
306 <PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/>
307 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0"/>
308 <PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/>
309 <PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/>
310 <PARAMETER MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/>
311 <PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
312 <PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
313 <PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
314 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
315 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
316 <PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/>
319 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn"/>
320 <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
321 <PORT DEF_SIGNAME="axi4lite_0_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4lite_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
322 <PORT DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="3" MSB="6" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
323 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
324 <PORT DEF_SIGNAME="axi4lite_0_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi4lite_0_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
325 <PORT DEF_SIGNAME="axi4lite_0_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
326 <PORT DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
327 <PORT DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
328 <PORT DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
329 <PORT DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
330 <PORT DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
331 <PORT DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
332 <PORT DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
333 <PORT DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
334 <PORT DEF_SIGNAME="axi4lite_0_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi4lite_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
335 <PORT DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
336 <PORT DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
337 <PORT DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
338 <PORT DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
339 <PORT DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
340 <PORT DEF_SIGNAME="axi4lite_0_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi4lite_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
341 <PORT DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
342 <PORT DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
343 <PORT DEF_SIGNAME="axi4lite_0_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
344 <PORT DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
345 <PORT DEF_SIGNAME="axi4lite_0_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi4lite_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
346 <PORT DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
347 <PORT DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
348 <PORT DEF_SIGNAME="axi4lite_0_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
349 <PORT DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
350 <PORT DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
351 <PORT DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
352 <PORT DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
353 <PORT DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
354 <PORT DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
355 <PORT DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
356 <PORT DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
357 <PORT DEF_SIGNAME="axi4lite_0_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi4lite_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
358 <PORT DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
359 <PORT DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
360 <PORT DEF_SIGNAME="axi4lite_0_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
361 <PORT DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
362 <PORT DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
363 <PORT DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
364 <PORT DEF_SIGNAME="axi4lite_0_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi4lite_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
365 <PORT DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
366 <PORT DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
367 <PORT DEF_SIGNAME="axi4lite_0_M_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="48" MSB="6" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi4lite_0_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
368 <PORT DEF_SIGNAME="axi4lite_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="49" MSB="6" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
369 <PORT DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="50" MSB="223" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
370 <PORT DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="51" MSB="55" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
371 <PORT DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="52" MSB="20" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
372 <PORT DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="53" MSB="13" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
373 <PORT DEF_SIGNAME="axi4lite_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="54" MSB="13" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
374 <PORT DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="55" MSB="27" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
375 <PORT DEF_SIGNAME="axi4lite_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="56" MSB="20" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
376 <PORT DEF_SIGNAME="axi4lite_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="57" MSB="27" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4lite_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
377 <PORT DEF_SIGNAME="axi4lite_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="58" MSB="27" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
378 <PORT DEF_SIGNAME="axi4lite_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="59" MSB="6" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4lite_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
379 <PORT DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="60" MSB="6" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi4lite_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
380 <PORT DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="61" MSB="6" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi4lite_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
381 <PORT DEF_SIGNAME="axi4lite_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="62" MSB="6" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4lite_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
382 <PORT DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="63" MSB="223" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
383 <PORT DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="64" MSB="27" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
384 <PORT DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="65" MSB="6" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi4lite_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
385 <PORT DEF_SIGNAME="axi4lite_0_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="66" MSB="6" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi4lite_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
386 <PORT DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="67" MSB="6" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi4lite_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
387 <PORT DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="68" MSB="6" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi4lite_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
388 <PORT DEF_SIGNAME="axi4lite_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="69" MSB="6" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
389 <PORT DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="70" MSB="13" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
390 <PORT DEF_SIGNAME="axi4lite_0_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="71" MSB="6" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi4lite_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
391 <PORT DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="72" MSB="6" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi4lite_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
392 <PORT DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="73" MSB="6" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi4lite_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
393 <PORT DEF_SIGNAME="axi4lite_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="74" MSB="6" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
394 <PORT DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="75" MSB="223" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
395 <PORT DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="55" LSB="0" MPD_INDEX="76" MSB="55" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
396 <PORT DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="77" MSB="20" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
397 <PORT DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="78" MSB="13" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
398 <PORT DEF_SIGNAME="axi4lite_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="79" MSB="13" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
399 <PORT DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="80" MSB="27" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
400 <PORT DEF_SIGNAME="axi4lite_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="20" LSB="0" MPD_INDEX="81" MSB="20" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
401 <PORT DEF_SIGNAME="axi4lite_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="82" MSB="27" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4lite_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
402 <PORT DEF_SIGNAME="axi4lite_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="27" LSB="0" MPD_INDEX="83" MSB="27" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
403 <PORT DEF_SIGNAME="axi4lite_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="84" MSB="6" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4lite_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
404 <PORT DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="85" MSB="6" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi4lite_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
405 <PORT DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="86" MSB="6" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi4lite_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
406 <PORT DEF_SIGNAME="axi4lite_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="87" MSB="6" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
407 <PORT DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="223" LSB="0" MPD_INDEX="88" MSB="223" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
408 <PORT DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="13" LSB="0" MPD_INDEX="89" MSB="13" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
409 <PORT DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="90" MSB="6" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi4lite_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
410 <PORT DEF_SIGNAME="axi4lite_0_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="91" MSB="6" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi4lite_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
411 <PORT DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="92" MSB="6" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi4lite_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
412 <PORT DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MPD_INDEX="93" MSB="6" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi4lite_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
413 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
414 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
415 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
416 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
417 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
418 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
419 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
420 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
421 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
422 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
423 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
424 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
425 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
426 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
427 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
428 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
431 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
433 <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
434 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
435 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
436 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
437 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
438 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
439 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
440 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
441 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
442 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
443 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
444 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
445 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
446 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
447 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
448 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
449 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
454 <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
456 <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
460 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
462 <MODULE HWVERSION="8.10.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="2" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
463 <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
464 <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
466 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_10_a/doc/microblaze.pdf" TYPE="IP"/>
469 <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
470 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
471 <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
472 <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
473 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
474 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
475 <PARAMETER MPD_INDEX="6" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0"/>
476 <PARAMETER MPD_INDEX="7" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
477 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/>
478 <PARAMETER MPD_INDEX="9" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0"/>
479 <PARAMETER MPD_INDEX="10" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
480 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="11" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2"/>
481 <PARAMETER MPD_INDEX="12" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0"/>
482 <PARAMETER MPD_INDEX="13" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
483 <PARAMETER MPD_INDEX="14" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
484 <PARAMETER MPD_INDEX="15" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
485 <PARAMETER MPD_INDEX="16" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
486 <PARAMETER MPD_INDEX="17" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
487 <PARAMETER MPD_INDEX="18" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
488 <PARAMETER MPD_INDEX="19" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
489 <PARAMETER MPD_INDEX="20" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
490 <PARAMETER MPD_INDEX="21" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
491 <PARAMETER MPD_INDEX="22" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
492 <PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
493 <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
494 <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
495 <PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
496 <PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
497 <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
498 <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
499 <PARAMETER MPD_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/>
500 <PARAMETER MPD_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/>
501 <PARAMETER MPD_INDEX="32" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
502 <PARAMETER MPD_INDEX="33" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
503 <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
504 <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
505 <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
506 <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
507 <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
508 <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
509 <PARAMETER MPD_INDEX="40" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/>
510 <PARAMETER MPD_INDEX="41" NAME="C_D_AXI" TYPE="integer" VALUE="0"/>
511 <PARAMETER MPD_INDEX="42" NAME="C_D_PLB" TYPE="integer" VALUE="0"/>
512 <PARAMETER MPD_INDEX="43" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
513 <PARAMETER MPD_INDEX="44" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
514 <PARAMETER MPD_INDEX="45" NAME="C_I_PLB" TYPE="integer" VALUE="0"/>
515 <PARAMETER MPD_INDEX="46" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
516 <PARAMETER MPD_INDEX="47" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1"/>
517 <PARAMETER MPD_INDEX="48" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1"/>
518 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="49" NAME="C_USE_BARREL" TYPE="integer" VALUE="1"/>
519 <PARAMETER MPD_INDEX="50" NAME="C_USE_DIV" TYPE="integer" VALUE="0"/>
520 <PARAMETER MPD_INDEX="51" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1"/>
521 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="52" NAME="C_USE_FPU" TYPE="integer" VALUE="1"/>
522 <PARAMETER MPD_INDEX="53" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="0"/>
523 <PARAMETER MPD_INDEX="54" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="0"/>
524 <PARAMETER MPD_INDEX="55" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="0"/>
525 <PARAMETER MPD_INDEX="56" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="0"/>
526 <PARAMETER MPD_INDEX="57" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"/>
527 <PARAMETER MPD_INDEX="58" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0"/>
528 <PARAMETER MPD_INDEX="59" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="0"/>
529 <PARAMETER MPD_INDEX="60" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="0"/>
530 <PARAMETER MPD_INDEX="61" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0"/>
531 <PARAMETER MPD_INDEX="62" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0"/>
532 <PARAMETER MPD_INDEX="63" NAME="C_PVR" TYPE="integer" VALUE="0"/>
533 <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="64" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00"/>
534 <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="65" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000"/>
535 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="66" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1"/>
536 <PARAMETER MPD_INDEX="67" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="1"/>
537 <PARAMETER MPD_INDEX="68" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="0"/>
538 <PARAMETER MPD_INDEX="69" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="0"/>
539 <PARAMETER MPD_INDEX="70" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0"/>
540 <PARAMETER MPD_INDEX="71" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1"/>
541 <PARAMETER MPD_INDEX="72" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000"/>
542 <PARAMETER MPD_INDEX="73" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="0"/>
543 <PARAMETER MPD_INDEX="74" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0"/>
544 <PARAMETER MPD_INDEX="75" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
545 <PARAMETER MPD_INDEX="76" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0"/>
546 <PARAMETER MPD_INDEX="77" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
547 <PARAMETER MPD_INDEX="78" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
548 <PARAMETER MPD_INDEX="79" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
549 <PARAMETER MPD_INDEX="80" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
550 <PARAMETER MPD_INDEX="81" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
551 <PARAMETER MPD_INDEX="82" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
552 <PARAMETER MPD_INDEX="83" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
553 <PARAMETER MPD_INDEX="84" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
554 <PARAMETER MPD_INDEX="85" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
555 <PARAMETER MPD_INDEX="86" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
556 <PARAMETER MPD_INDEX="87" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
557 <PARAMETER MPD_INDEX="88" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
558 <PARAMETER MPD_INDEX="89" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
559 <PARAMETER MPD_INDEX="90" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
560 <PARAMETER MPD_INDEX="91" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
561 <PARAMETER MPD_INDEX="92" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
562 <PARAMETER MPD_INDEX="93" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
563 <PARAMETER MPD_INDEX="94" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
564 <PARAMETER MPD_INDEX="95" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
565 <PARAMETER MPD_INDEX="96" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
566 <PARAMETER MPD_INDEX="97" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
567 <PARAMETER MPD_INDEX="98" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
568 <PARAMETER MPD_INDEX="99" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
569 <PARAMETER MPD_INDEX="100" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
570 <PARAMETER MPD_INDEX="101" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
571 <PARAMETER MPD_INDEX="102" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
572 <PARAMETER MPD_INDEX="103" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
573 <PARAMETER MPD_INDEX="104" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
574 <PARAMETER MPD_INDEX="105" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
575 <PARAMETER MPD_INDEX="106" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
576 <PARAMETER MPD_INDEX="107" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
577 <PARAMETER MPD_INDEX="108" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
578 <PARAMETER MPD_INDEX="109" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
579 <PARAMETER MPD_INDEX="110" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
580 <PARAMETER MPD_INDEX="111" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
581 <PARAMETER MPD_INDEX="112" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
582 <PARAMETER MPD_INDEX="113" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
583 <PARAMETER MPD_INDEX="114" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
584 <PARAMETER MPD_INDEX="115" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
585 <PARAMETER MPD_INDEX="116" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
586 <PARAMETER MPD_INDEX="117" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
587 <PARAMETER MPD_INDEX="118" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
588 <PARAMETER MPD_INDEX="119" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
589 <PARAMETER MPD_INDEX="120" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
590 <PARAMETER MPD_INDEX="121" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
591 <PARAMETER MPD_INDEX="122" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
592 <PARAMETER MPD_INDEX="123" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
593 <PARAMETER MPD_INDEX="124" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
594 <PARAMETER MPD_INDEX="125" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
595 <PARAMETER MPD_INDEX="126" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
596 <PARAMETER MPD_INDEX="127" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
597 <PARAMETER MPD_INDEX="128" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
598 <PARAMETER MPD_INDEX="129" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
599 <PARAMETER MPD_INDEX="130" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
600 <PARAMETER MPD_INDEX="131" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
601 <PARAMETER MPD_INDEX="132" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
602 <PARAMETER MPD_INDEX="133" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
603 <PARAMETER MPD_INDEX="134" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
604 <PARAMETER MPD_INDEX="135" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
605 <PARAMETER MPD_INDEX="136" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
606 <PARAMETER MPD_INDEX="137" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
607 <PARAMETER MPD_INDEX="138" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
608 <PARAMETER MPD_INDEX="139" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
609 <PARAMETER MPD_INDEX="140" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
610 <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="141" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000"/>
611 <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="142" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xcfffffff"/>
612 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="143" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1"/>
613 <PARAMETER MPD_INDEX="144" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1"/>
614 <PARAMETER MPD_INDEX="145" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="17"/>
615 <PARAMETER MPD_INDEX="146" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="8192"/>
616 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="0"/>
617 <PARAMETER MPD_INDEX="148" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4"/>
618 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="149" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1"/>
619 <PARAMETER MPD_INDEX="150" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
620 <PARAMETER MPD_INDEX="151" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0"/>
621 <PARAMETER MPD_INDEX="152" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0"/>
622 <PARAMETER MPD_INDEX="153" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0"/>
623 <PARAMETER MPD_INDEX="154" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
624 <PARAMETER MPD_INDEX="155" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
625 <PARAMETER MPD_INDEX="156" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
626 <PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
627 <PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
628 <PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
629 <PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
630 <PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
631 <PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
632 <PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
633 <PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
634 <PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
635 <PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
636 <PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
637 <PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
638 <PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
639 <PARAMETER MPD_INDEX="170" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
640 <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="171" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0000000"/>
641 <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="172" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0xcfffffff"/>
642 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="173" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1"/>
643 <PARAMETER MPD_INDEX="174" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1"/>
644 <PARAMETER MPD_INDEX="175" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="17"/>
645 <PARAMETER MPD_INDEX="176" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="8192"/>
646 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/>
647 <PARAMETER MPD_INDEX="178" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4"/>
648 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="179" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1"/>
649 <PARAMETER MPD_INDEX="180" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
650 <PARAMETER MPD_INDEX="181" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0"/>
651 <PARAMETER MPD_INDEX="182" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0"/>
652 <PARAMETER MPD_INDEX="183" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0"/>
653 <PARAMETER MPD_INDEX="184" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
654 <PARAMETER MPD_INDEX="185" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
655 <PARAMETER MPD_INDEX="186" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
656 <PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
657 <PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
658 <PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
659 <PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
660 <PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
661 <PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
662 <PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
663 <PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
664 <PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
665 <PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
666 <PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
667 <PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
668 <PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
669 <PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
670 <PARAMETER MPD_INDEX="201" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/>
671 <PARAMETER MPD_INDEX="202" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/>
672 <PARAMETER MPD_INDEX="203" NAME="C_USE_MMU" TYPE="integer" VALUE="0"/>
673 <PARAMETER MPD_INDEX="204" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4"/>
674 <PARAMETER MPD_INDEX="205" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2"/>
675 <PARAMETER MPD_INDEX="206" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3"/>
676 <PARAMETER MPD_INDEX="207" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16"/>
677 <PARAMETER MPD_INDEX="208" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0"/>
678 <PARAMETER MPD_INDEX="209" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="0"/>
679 <PARAMETER MPD_INDEX="210" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="0"/>
680 <PARAMETER MPD_INDEX="211" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="0"/>
681 <PARAMETER MPD_INDEX="212" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0"/>
682 <PARAMETER MPD_INDEX="213" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0"/>
683 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_M_AXI_DC_AW_REGISTER" VALUE="1"/>
684 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_M_AXI_DC_W_REGISTER" VALUE="1"/>
685 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" NAME="C_INTERCONNECT_M_AXI_DP_AW_REGISTER" VALUE="1"/>
686 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" NAME="C_INTERCONNECT_M_AXI_DP_AR_REGISTER" VALUE="1"/>
687 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_M_AXI_DP_W_REGISTER" VALUE="1"/>
688 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" NAME="C_INTERCONNECT_M_AXI_DP_R_REGISTER" VALUE="1"/>
689 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" NAME="C_INTERCONNECT_M_AXI_DP_B_REGISTER" VALUE="1"/>
690 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" NAME="C_INTERCONNECT_M_AXI_DC_AR_REGISTER" VALUE="1"/>
691 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" NAME="C_INTERCONNECT_M_AXI_DC_R_REGISTER" VALUE="1"/>
692 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" NAME="C_INTERCONNECT_M_AXI_DC_B_REGISTER" VALUE="1"/>
693 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" NAME="C_INTERCONNECT_M_AXI_IC_AW_REGISTER" VALUE="1"/>
694 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" NAME="C_INTERCONNECT_M_AXI_IC_AR_REGISTER" VALUE="1"/>
695 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="26" NAME="C_INTERCONNECT_M_AXI_IC_W_REGISTER" VALUE="1"/>
696 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" NAME="C_INTERCONNECT_M_AXI_IC_R_REGISTER" VALUE="1"/>
697 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_IC_B_REGISTER" VALUE="1"/>
700 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
701 <PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
702 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt"/>
703 <PORT BUS="DLMB:ILMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
704 <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/>
705 <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/>
706 <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
707 <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
708 <PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/>
709 <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
710 <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="I" MPD_INDEX="10" NAME="IREADY" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
711 <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="I" MPD_INDEX="11" NAME="IWAIT" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
712 <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="I" MPD_INDEX="12" NAME="ICE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
713 <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="I" MPD_INDEX="13" NAME="IUE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
714 <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:31]"/>
715 <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="IFETCH" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
716 <PORT BUS="ILMB" DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="16" NAME="I_AS" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
717 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="17" NAME="IPLB_M_ABort" SIGNAME="__NOC__"/>
718 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
719 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
720 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/>
721 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="IPLB_M_busLock" SIGNAME="__NOC__"/>
722 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="IPLB_M_lockErr" SIGNAME="__NOC__"/>
723 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
724 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
725 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="25" NAME="IPLB_M_rdBurst" SIGNAME="__NOC__"/>
726 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="IPLB_M_request" SIGNAME="__NOC__"/>
727 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="27" NAME="IPLB_M_RNW" SIGNAME="__NOC__"/>
728 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
729 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
730 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="30" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
731 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="IPLB_M_wrBurst" SIGNAME="__NOC__"/>
732 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
733 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="IPLB_MBusy" SIGNAME="__NOC__"/>
734 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="IPLB_MRdErr" SIGNAME="__NOC__"/>
735 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrErr" SIGNAME="__NOC__"/>
736 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="IPLB_MIRQ" SIGNAME="__NOC__"/>
737 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="IPLB_MWrBTerm" SIGNAME="__NOC__"/>
738 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrDAck" SIGNAME="__NOC__"/>
739 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="IPLB_MAddrAck" SIGNAME="__NOC__"/>
740 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="40" NAME="IPLB_MRdBTerm" SIGNAME="__NOC__"/>
741 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="IPLB_MRdDAck" SIGNAME="__NOC__"/>
742 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="42" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
743 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
744 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="IPLB_MRearbitrate" SIGNAME="__NOC__"/>
745 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
746 <PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="IPLB_MTimeout" SIGNAME="__NOC__"/>
747 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
748 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="I" MPD_INDEX="48" NAME="DREADY" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
749 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="I" MPD_INDEX="49" NAME="DWAIT" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
750 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="I" MPD_INDEX="50" NAME="DCE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
751 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="I" MPD_INDEX="51" NAME="DUE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
752 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:31]"/>
753 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:31]"/>
754 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="54" NAME="D_AS" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
755 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="55" NAME="READ_STROBE" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
756 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="56" NAME="WRITE_STROBE" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
757 <PORT BUS="DLMB" DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:3]"/>
758 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="DPLB_M_ABort" SIGNAME="__NOC__"/>
759 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="59" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
760 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="60" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
761 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/>
762 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="DPLB_M_busLock" SIGNAME="__NOC__"/>
763 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="63" NAME="DPLB_M_lockErr" SIGNAME="__NOC__"/>
764 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
765 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
766 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="DPLB_M_rdBurst" SIGNAME="__NOC__"/>
767 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="DPLB_M_request" SIGNAME="__NOC__"/>
768 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="DPLB_M_RNW" SIGNAME="__NOC__"/>
769 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="69" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
770 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="70" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
771 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="71" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
772 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="DPLB_M_wrBurst" SIGNAME="__NOC__"/>
773 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="73" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
774 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="DPLB_MBusy" SIGNAME="__NOC__"/>
775 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="DPLB_MRdErr" SIGNAME="__NOC__"/>
776 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="DPLB_MWrErr" SIGNAME="__NOC__"/>
777 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="DPLB_MIRQ" SIGNAME="__NOC__"/>
778 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="DPLB_MWrBTerm" SIGNAME="__NOC__"/>
779 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrDAck" SIGNAME="__NOC__"/>
780 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="DPLB_MAddrAck" SIGNAME="__NOC__"/>
781 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="DPLB_MRdBTerm" SIGNAME="__NOC__"/>
782 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="DPLB_MRdDAck" SIGNAME="__NOC__"/>
783 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="83" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
784 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
785 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/>
786 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="86" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
787 <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/>
788 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
789 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="89" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
790 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="90" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
791 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="91" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
792 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="92" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
793 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
794 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
795 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="95" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
796 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="96" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
797 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
798 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
799 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="99" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
800 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="100" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
801 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
802 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
803 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
804 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
805 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="105" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
806 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
807 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
808 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
809 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="109" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
810 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="110" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
811 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="111" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
812 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="112" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
813 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
814 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="114" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
815 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
816 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="116" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
817 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
818 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="118" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
819 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="119" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
820 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="120" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
821 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="121" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
822 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
823 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
824 <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="124" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
825 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWID" DIR="O" MPD_INDEX="125" NAME="M_AXI_DP_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
826 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="126" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
827 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[7:0]"/>
828 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="128" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[2:0]"/>
829 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[1:0]"/>
830 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="O" MPD_INDEX="130" NAME="M_AXI_DP_AWLOCK" SIGNAME="axi4lite_0_S_AWLOCK"/>
831 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="131" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[3:0]"/>
832 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="132" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[2:0]"/>
833 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="133" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[3:0]"/>
834 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="O" MPD_INDEX="134" NAME="M_AXI_DP_AWVALID" SIGNAME="axi4lite_0_S_AWVALID"/>
835 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="I" MPD_INDEX="135" NAME="M_AXI_DP_AWREADY" SIGNAME="axi4lite_0_S_AWREADY"/>
836 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="136" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
837 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="137" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/>
838 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="O" MPD_INDEX="138" NAME="M_AXI_DP_WLAST" SIGNAME="axi4lite_0_S_WLAST"/>
839 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="O" MPD_INDEX="139" NAME="M_AXI_DP_WVALID" SIGNAME="axi4lite_0_S_WVALID"/>
840 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="I" MPD_INDEX="140" NAME="M_AXI_DP_WREADY" SIGNAME="axi4lite_0_S_WREADY"/>
841 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BID" DIR="I" MPD_INDEX="141" NAME="M_AXI_DP_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
842 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="142" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[1:0]"/>
843 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_BVALID" SIGNAME="axi4lite_0_S_BVALID"/>
844 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="O" MPD_INDEX="144" NAME="M_AXI_DP_BREADY" SIGNAME="axi4lite_0_S_BREADY"/>
845 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARID" DIR="O" MPD_INDEX="145" NAME="M_AXI_DP_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
846 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
847 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="147" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[7:0]"/>
848 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="148" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[2:0]"/>
849 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="149" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[1:0]"/>
850 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="O" MPD_INDEX="150" NAME="M_AXI_DP_ARLOCK" SIGNAME="axi4lite_0_S_ARLOCK"/>
851 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[3:0]"/>
852 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="152" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[2:0]"/>
853 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="153" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[3:0]"/>
854 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="O" MPD_INDEX="154" NAME="M_AXI_DP_ARVALID" SIGNAME="axi4lite_0_S_ARVALID"/>
855 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="I" MPD_INDEX="155" NAME="M_AXI_DP_ARREADY" SIGNAME="axi4lite_0_S_ARREADY"/>
856 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RID" DIR="I" MPD_INDEX="156" NAME="M_AXI_DP_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
857 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
858 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="158" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[1:0]"/>
859 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="I" MPD_INDEX="159" NAME="M_AXI_DP_RLAST" SIGNAME="axi4lite_0_S_RLAST"/>
860 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="I" MPD_INDEX="160" NAME="M_AXI_DP_RVALID" SIGNAME="axi4lite_0_S_RVALID"/>
861 <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="O" MPD_INDEX="161" NAME="M_AXI_DP_RREADY" SIGNAME="axi4lite_0_S_RREADY"/>
862 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="162" NAME="M_AXI_IC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
863 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
864 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="164" MSB="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
865 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="165" MSB="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
866 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="166" MSB="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
867 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="167" NAME="M_AXI_IC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
868 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="168" MSB="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
869 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="169" MSB="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
870 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="170" MSB="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
871 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="171" NAME="M_AXI_IC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
872 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="172" NAME="M_AXI_IC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
873 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="173" MSB="4" NAME="M_AXI_IC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_IC_AWUSER_WIDTH-1):0]"/>
874 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
875 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="175" MSB="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_IC_DATA_WIDTH/8)-1):0]"/>
876 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="176" NAME="M_AXI_IC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
877 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="177" NAME="M_AXI_IC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
878 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="178" NAME="M_AXI_IC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
879 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="179" NAME="M_AXI_IC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_IC_WUSER_WIDTH-1):0]"/>
880 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="180" NAME="M_AXI_IC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
881 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="181" MSB="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
882 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="182" NAME="M_AXI_IC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
883 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="183" NAME="M_AXI_IC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
884 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="184" NAME="M_AXI_IC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_IC_BUSER_WIDTH-1):0]"/>
885 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="185" NAME="M_AXI_IC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
886 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
887 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="187" MSB="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
888 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="188" MSB="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
889 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="189" MSB="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
890 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="190" NAME="M_AXI_IC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
891 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="191" MSB="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
892 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="192" MSB="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
893 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="193" MSB="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
894 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="194" NAME="M_AXI_IC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
895 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="195" NAME="M_AXI_IC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
896 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="196" MSB="4" NAME="M_AXI_IC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_IC_ARUSER_WIDTH-1):0]"/>
897 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="197" NAME="M_AXI_IC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
898 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="198" MSB="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
899 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="199" MSB="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
900 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="200" NAME="M_AXI_IC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
901 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="201" NAME="M_AXI_IC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
902 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="202" NAME="M_AXI_IC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
903 <PORT BUS="M_AXI_IC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="203" NAME="M_AXI_IC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_IC_RUSER_WIDTH-1):0]"/>
904 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWID" DIR="O" MPD_INDEX="204" NAME="M_AXI_DC_AWID" SIGNAME="axi4_0_S_AWID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
905 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="205" MSB="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGNAME="axi4_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
906 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="206" MSB="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGNAME="axi4_0_S_AWLEN" VECFORMULA="[7:0]"/>
907 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="207" MSB="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGNAME="axi4_0_S_AWSIZE" VECFORMULA="[2:0]"/>
908 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="208" MSB="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGNAME="axi4_0_S_AWBURST" VECFORMULA="[1:0]"/>
909 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWLOCK" DIR="O" MPD_INDEX="209" NAME="M_AXI_DC_AWLOCK" SIGNAME="axi4_0_S_AWLOCK"/>
910 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGNAME="axi4_0_S_AWCACHE" VECFORMULA="[3:0]"/>
911 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="211" MSB="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGNAME="axi4_0_S_AWPROT" VECFORMULA="[2:0]"/>
912 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="212" MSB="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGNAME="axi4_0_S_AWQOS" VECFORMULA="[3:0]"/>
913 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWVALID" DIR="O" MPD_INDEX="213" NAME="M_AXI_DC_AWVALID" SIGNAME="axi4_0_S_AWVALID"/>
914 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWREADY" DIR="I" MPD_INDEX="214" NAME="M_AXI_DC_AWREADY" SIGNAME="axi4_0_S_AWREADY"/>
915 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="215" MSB="4" NAME="M_AXI_DC_AWUSER" RIGHT="0" SIGNAME="axi4_0_S_AWUSER" VECFORMULA="[(C_M_AXI_DC_AWUSER_WIDTH-1):0]"/>
916 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="216" MSB="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGNAME="axi4_0_S_WDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
917 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="217" MSB="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGNAME="axi4_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DC_DATA_WIDTH/8)-1):0]"/>
918 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WLAST" DIR="O" MPD_INDEX="218" NAME="M_AXI_DC_WLAST" SIGNAME="axi4_0_S_WLAST"/>
919 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WVALID" DIR="O" MPD_INDEX="219" NAME="M_AXI_DC_WVALID" SIGNAME="axi4_0_S_WVALID"/>
920 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WREADY" DIR="I" MPD_INDEX="220" NAME="M_AXI_DC_WREADY" SIGNAME="axi4_0_S_WREADY"/>
921 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_WUSER" DIR="O" MPD_INDEX="221" NAME="M_AXI_DC_WUSER" SIGNAME="axi4_0_S_WUSER" VECFORMULA="[(C_M_AXI_DC_WUSER_WIDTH-1):0]"/>
922 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BID" DIR="I" MPD_INDEX="222" NAME="M_AXI_DC_BID" SIGNAME="axi4_0_S_BID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
923 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGNAME="axi4_0_S_BRESP" VECFORMULA="[1:0]"/>
924 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BVALID" DIR="I" MPD_INDEX="224" NAME="M_AXI_DC_BVALID" SIGNAME="axi4_0_S_BVALID"/>
925 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BREADY" DIR="O" MPD_INDEX="225" NAME="M_AXI_DC_BREADY" SIGNAME="axi4_0_S_BREADY"/>
926 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_BUSER" DIR="I" MPD_INDEX="226" NAME="M_AXI_DC_BUSER" SIGNAME="axi4_0_S_BUSER" VECFORMULA="[(C_M_AXI_DC_BUSER_WIDTH-1):0]"/>
927 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARID" DIR="O" MPD_INDEX="227" NAME="M_AXI_DC_ARID" SIGNAME="axi4_0_S_ARID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
928 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="228" MSB="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGNAME="axi4_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
929 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="229" MSB="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGNAME="axi4_0_S_ARLEN" VECFORMULA="[7:0]"/>
930 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="230" MSB="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGNAME="axi4_0_S_ARSIZE" VECFORMULA="[2:0]"/>
931 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="231" MSB="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGNAME="axi4_0_S_ARBURST" VECFORMULA="[1:0]"/>
932 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARLOCK" DIR="O" MPD_INDEX="232" NAME="M_AXI_DC_ARLOCK" SIGNAME="axi4_0_S_ARLOCK"/>
933 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="233" MSB="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGNAME="axi4_0_S_ARCACHE" VECFORMULA="[3:0]"/>
934 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="234" MSB="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGNAME="axi4_0_S_ARPROT" VECFORMULA="[2:0]"/>
935 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGNAME="axi4_0_S_ARQOS" VECFORMULA="[3:0]"/>
936 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARVALID" DIR="O" MPD_INDEX="236" NAME="M_AXI_DC_ARVALID" SIGNAME="axi4_0_S_ARVALID"/>
937 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARREADY" DIR="I" MPD_INDEX="237" NAME="M_AXI_DC_ARREADY" SIGNAME="axi4_0_S_ARREADY"/>
938 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="238" MSB="4" NAME="M_AXI_DC_ARUSER" RIGHT="0" SIGNAME="axi4_0_S_ARUSER" VECFORMULA="[(C_M_AXI_DC_ARUSER_WIDTH-1):0]"/>
939 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RID" DIR="I" MPD_INDEX="239" NAME="M_AXI_DC_RID" SIGNAME="axi4_0_S_RID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
940 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGNAME="axi4_0_S_RDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
941 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="241" MSB="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGNAME="axi4_0_S_RRESP" VECFORMULA="[1:0]"/>
942 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RLAST" DIR="I" MPD_INDEX="242" NAME="M_AXI_DC_RLAST" SIGNAME="axi4_0_S_RLAST"/>
943 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RVALID" DIR="I" MPD_INDEX="243" NAME="M_AXI_DC_RVALID" SIGNAME="axi4_0_S_RVALID"/>
944 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RREADY" DIR="O" MPD_INDEX="244" NAME="M_AXI_DC_RREADY" SIGNAME="axi4_0_S_RREADY"/>
945 <PORT BUS="M_AXI_DC" DEF_SIGNAME="axi4_0_S_RUSER" DIR="I" MPD_INDEX="245" NAME="M_AXI_DC_RUSER" SIGNAME="axi4_0_S_RUSER" VECFORMULA="[(C_M_AXI_DC_RUSER_WIDTH-1):0]"/>
946 <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="I" MPD_INDEX="246" NAME="DBG_CLK" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
947 <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="I" MPD_INDEX="247" NAME="DBG_TDI" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
948 <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="O" MPD_INDEX="248" NAME="DBG_TDO" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
949 <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="249" MSB="0" NAME="DBG_REG_EN" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
950 <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="I" MPD_INDEX="250" NAME="DBG_SHIFT" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
951 <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="I" MPD_INDEX="251" NAME="DBG_CAPTURE" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
952 <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="I" MPD_INDEX="252" NAME="DBG_UPDATE" SIGNAME="microblaze_0_debug_Dbg_Update"/>
953 <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="I" MPD_INDEX="253" NAME="DEBUG_RST" SIGIS="RST" SIGNAME="microblaze_0_debug_Debug_Rst"/>
954 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="254" MSB="0" NAME="Trace_Instruction" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
955 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="255" NAME="Trace_Valid_Instr" SIGNAME="__NOC__"/>
956 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="256" MSB="0" NAME="Trace_PC" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
957 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="257" NAME="Trace_Reg_Write" SIGNAME="__NOC__"/>
958 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="258" MSB="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
959 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="14" MPD_INDEX="259" MSB="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGNAME="__NOC__" VECFORMULA="[0:14]"/>
960 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="260" MSB="0" NAME="Trace_PID_Reg" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
961 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="261" MSB="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
962 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="262" NAME="Trace_Exception_Taken" SIGNAME="__NOC__"/>
963 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="263" MSB="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
964 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="Trace_Jump_Taken" SIGNAME="__NOC__"/>
965 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="265" NAME="Trace_Delay_Slot" SIGNAME="__NOC__"/>
966 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="266" MSB="0" NAME="Trace_Data_Address" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
967 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="267" NAME="Trace_Data_Access" SIGNAME="__NOC__"/>
968 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="268" NAME="Trace_Data_Read" SIGNAME="__NOC__"/>
969 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="269" NAME="Trace_Data_Write" SIGNAME="__NOC__"/>
970 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="270" MSB="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
971 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="271" MSB="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
972 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="272" NAME="Trace_DCache_Req" SIGNAME="__NOC__"/>
973 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="273" NAME="Trace_DCache_Hit" SIGNAME="__NOC__"/>
974 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="274" NAME="Trace_DCache_Rdy" SIGNAME="__NOC__"/>
975 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="275" NAME="Trace_DCache_Read" SIGNAME="__NOC__"/>
976 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="276" NAME="Trace_ICache_Req" SIGNAME="__NOC__"/>
977 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="277" NAME="Trace_ICache_Hit" SIGNAME="__NOC__"/>
978 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="278" NAME="Trace_ICache_Rdy" SIGNAME="__NOC__"/>
979 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="279" NAME="Trace_OF_PipeRun" SIGNAME="__NOC__"/>
980 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="280" NAME="Trace_EX_PipeRun" SIGNAME="__NOC__"/>
981 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="281" NAME="Trace_MEM_PipeRun" SIGNAME="__NOC__"/>
982 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="282" NAME="Trace_MB_Halted" SIGNAME="__NOC__"/>
983 <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="283" NAME="Trace_Jump_Hit" SIGNAME="__NOC__"/>
984 <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="284" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
985 <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="285" NAME="FSL0_S_READ" SIGNAME="__NOC__"/>
986 <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="286" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
987 <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="287" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/>
988 <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="288" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/>
989 <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="289" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
990 <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="290" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/>
991 <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="291" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
992 <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="292" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/>
993 <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="293" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/>
994 <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="294" NAME="FSL1_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
995 <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="295" NAME="FSL1_S_READ" SIGNAME="__NOC__"/>
996 <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="296" MSB="0" NAME="FSL1_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
997 <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="297" NAME="FSL1_S_CONTROL" SIGNAME="__NOC__"/>
998 <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="298" NAME="FSL1_S_EXISTS" SIGNAME="__NOC__"/>
999 <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="299" NAME="FSL1_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1000 <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="300" NAME="FSL1_M_WRITE" SIGNAME="__NOC__"/>
1001 <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="301" MSB="0" NAME="FSL1_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1002 <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="302" NAME="FSL1_M_CONTROL" SIGNAME="__NOC__"/>
1003 <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="303" NAME="FSL1_M_FULL" SIGNAME="__NOC__"/>
1004 <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="304" NAME="FSL2_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1005 <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="305" NAME="FSL2_S_READ" SIGNAME="__NOC__"/>
1006 <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="306" MSB="0" NAME="FSL2_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1007 <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="307" NAME="FSL2_S_CONTROL" SIGNAME="__NOC__"/>
1008 <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="308" NAME="FSL2_S_EXISTS" SIGNAME="__NOC__"/>
1009 <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="309" NAME="FSL2_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1010 <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="310" NAME="FSL2_M_WRITE" SIGNAME="__NOC__"/>
1011 <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="311" MSB="0" NAME="FSL2_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1012 <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="FSL2_M_CONTROL" SIGNAME="__NOC__"/>
1013 <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="313" NAME="FSL2_M_FULL" SIGNAME="__NOC__"/>
1014 <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="314" NAME="FSL3_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1015 <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="315" NAME="FSL3_S_READ" SIGNAME="__NOC__"/>
1016 <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="316" MSB="0" NAME="FSL3_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1017 <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="317" NAME="FSL3_S_CONTROL" SIGNAME="__NOC__"/>
1018 <PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="318" NAME="FSL3_S_EXISTS" SIGNAME="__NOC__"/>
1019 <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="319" NAME="FSL3_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1020 <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="320" NAME="FSL3_M_WRITE" SIGNAME="__NOC__"/>
1021 <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="321" MSB="0" NAME="FSL3_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1022 <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="322" NAME="FSL3_M_CONTROL" SIGNAME="__NOC__"/>
1023 <PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="323" NAME="FSL3_M_FULL" SIGNAME="__NOC__"/>
1024 <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="324" NAME="FSL4_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1025 <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="325" NAME="FSL4_S_READ" SIGNAME="__NOC__"/>
1026 <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="326" MSB="0" NAME="FSL4_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1027 <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="327" NAME="FSL4_S_CONTROL" SIGNAME="__NOC__"/>
1028 <PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="328" NAME="FSL4_S_EXISTS" SIGNAME="__NOC__"/>
1029 <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="329" NAME="FSL4_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1030 <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="330" NAME="FSL4_M_WRITE" SIGNAME="__NOC__"/>
1031 <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="331" MSB="0" NAME="FSL4_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1032 <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="332" NAME="FSL4_M_CONTROL" SIGNAME="__NOC__"/>
1033 <PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="333" NAME="FSL4_M_FULL" SIGNAME="__NOC__"/>
1034 <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="334" NAME="FSL5_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1035 <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="335" NAME="FSL5_S_READ" SIGNAME="__NOC__"/>
1036 <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="336" MSB="0" NAME="FSL5_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1037 <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="337" NAME="FSL5_S_CONTROL" SIGNAME="__NOC__"/>
1038 <PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="338" NAME="FSL5_S_EXISTS" SIGNAME="__NOC__"/>
1039 <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="339" NAME="FSL5_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1040 <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="340" NAME="FSL5_M_WRITE" SIGNAME="__NOC__"/>
1041 <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="341" MSB="0" NAME="FSL5_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1042 <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="342" NAME="FSL5_M_CONTROL" SIGNAME="__NOC__"/>
1043 <PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="343" NAME="FSL5_M_FULL" SIGNAME="__NOC__"/>
1044 <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="344" NAME="FSL6_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1045 <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="345" NAME="FSL6_S_READ" SIGNAME="__NOC__"/>
1046 <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="346" MSB="0" NAME="FSL6_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1047 <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="347" NAME="FSL6_S_CONTROL" SIGNAME="__NOC__"/>
1048 <PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="348" NAME="FSL6_S_EXISTS" SIGNAME="__NOC__"/>
1049 <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="349" NAME="FSL6_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1050 <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="350" NAME="FSL6_M_WRITE" SIGNAME="__NOC__"/>
1051 <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="351" MSB="0" NAME="FSL6_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1052 <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="352" NAME="FSL6_M_CONTROL" SIGNAME="__NOC__"/>
1053 <PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="353" NAME="FSL6_M_FULL" SIGNAME="__NOC__"/>
1054 <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="354" NAME="FSL7_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1055 <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="355" NAME="FSL7_S_READ" SIGNAME="__NOC__"/>
1056 <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="356" MSB="0" NAME="FSL7_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1057 <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="357" NAME="FSL7_S_CONTROL" SIGNAME="__NOC__"/>
1058 <PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="358" NAME="FSL7_S_EXISTS" SIGNAME="__NOC__"/>
1059 <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="359" NAME="FSL7_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1060 <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="360" NAME="FSL7_M_WRITE" SIGNAME="__NOC__"/>
1061 <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="361" MSB="0" NAME="FSL7_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1062 <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="362" NAME="FSL7_M_CONTROL" SIGNAME="__NOC__"/>
1063 <PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="363" NAME="FSL7_M_FULL" SIGNAME="__NOC__"/>
1064 <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="364" NAME="FSL8_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1065 <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="365" NAME="FSL8_S_READ" SIGNAME="__NOC__"/>
1066 <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="366" MSB="0" NAME="FSL8_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1067 <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="367" NAME="FSL8_S_CONTROL" SIGNAME="__NOC__"/>
1068 <PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="368" NAME="FSL8_S_EXISTS" SIGNAME="__NOC__"/>
1069 <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="369" NAME="FSL8_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1070 <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="370" NAME="FSL8_M_WRITE" SIGNAME="__NOC__"/>
1071 <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="371" MSB="0" NAME="FSL8_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1072 <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="372" NAME="FSL8_M_CONTROL" SIGNAME="__NOC__"/>
1073 <PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="373" NAME="FSL8_M_FULL" SIGNAME="__NOC__"/>
1074 <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="374" NAME="FSL9_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1075 <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="375" NAME="FSL9_S_READ" SIGNAME="__NOC__"/>
1076 <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="376" MSB="0" NAME="FSL9_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1077 <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="377" NAME="FSL9_S_CONTROL" SIGNAME="__NOC__"/>
1078 <PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="378" NAME="FSL9_S_EXISTS" SIGNAME="__NOC__"/>
1079 <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="379" NAME="FSL9_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1080 <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="380" NAME="FSL9_M_WRITE" SIGNAME="__NOC__"/>
1081 <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="381" MSB="0" NAME="FSL9_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1082 <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="382" NAME="FSL9_M_CONTROL" SIGNAME="__NOC__"/>
1083 <PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="383" NAME="FSL9_M_FULL" SIGNAME="__NOC__"/>
1084 <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="384" NAME="FSL10_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1085 <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="385" NAME="FSL10_S_READ" SIGNAME="__NOC__"/>
1086 <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="386" MSB="0" NAME="FSL10_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1087 <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="387" NAME="FSL10_S_CONTROL" SIGNAME="__NOC__"/>
1088 <PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="388" NAME="FSL10_S_EXISTS" SIGNAME="__NOC__"/>
1089 <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="389" NAME="FSL10_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1090 <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="390" NAME="FSL10_M_WRITE" SIGNAME="__NOC__"/>
1091 <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="391" MSB="0" NAME="FSL10_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1092 <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="392" NAME="FSL10_M_CONTROL" SIGNAME="__NOC__"/>
1093 <PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="393" NAME="FSL10_M_FULL" SIGNAME="__NOC__"/>
1094 <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="394" NAME="FSL11_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1095 <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="395" NAME="FSL11_S_READ" SIGNAME="__NOC__"/>
1096 <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="396" MSB="0" NAME="FSL11_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1097 <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="397" NAME="FSL11_S_CONTROL" SIGNAME="__NOC__"/>
1098 <PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="398" NAME="FSL11_S_EXISTS" SIGNAME="__NOC__"/>
1099 <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="399" NAME="FSL11_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1100 <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="400" NAME="FSL11_M_WRITE" SIGNAME="__NOC__"/>
1101 <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="401" MSB="0" NAME="FSL11_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1102 <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="402" NAME="FSL11_M_CONTROL" SIGNAME="__NOC__"/>
1103 <PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="403" NAME="FSL11_M_FULL" SIGNAME="__NOC__"/>
1104 <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="404" NAME="FSL12_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1105 <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="405" NAME="FSL12_S_READ" SIGNAME="__NOC__"/>
1106 <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="406" MSB="0" NAME="FSL12_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1107 <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="407" NAME="FSL12_S_CONTROL" SIGNAME="__NOC__"/>
1108 <PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="408" NAME="FSL12_S_EXISTS" SIGNAME="__NOC__"/>
1109 <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="409" NAME="FSL12_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1110 <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="410" NAME="FSL12_M_WRITE" SIGNAME="__NOC__"/>
1111 <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="411" MSB="0" NAME="FSL12_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1112 <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="412" NAME="FSL12_M_CONTROL" SIGNAME="__NOC__"/>
1113 <PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="413" NAME="FSL12_M_FULL" SIGNAME="__NOC__"/>
1114 <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="414" NAME="FSL13_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1115 <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="415" NAME="FSL13_S_READ" SIGNAME="__NOC__"/>
1116 <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="416" MSB="0" NAME="FSL13_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1117 <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="417" NAME="FSL13_S_CONTROL" SIGNAME="__NOC__"/>
1118 <PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="418" NAME="FSL13_S_EXISTS" SIGNAME="__NOC__"/>
1119 <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="419" NAME="FSL13_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1120 <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="420" NAME="FSL13_M_WRITE" SIGNAME="__NOC__"/>
1121 <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="421" MSB="0" NAME="FSL13_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1122 <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="422" NAME="FSL13_M_CONTROL" SIGNAME="__NOC__"/>
1123 <PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="423" NAME="FSL13_M_FULL" SIGNAME="__NOC__"/>
1124 <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="424" NAME="FSL14_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1125 <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="425" NAME="FSL14_S_READ" SIGNAME="__NOC__"/>
1126 <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="426" MSB="0" NAME="FSL14_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1127 <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="427" NAME="FSL14_S_CONTROL" SIGNAME="__NOC__"/>
1128 <PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="428" NAME="FSL14_S_EXISTS" SIGNAME="__NOC__"/>
1129 <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="429" NAME="FSL14_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1130 <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="430" NAME="FSL14_M_WRITE" SIGNAME="__NOC__"/>
1131 <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="431" MSB="0" NAME="FSL14_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1132 <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="432" NAME="FSL14_M_CONTROL" SIGNAME="__NOC__"/>
1133 <PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="433" NAME="FSL14_M_FULL" SIGNAME="__NOC__"/>
1134 <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="434" NAME="FSL15_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1135 <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="435" NAME="FSL15_S_READ" SIGNAME="__NOC__"/>
1136 <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="436" MSB="0" NAME="FSL15_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1137 <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="437" NAME="FSL15_S_CONTROL" SIGNAME="__NOC__"/>
1138 <PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="438" NAME="FSL15_S_EXISTS" SIGNAME="__NOC__"/>
1139 <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="439" NAME="FSL15_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1140 <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="440" NAME="FSL15_M_WRITE" SIGNAME="__NOC__"/>
1141 <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="441" MSB="0" NAME="FSL15_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
1142 <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="442" NAME="FSL15_M_CONTROL" SIGNAME="__NOC__"/>
1143 <PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="443" NAME="FSL15_M_FULL" SIGNAME="__NOC__"/>
1144 <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="444" NAME="M0_AXIS_TLAST" SIGNAME="__NOC__"/>
1145 <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="445" MSB="31" NAME="M0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M0_AXIS_DATA_WIDTH-1:0]"/>
1146 <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="446" NAME="M0_AXIS_TVALID" SIGNAME="__NOC__"/>
1147 <PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="447" NAME="M0_AXIS_TREADY" SIGNAME="__NOC__"/>
1148 <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="448" NAME="S0_AXIS_TLAST" SIGNAME="__NOC__"/>
1149 <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="449" MSB="31" NAME="S0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S0_AXIS_DATA_WIDTH-1:0]"/>
1150 <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="450" NAME="S0_AXIS_TVALID" SIGNAME="__NOC__"/>
1151 <PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="451" NAME="S0_AXIS_TREADY" SIGNAME="__NOC__"/>
1152 <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="452" NAME="M1_AXIS_TLAST" SIGNAME="__NOC__"/>
1153 <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="453" MSB="31" NAME="M1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M1_AXIS_DATA_WIDTH-1:0]"/>
1154 <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="454" NAME="M1_AXIS_TVALID" SIGNAME="__NOC__"/>
1155 <PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="455" NAME="M1_AXIS_TREADY" SIGNAME="__NOC__"/>
1156 <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="456" NAME="S1_AXIS_TLAST" SIGNAME="__NOC__"/>
1157 <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="457" MSB="31" NAME="S1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S1_AXIS_DATA_WIDTH-1:0]"/>
1158 <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="458" NAME="S1_AXIS_TVALID" SIGNAME="__NOC__"/>
1159 <PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="459" NAME="S1_AXIS_TREADY" SIGNAME="__NOC__"/>
1160 <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="460" NAME="M2_AXIS_TLAST" SIGNAME="__NOC__"/>
1161 <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="461" MSB="31" NAME="M2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M2_AXIS_DATA_WIDTH-1:0]"/>
1162 <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="462" NAME="M2_AXIS_TVALID" SIGNAME="__NOC__"/>
1163 <PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="463" NAME="M2_AXIS_TREADY" SIGNAME="__NOC__"/>
1164 <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="464" NAME="S2_AXIS_TLAST" SIGNAME="__NOC__"/>
1165 <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="465" MSB="31" NAME="S2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S2_AXIS_DATA_WIDTH-1:0]"/>
1166 <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="466" NAME="S2_AXIS_TVALID" SIGNAME="__NOC__"/>
1167 <PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="467" NAME="S2_AXIS_TREADY" SIGNAME="__NOC__"/>
1168 <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="468" NAME="M3_AXIS_TLAST" SIGNAME="__NOC__"/>
1169 <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="469" MSB="31" NAME="M3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M3_AXIS_DATA_WIDTH-1:0]"/>
1170 <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="470" NAME="M3_AXIS_TVALID" SIGNAME="__NOC__"/>
1171 <PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="471" NAME="M3_AXIS_TREADY" SIGNAME="__NOC__"/>
1172 <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="472" NAME="S3_AXIS_TLAST" SIGNAME="__NOC__"/>
1173 <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="473" MSB="31" NAME="S3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S3_AXIS_DATA_WIDTH-1:0]"/>
1174 <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="474" NAME="S3_AXIS_TVALID" SIGNAME="__NOC__"/>
1175 <PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="475" NAME="S3_AXIS_TREADY" SIGNAME="__NOC__"/>
1176 <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="476" NAME="M4_AXIS_TLAST" SIGNAME="__NOC__"/>
1177 <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="477" MSB="31" NAME="M4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M4_AXIS_DATA_WIDTH-1:0]"/>
1178 <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="478" NAME="M4_AXIS_TVALID" SIGNAME="__NOC__"/>
1179 <PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="479" NAME="M4_AXIS_TREADY" SIGNAME="__NOC__"/>
1180 <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="480" NAME="S4_AXIS_TLAST" SIGNAME="__NOC__"/>
1181 <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="481" MSB="31" NAME="S4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S4_AXIS_DATA_WIDTH-1:0]"/>
1182 <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="482" NAME="S4_AXIS_TVALID" SIGNAME="__NOC__"/>
1183 <PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="483" NAME="S4_AXIS_TREADY" SIGNAME="__NOC__"/>
1184 <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="484" NAME="M5_AXIS_TLAST" SIGNAME="__NOC__"/>
1185 <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="485" MSB="31" NAME="M5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M5_AXIS_DATA_WIDTH-1:0]"/>
1186 <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="486" NAME="M5_AXIS_TVALID" SIGNAME="__NOC__"/>
1187 <PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="487" NAME="M5_AXIS_TREADY" SIGNAME="__NOC__"/>
1188 <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="488" NAME="S5_AXIS_TLAST" SIGNAME="__NOC__"/>
1189 <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="489" MSB="31" NAME="S5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S5_AXIS_DATA_WIDTH-1:0]"/>
1190 <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="490" NAME="S5_AXIS_TVALID" SIGNAME="__NOC__"/>
1191 <PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="491" NAME="S5_AXIS_TREADY" SIGNAME="__NOC__"/>
1192 <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="492" NAME="M6_AXIS_TLAST" SIGNAME="__NOC__"/>
1193 <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="493" MSB="31" NAME="M6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M6_AXIS_DATA_WIDTH-1:0]"/>
1194 <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="494" NAME="M6_AXIS_TVALID" SIGNAME="__NOC__"/>
1195 <PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="495" NAME="M6_AXIS_TREADY" SIGNAME="__NOC__"/>
1196 <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="496" NAME="S6_AXIS_TLAST" SIGNAME="__NOC__"/>
1197 <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="497" MSB="31" NAME="S6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S6_AXIS_DATA_WIDTH-1:0]"/>
1198 <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="498" NAME="S6_AXIS_TVALID" SIGNAME="__NOC__"/>
1199 <PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="499" NAME="S6_AXIS_TREADY" SIGNAME="__NOC__"/>
1200 <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="500" NAME="M7_AXIS_TLAST" SIGNAME="__NOC__"/>
1201 <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="501" MSB="31" NAME="M7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M7_AXIS_DATA_WIDTH-1:0]"/>
1202 <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="502" NAME="M7_AXIS_TVALID" SIGNAME="__NOC__"/>
1203 <PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="503" NAME="M7_AXIS_TREADY" SIGNAME="__NOC__"/>
1204 <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="504" NAME="S7_AXIS_TLAST" SIGNAME="__NOC__"/>
1205 <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="505" MSB="31" NAME="S7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S7_AXIS_DATA_WIDTH-1:0]"/>
1206 <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="506" NAME="S7_AXIS_TVALID" SIGNAME="__NOC__"/>
1207 <PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="507" NAME="S7_AXIS_TREADY" SIGNAME="__NOC__"/>
1208 <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="508" NAME="M8_AXIS_TLAST" SIGNAME="__NOC__"/>
1209 <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="509" MSB="31" NAME="M8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M8_AXIS_DATA_WIDTH-1:0]"/>
1210 <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="510" NAME="M8_AXIS_TVALID" SIGNAME="__NOC__"/>
1211 <PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="511" NAME="M8_AXIS_TREADY" SIGNAME="__NOC__"/>
1212 <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="512" NAME="S8_AXIS_TLAST" SIGNAME="__NOC__"/>
1213 <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="513" MSB="31" NAME="S8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S8_AXIS_DATA_WIDTH-1:0]"/>
1214 <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="514" NAME="S8_AXIS_TVALID" SIGNAME="__NOC__"/>
1215 <PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="515" NAME="S8_AXIS_TREADY" SIGNAME="__NOC__"/>
1216 <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="516" NAME="M9_AXIS_TLAST" SIGNAME="__NOC__"/>
1217 <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="517" MSB="31" NAME="M9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M9_AXIS_DATA_WIDTH-1:0]"/>
1218 <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="518" NAME="M9_AXIS_TVALID" SIGNAME="__NOC__"/>
1219 <PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="519" NAME="M9_AXIS_TREADY" SIGNAME="__NOC__"/>
1220 <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="520" NAME="S9_AXIS_TLAST" SIGNAME="__NOC__"/>
1221 <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="521" MSB="31" NAME="S9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S9_AXIS_DATA_WIDTH-1:0]"/>
1222 <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="522" NAME="S9_AXIS_TVALID" SIGNAME="__NOC__"/>
1223 <PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="523" NAME="S9_AXIS_TREADY" SIGNAME="__NOC__"/>
1224 <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="524" NAME="M10_AXIS_TLAST" SIGNAME="__NOC__"/>
1225 <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="525" MSB="31" NAME="M10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M10_AXIS_DATA_WIDTH-1:0]"/>
1226 <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="526" NAME="M10_AXIS_TVALID" SIGNAME="__NOC__"/>
1227 <PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="527" NAME="M10_AXIS_TREADY" SIGNAME="__NOC__"/>
1228 <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="528" NAME="S10_AXIS_TLAST" SIGNAME="__NOC__"/>
1229 <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="529" MSB="31" NAME="S10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S10_AXIS_DATA_WIDTH-1:0]"/>
1230 <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="530" NAME="S10_AXIS_TVALID" SIGNAME="__NOC__"/>
1231 <PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="531" NAME="S10_AXIS_TREADY" SIGNAME="__NOC__"/>
1232 <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="532" NAME="M11_AXIS_TLAST" SIGNAME="__NOC__"/>
1233 <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="533" MSB="31" NAME="M11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M11_AXIS_DATA_WIDTH-1:0]"/>
1234 <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="534" NAME="M11_AXIS_TVALID" SIGNAME="__NOC__"/>
1235 <PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="535" NAME="M11_AXIS_TREADY" SIGNAME="__NOC__"/>
1236 <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="536" NAME="S11_AXIS_TLAST" SIGNAME="__NOC__"/>
1237 <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="537" MSB="31" NAME="S11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S11_AXIS_DATA_WIDTH-1:0]"/>
1238 <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="538" NAME="S11_AXIS_TVALID" SIGNAME="__NOC__"/>
1239 <PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="539" NAME="S11_AXIS_TREADY" SIGNAME="__NOC__"/>
1240 <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="540" NAME="M12_AXIS_TLAST" SIGNAME="__NOC__"/>
1241 <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="541" MSB="31" NAME="M12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M12_AXIS_DATA_WIDTH-1:0]"/>
1242 <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="542" NAME="M12_AXIS_TVALID" SIGNAME="__NOC__"/>
1243 <PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="543" NAME="M12_AXIS_TREADY" SIGNAME="__NOC__"/>
1244 <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="544" NAME="S12_AXIS_TLAST" SIGNAME="__NOC__"/>
1245 <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="545" MSB="31" NAME="S12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S12_AXIS_DATA_WIDTH-1:0]"/>
1246 <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="546" NAME="S12_AXIS_TVALID" SIGNAME="__NOC__"/>
1247 <PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="547" NAME="S12_AXIS_TREADY" SIGNAME="__NOC__"/>
1248 <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="548" NAME="M13_AXIS_TLAST" SIGNAME="__NOC__"/>
1249 <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="549" MSB="31" NAME="M13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M13_AXIS_DATA_WIDTH-1:0]"/>
1250 <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="550" NAME="M13_AXIS_TVALID" SIGNAME="__NOC__"/>
1251 <PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="551" NAME="M13_AXIS_TREADY" SIGNAME="__NOC__"/>
1252 <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="552" NAME="S13_AXIS_TLAST" SIGNAME="__NOC__"/>
1253 <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="553" MSB="31" NAME="S13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S13_AXIS_DATA_WIDTH-1:0]"/>
1254 <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="554" NAME="S13_AXIS_TVALID" SIGNAME="__NOC__"/>
1255 <PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="555" NAME="S13_AXIS_TREADY" SIGNAME="__NOC__"/>
1256 <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="556" NAME="M14_AXIS_TLAST" SIGNAME="__NOC__"/>
1257 <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="557" MSB="31" NAME="M14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M14_AXIS_DATA_WIDTH-1:0]"/>
1258 <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="558" NAME="M14_AXIS_TVALID" SIGNAME="__NOC__"/>
1259 <PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="559" NAME="M14_AXIS_TREADY" SIGNAME="__NOC__"/>
1260 <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="560" NAME="S14_AXIS_TLAST" SIGNAME="__NOC__"/>
1261 <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="561" MSB="31" NAME="S14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S14_AXIS_DATA_WIDTH-1:0]"/>
1262 <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="562" NAME="S14_AXIS_TVALID" SIGNAME="__NOC__"/>
1263 <PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="563" NAME="S14_AXIS_TREADY" SIGNAME="__NOC__"/>
1264 <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="564" NAME="M15_AXIS_TLAST" SIGNAME="__NOC__"/>
1265 <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="565" MSB="31" NAME="M15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M15_AXIS_DATA_WIDTH-1:0]"/>
1266 <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="566" NAME="M15_AXIS_TVALID" SIGNAME="__NOC__"/>
1267 <PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="567" NAME="M15_AXIS_TREADY" SIGNAME="__NOC__"/>
1268 <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="568" NAME="S15_AXIS_TLAST" SIGNAME="__NOC__"/>
1269 <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="569" MSB="31" NAME="S15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S15_AXIS_DATA_WIDTH-1:0]"/>
1270 <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="570" NAME="S15_AXIS_TVALID" SIGNAME="__NOC__"/>
1271 <PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="571" NAME="S15_AXIS_TREADY" SIGNAME="__NOC__"/>
1272 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="572" NAME="ICACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1273 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="573" NAME="ICACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
1274 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="574" MSB="0" NAME="ICACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1275 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="575" NAME="ICACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
1276 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="576" NAME="ICACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
1277 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="577" NAME="ICACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1278 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="578" NAME="ICACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
1279 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="579" MSB="0" NAME="ICACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1280 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="580" NAME="ICACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
1281 <PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="581" NAME="ICACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
1282 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="582" NAME="DCACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1283 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="583" NAME="DCACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
1284 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="584" MSB="0" NAME="DCACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1285 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="585" NAME="DCACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
1286 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="586" NAME="DCACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
1287 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="587" NAME="DCACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
1288 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="588" NAME="DCACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
1289 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="589" MSB="0" NAME="DCACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
1290 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="590" NAME="DCACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
1291 <PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="591" NAME="DCACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
1294 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER">
1296 <PORTMAP DIR="I" PHYSICAL="CLK"/>
1297 <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABort"/>
1298 <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABus"/>
1299 <PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/>
1300 <PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/>
1301 <PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/>
1302 <PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/>
1303 <PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/>
1304 <PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/>
1305 <PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/>
1306 <PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/>
1307 <PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/>
1308 <PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/>
1309 <PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/>
1310 <PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/>
1311 <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/>
1312 <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/>
1313 <PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/>
1314 <PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/>
1315 <PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/>
1316 <PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/>
1317 <PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/>
1318 <PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/>
1319 <PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/>
1320 <PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/>
1321 <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/>
1322 <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/>
1323 <PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/>
1324 <PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/>
1325 <PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/>
1326 <PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/>
1329 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER">
1331 <PORTMAP DIR="I" PHYSICAL="CLK"/>
1332 <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/>
1333 <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/>
1334 <PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/>
1335 <PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/>
1336 <PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/>
1337 <PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/>
1338 <PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/>
1339 <PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/>
1340 <PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/>
1341 <PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/>
1342 <PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/>
1343 <PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/>
1344 <PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/>
1345 <PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/>
1346 <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/>
1347 <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/>
1348 <PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/>
1349 <PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/>
1350 <PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/>
1351 <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
1352 <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
1353 <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
1354 <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
1355 <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
1356 <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
1357 <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
1358 <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
1359 <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
1360 <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
1361 <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
1364 <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER">
1366 <PORTMAP DIR="I" PHYSICAL="CLK"/>
1367 <PORTMAP DIR="I" PHYSICAL="RESET"/>
1368 <PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
1369 <PORTMAP DIR="I" PHYSICAL="DREADY"/>
1370 <PORTMAP DIR="I" PHYSICAL="DWAIT"/>
1371 <PORTMAP DIR="I" PHYSICAL="DCE"/>
1372 <PORTMAP DIR="I" PHYSICAL="DUE"/>
1373 <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
1374 <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
1375 <PORTMAP DIR="O" PHYSICAL="D_AS"/>
1376 <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
1377 <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
1378 <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
1381 <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
1383 <PORTMAP DIR="I" PHYSICAL="CLK"/>
1384 <PORTMAP DIR="I" PHYSICAL="RESET"/>
1385 <PORTMAP DIR="I" PHYSICAL="INSTR"/>
1386 <PORTMAP DIR="I" PHYSICAL="IREADY"/>
1387 <PORTMAP DIR="I" PHYSICAL="IWAIT"/>
1388 <PORTMAP DIR="I" PHYSICAL="ICE"/>
1389 <PORTMAP DIR="I" PHYSICAL="IUE"/>
1390 <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
1391 <PORTMAP DIR="O" PHYSICAL="IFETCH"/>
1392 <PORTMAP DIR="O" PHYSICAL="I_AS"/>
1395 <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
1397 <PORTMAP DIR="I" PHYSICAL="CLK"/>
1398 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
1399 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
1400 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
1401 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
1402 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
1403 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
1404 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
1405 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
1406 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
1407 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
1408 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
1409 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
1410 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
1411 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
1412 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
1413 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
1414 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
1415 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
1416 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
1417 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
1418 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
1419 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
1420 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
1421 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
1422 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
1423 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
1424 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
1425 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
1426 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
1427 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
1428 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
1429 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
1430 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
1431 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
1432 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
1433 <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
1434 <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
1437 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
1439 <PORTMAP DIR="I" PHYSICAL="CLK"/>
1440 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
1441 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
1442 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
1443 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
1444 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
1445 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
1446 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
1447 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
1448 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
1449 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
1450 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
1451 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
1452 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
1453 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
1454 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
1455 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
1456 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
1457 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
1458 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
1459 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
1460 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
1461 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
1462 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
1463 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
1464 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
1465 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
1466 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
1467 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
1468 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
1469 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
1470 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
1471 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
1472 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
1473 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
1474 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
1475 <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
1476 <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
1479 <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
1481 <PORTMAP DIR="I" PHYSICAL="CLK"/>
1482 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
1483 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
1484 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
1485 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
1486 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
1487 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
1488 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
1489 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
1490 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
1491 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
1492 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
1493 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
1494 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
1495 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
1496 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
1497 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
1498 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
1499 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
1500 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
1501 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
1502 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
1503 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
1504 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
1505 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
1506 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
1507 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
1508 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
1509 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
1510 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
1511 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
1512 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
1513 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
1514 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
1515 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
1516 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
1517 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
1518 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
1519 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
1520 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
1521 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
1522 <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
1523 <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
1526 <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="4" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
1528 <PORTMAP DIR="I" PHYSICAL="CLK"/>
1529 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
1530 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
1531 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
1532 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
1533 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
1534 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
1535 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
1536 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
1537 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
1538 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
1539 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
1540 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
1541 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
1542 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
1543 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
1544 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
1545 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
1546 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
1547 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
1548 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
1549 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
1550 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
1551 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
1552 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
1553 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
1554 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
1555 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
1556 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
1557 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
1558 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
1559 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
1560 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
1561 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
1562 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
1563 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
1564 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
1565 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
1566 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
1567 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
1568 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
1569 <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
1570 <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
1573 <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
1575 <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
1576 <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
1577 <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
1578 <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
1579 <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
1580 <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
1581 <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
1582 <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
1585 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
1587 <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
1588 <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
1589 <PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
1590 <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
1591 <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
1592 <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
1593 <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
1594 <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
1595 <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
1596 <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
1597 <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
1598 <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
1599 <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
1600 <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
1601 <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
1602 <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
1603 <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
1604 <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
1605 <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
1606 <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
1607 <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
1608 <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
1609 <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
1610 <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
1611 <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
1612 <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
1613 <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
1614 <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
1615 <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
1616 <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
1619 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
1621 <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
1622 <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
1623 <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
1624 <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
1625 <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
1628 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
1630 <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
1631 <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
1632 <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
1633 <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
1634 <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
1637 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
1639 <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
1640 <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
1641 <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
1642 <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
1643 <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
1646 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
1648 <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
1649 <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
1650 <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
1651 <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
1652 <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
1655 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
1657 <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
1658 <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
1659 <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
1660 <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
1661 <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
1664 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
1666 <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
1667 <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
1668 <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
1669 <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
1670 <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
1673 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
1675 <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
1676 <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
1677 <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
1678 <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
1679 <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
1682 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
1684 <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
1685 <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
1686 <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
1687 <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
1688 <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
1691 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
1693 <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
1694 <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
1695 <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
1696 <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
1697 <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
1700 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
1702 <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
1703 <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
1704 <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
1705 <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
1706 <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
1709 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
1711 <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
1712 <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
1713 <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
1714 <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
1715 <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
1718 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
1720 <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
1721 <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
1722 <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
1723 <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
1724 <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
1727 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
1729 <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
1730 <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
1731 <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
1732 <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
1733 <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
1736 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
1738 <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
1739 <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
1740 <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
1741 <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
1742 <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
1745 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
1747 <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
1748 <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
1749 <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
1750 <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
1751 <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
1754 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
1756 <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
1757 <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
1758 <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
1759 <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
1760 <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
1763 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
1765 <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
1766 <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
1767 <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
1768 <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
1769 <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
1772 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
1774 <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
1775 <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
1776 <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
1777 <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
1778 <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
1781 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
1783 <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
1784 <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
1785 <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
1786 <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
1787 <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
1790 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
1792 <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
1793 <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
1794 <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
1795 <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
1796 <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
1799 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
1801 <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
1802 <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
1803 <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
1804 <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
1805 <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
1808 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
1810 <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
1811 <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
1812 <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
1813 <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
1814 <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
1817 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
1819 <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
1820 <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
1821 <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
1822 <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
1823 <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
1826 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
1828 <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
1829 <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
1830 <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
1831 <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
1832 <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
1835 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
1837 <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
1838 <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
1839 <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
1840 <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
1841 <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
1844 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
1846 <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
1847 <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
1848 <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
1849 <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
1850 <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
1853 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
1855 <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
1856 <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
1857 <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
1858 <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
1859 <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
1862 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
1864 <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
1865 <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
1866 <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
1867 <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
1868 <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
1871 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
1873 <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
1874 <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
1875 <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
1876 <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
1877 <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
1880 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
1882 <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
1883 <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
1884 <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
1885 <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
1886 <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
1889 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
1891 <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
1892 <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
1893 <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
1894 <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
1895 <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
1898 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
1900 <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
1901 <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
1902 <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
1903 <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
1904 <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
1907 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
1909 <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
1910 <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
1911 <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
1912 <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
1913 <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
1916 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
1918 <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
1919 <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
1920 <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
1921 <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
1922 <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
1925 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
1927 <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
1928 <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
1929 <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
1930 <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
1931 <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
1934 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
1936 <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
1937 <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
1938 <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
1939 <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
1940 <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
1943 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
1945 <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
1946 <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
1947 <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
1948 <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
1949 <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
1952 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
1954 <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
1955 <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
1956 <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
1957 <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
1958 <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
1961 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
1963 <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
1964 <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
1965 <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
1966 <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
1967 <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
1970 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
1972 <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
1973 <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
1974 <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
1975 <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
1976 <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
1979 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
1981 <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
1982 <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
1983 <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
1984 <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
1985 <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
1988 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
1990 <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
1991 <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
1992 <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
1993 <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
1994 <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
1997 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
1999 <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
2000 <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
2001 <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
2002 <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
2003 <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
2006 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
2008 <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
2009 <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
2010 <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
2011 <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
2012 <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
2015 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
2017 <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
2018 <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
2019 <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
2020 <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
2021 <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
2024 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
2026 <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
2027 <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
2028 <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
2029 <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
2030 <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
2033 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
2035 <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
2036 <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
2037 <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
2038 <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
2039 <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
2042 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
2044 <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
2045 <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
2046 <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
2047 <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
2048 <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
2051 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
2053 <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
2054 <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
2055 <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
2056 <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
2057 <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
2060 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
2062 <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
2063 <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
2064 <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
2065 <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
2066 <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
2069 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
2071 <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
2072 <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
2073 <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
2074 <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
2075 <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
2078 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
2080 <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
2081 <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
2082 <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
2083 <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
2084 <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
2087 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
2089 <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
2090 <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
2091 <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
2092 <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
2093 <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
2096 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
2098 <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
2099 <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
2100 <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
2101 <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
2102 <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
2105 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
2107 <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
2108 <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
2109 <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
2110 <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
2111 <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
2114 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
2116 <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
2117 <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
2118 <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
2119 <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
2120 <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
2123 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
2125 <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
2126 <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
2127 <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
2128 <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
2129 <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
2132 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
2134 <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
2135 <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
2136 <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
2137 <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
2138 <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
2141 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
2143 <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
2144 <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
2145 <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
2146 <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
2147 <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
2150 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
2152 <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
2153 <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
2154 <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
2155 <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
2156 <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
2159 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
2161 <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
2162 <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
2163 <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
2164 <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
2165 <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
2168 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
2170 <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
2171 <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
2172 <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
2173 <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
2174 <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
2177 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
2179 <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
2180 <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
2181 <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
2182 <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
2183 <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
2186 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
2188 <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
2189 <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
2190 <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
2191 <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
2192 <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
2195 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2197 <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
2198 <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
2199 <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
2200 <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
2203 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2205 <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
2206 <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
2207 <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
2208 <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
2211 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2213 <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
2214 <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
2215 <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
2216 <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
2219 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2221 <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
2222 <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
2223 <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
2224 <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
2227 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2229 <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
2230 <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
2231 <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
2232 <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
2235 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2237 <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
2238 <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
2239 <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
2240 <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
2243 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2245 <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
2246 <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
2247 <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
2248 <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
2251 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2253 <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
2254 <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
2255 <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
2256 <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
2259 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2261 <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
2262 <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
2263 <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
2264 <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
2267 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2269 <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
2270 <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
2271 <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
2272 <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
2275 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2277 <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
2278 <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
2279 <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
2280 <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
2283 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2285 <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
2286 <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
2287 <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
2288 <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
2291 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2293 <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
2294 <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
2295 <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
2296 <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
2299 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2301 <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
2302 <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
2303 <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
2304 <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
2307 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2309 <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
2310 <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
2311 <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
2312 <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
2315 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2317 <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
2318 <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
2319 <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
2320 <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
2323 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2325 <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
2326 <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
2327 <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
2328 <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
2331 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2333 <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
2334 <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
2335 <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
2336 <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
2339 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2341 <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
2342 <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
2343 <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
2344 <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
2347 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2349 <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
2350 <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
2351 <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
2352 <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
2355 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2357 <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
2358 <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
2359 <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
2360 <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
2363 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2365 <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
2366 <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
2367 <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
2368 <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
2371 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2373 <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
2374 <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
2375 <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
2376 <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
2379 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2381 <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
2382 <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
2383 <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
2384 <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
2387 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2389 <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
2390 <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
2391 <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
2392 <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
2395 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2397 <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
2398 <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
2399 <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
2400 <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
2403 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2405 <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
2406 <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
2407 <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
2408 <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
2411 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2413 <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
2414 <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
2415 <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
2416 <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
2419 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2421 <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
2422 <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
2423 <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
2424 <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
2427 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2429 <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
2430 <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
2431 <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
2432 <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
2435 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
2437 <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
2438 <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
2439 <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
2440 <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
2443 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
2445 <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
2446 <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
2447 <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
2448 <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
2451 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
2453 <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
2454 <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
2455 <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
2456 <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
2457 <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
2458 <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
2459 <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
2460 <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
2461 <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
2462 <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
2465 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
2467 <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
2468 <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
2469 <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
2470 <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
2471 <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
2472 <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
2473 <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
2474 <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
2475 <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
2476 <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
2480 <INTERRUPTINFO TYPE="TARGET">
2481 <SOURCE INSTANCE="microblaze_0_intc" INTC_INDEX="0"/>
2484 <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
2486 <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_dlmb"/>
2489 <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="microblaze_0_i_bram_ctrl" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
2491 <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_ilmb"/>
2494 <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" INSTANCE="debug_module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2496 <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2499 <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2501 <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2504 <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" INSTANCE="LEDs_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2506 <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2509 <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" INSTANCE="Push_Buttons_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2511 <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2514 <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" INSTANCE="Ethernet_Lite" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2516 <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2519 <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2521 <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2524 <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" INSTANCE="microblaze_0_intc" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
2526 <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
2529 <MEMRANGE BASEDECIMAL="3288334336" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xC4000000" HIGHDECIMAL="3288399871" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xC400FFFF" INSTANCE="axi_bram_ctrl_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="65536" SIZEABRV="64K">
2531 <ROUTEPNT INDEX="0" INSTANCE="axi4_0"/>
2536 <PERIPHERAL INSTANCE="microblaze_0_d_bram_ctrl"/>
2537 <PERIPHERAL INSTANCE="microblaze_0_i_bram_ctrl"/>
2538 <PERIPHERAL INSTANCE="debug_module"/>
2539 <PERIPHERAL INSTANCE="RS232_Uart_1"/>
2540 <PERIPHERAL INSTANCE="LEDs_4Bits"/>
2541 <PERIPHERAL INSTANCE="Push_Buttons_4Bits"/>
2542 <PERIPHERAL INSTANCE="Ethernet_Lite"/>
2543 <PERIPHERAL INSTANCE="axi_timer_0"/>
2544 <PERIPHERAL INSTANCE="microblaze_0_intc"/>
2545 <PERIPHERAL INSTANCE="axi_bram_ctrl_0"/>
2547 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
2549 <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
2550 <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
2551 <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
2553 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
2556 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
2557 <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
2558 <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
2559 <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/>
2562 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
2563 <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
2564 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
2565 <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
2566 <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_ilmb_M_ReadStrobe"/>
2567 <PORT DEF_SIGNAME="microblaze_0_ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_ilmb_M_WriteStrobe"/>
2568 <PORT DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_ilmb_M_AddrStrobe"/>
2569 <PORT DEF_SIGNAME="microblaze_0_ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2570 <PORT DEF_SIGNAME="microblaze_0_ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
2571 <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
2572 <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
2573 <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
2574 <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
2575 <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
2576 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
2577 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
2578 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
2579 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
2580 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2581 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2582 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_ilmb_LMB_Ready"/>
2583 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_ilmb_LMB_Wait"/>
2584 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_ilmb_LMB_UE"/>
2585 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_ilmb_LMB_CE"/>
2586 <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
2590 <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
2592 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
2594 <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.a" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="4" MODCLASS="BUS" MODTYPE="lmb_v10">
2595 <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
2596 <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
2598 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
2601 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
2602 <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
2603 <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
2604 <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/>
2607 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET"/>
2608 <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
2609 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
2610 <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
2611 <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_dlmb_M_ReadStrobe"/>
2612 <PORT DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_dlmb_M_WriteStrobe"/>
2613 <PORT DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_dlmb_M_AddrStrobe"/>
2614 <PORT DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2615 <PORT DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
2616 <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
2617 <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
2618 <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
2619 <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
2620 <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
2621 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
2622 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
2623 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
2624 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
2625 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2626 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2627 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_dlmb_LMB_Ready"/>
2628 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_dlmb_LMB_Wait"/>
2629 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_dlmb_LMB_UE"/>
2630 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_dlmb_LMB_CE"/>
2631 <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
2635 <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
2637 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
2639 <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
2640 <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
2641 <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
2643 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
2646 <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
2647 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
2648 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
2649 <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x00800000"/>
2650 <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
2651 <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
2652 <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0"/>
2653 <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"/>
2654 <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"/>
2655 <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
2656 <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
2657 <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"/>
2658 <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"/>
2659 <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"/>
2660 <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"/>
2661 <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"/>
2662 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
2663 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
2664 <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/>
2665 <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"/>
2666 <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"/>
2667 <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
2668 <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
2669 <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
2670 <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
2671 <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
2672 <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
2673 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
2674 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
2675 <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
2676 <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
2677 <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
2680 <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
2681 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst"/>
2682 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
2683 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2684 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe"/>
2685 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe"/>
2686 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe"/>
2687 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
2688 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2689 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready"/>
2690 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait"/>
2691 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE"/>
2692 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE"/>
2693 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
2694 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
2695 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
2696 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
2697 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
2698 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
2699 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
2700 <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
2701 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
2702 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
2703 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
2704 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
2705 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
2706 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
2707 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
2708 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
2709 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
2710 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2711 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
2712 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
2713 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
2714 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
2715 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
2716 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
2717 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
2718 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
2719 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
2720 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
2721 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
2722 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
2723 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
2724 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
2725 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
2726 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
2727 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2728 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
2729 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
2730 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
2731 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
2732 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
2733 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2734 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2735 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2736 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
2737 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
2738 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
2739 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
2740 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
2741 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
2742 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
2743 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
2744 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
2745 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
2746 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
2747 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
2748 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
2749 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
2750 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
2751 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
2752 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
2753 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
2754 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
2755 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
2756 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
2757 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
2758 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
2759 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
2762 <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
2764 <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
2765 <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
2766 <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
2767 <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
2768 <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
2769 <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
2770 <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
2771 <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
2772 <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
2773 <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
2774 <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
2775 <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
2776 <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
2779 <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
2781 <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
2782 <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
2783 <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
2784 <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
2785 <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
2786 <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
2787 <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
2790 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
2792 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
2793 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
2794 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
2795 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
2796 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
2797 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
2798 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
2799 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
2800 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
2801 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
2802 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
2803 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
2804 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
2805 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
2806 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
2807 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
2808 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
2809 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
2810 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
2811 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
2812 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
2813 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
2814 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
2815 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
2816 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
2817 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
2818 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
2819 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
2820 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
2821 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
2822 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
2823 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
2824 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
2825 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
2826 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
2827 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
2828 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
2829 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
2830 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
2831 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
2834 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
2836 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
2837 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
2838 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
2839 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
2840 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
2841 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
2842 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
2843 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
2844 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
2845 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
2846 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
2847 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
2848 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
2849 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
2850 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
2851 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
2852 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
2853 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
2854 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
2859 <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
2861 <SLAVE BUSINTERFACE="SLMB"/>
2864 <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
2866 <SLAVE BUSINTERFACE="SPLB_CTRL"/>
2869 <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
2871 <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
2875 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
2877 <MODULE HWVERSION="3.00.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
2878 <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
2879 <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
2881 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_a/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
2884 <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
2885 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff"/>
2886 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
2887 <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x00800000"/>
2888 <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
2889 <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
2890 <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0"/>
2891 <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"/>
2892 <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"/>
2893 <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
2894 <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
2895 <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"/>
2896 <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"/>
2897 <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"/>
2898 <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"/>
2899 <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"/>
2900 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
2901 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
2902 <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/>
2903 <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"/>
2904 <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"/>
2905 <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
2906 <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
2907 <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
2908 <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
2909 <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
2910 <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
2911 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
2912 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
2913 <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
2914 <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
2915 <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
2918 <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzPLL0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
2919 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst"/>
2920 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
2921 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2922 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe"/>
2923 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe"/>
2924 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe"/>
2925 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
2926 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
2927 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready"/>
2928 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait"/>
2929 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE"/>
2930 <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE"/>
2931 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
2932 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
2933 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
2934 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
2935 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
2936 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
2937 <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
2938 <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
2939 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
2940 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
2941 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
2942 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
2943 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
2944 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
2945 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
2946 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
2947 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
2948 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2949 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
2950 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
2951 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
2952 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
2953 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
2954 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
2955 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
2956 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
2957 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
2958 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
2959 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
2960 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
2961 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
2962 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
2963 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
2964 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
2965 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2966 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
2967 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
2968 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
2969 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
2970 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
2971 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2972 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2973 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
2974 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
2975 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
2976 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
2977 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
2978 <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
2979 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
2980 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
2981 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
2982 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
2983 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
2984 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
2985 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
2986 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
2987 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
2988 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
2989 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
2990 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
2991 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
2992 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
2993 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
2994 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
2995 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
2996 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
2997 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
3000 <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
3002 <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
3003 <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
3004 <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
3005 <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
3006 <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
3007 <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
3008 <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
3009 <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
3010 <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
3011 <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
3012 <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
3013 <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
3014 <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
3017 <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
3019 <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
3020 <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
3021 <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
3022 <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
3023 <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
3024 <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
3025 <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
3028 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
3030 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
3031 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
3032 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
3033 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
3034 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
3035 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
3036 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
3037 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
3038 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
3039 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
3040 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
3041 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
3042 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
3043 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
3044 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
3045 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
3046 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
3047 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
3048 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
3049 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
3050 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
3051 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
3052 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
3053 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
3054 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
3055 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
3056 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
3057 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
3058 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
3059 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
3060 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
3061 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
3062 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
3063 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
3064 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
3065 <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
3066 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
3067 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
3068 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
3069 <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
3072 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
3074 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
3075 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
3076 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
3077 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
3078 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
3079 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
3080 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
3081 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
3082 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
3083 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
3084 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
3085 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
3086 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
3087 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
3088 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
3089 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
3090 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
3091 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
3092 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
3097 <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
3099 <SLAVE BUSINTERFACE="SLMB"/>
3102 <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
3104 <SLAVE BUSINTERFACE="SPLB_CTRL"/>
3107 <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
3109 <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
3113 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3115 <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY" MODTYPE="bram_block">
3116 <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
3117 <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
3119 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
3122 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000"/>
3123 <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"/>
3124 <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32"/>
3125 <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4"/>
3126 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
3129 <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
3130 <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
3131 <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
3132 <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
3133 <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
3134 <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
3135 <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
3136 <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst"/>
3137 <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk"/>
3138 <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN"/>
3139 <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
3140 <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
3141 <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
3142 <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
3145 <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
3147 <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
3148 <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
3149 <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
3150 <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
3151 <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
3152 <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
3153 <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
3156 <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
3158 <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
3159 <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
3160 <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
3161 <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
3162 <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
3163 <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
3164 <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
3168 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3170 <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
3171 <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
3172 <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
3174 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
3177 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t"/>
3178 <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"/>
3179 <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4"/>
3180 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1"/>
3181 <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1"/>
3182 <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1"/>
3183 <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1"/>
3184 <PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1"/>
3185 <PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1"/>
3186 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6"/>
3189 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="RESET"/>
3190 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset"/>
3191 <PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
3192 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
3193 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
3194 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
3195 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="18" NAME="BUS_STRUCT_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
3196 <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
3197 <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
3198 <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
3199 <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
3200 <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
3201 <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
3202 <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
3203 <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
3204 <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
3205 <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
3206 <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
3207 <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
3208 <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
3209 <PORT DIR="O" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
3210 <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
3213 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
3215 <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
3216 <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
3217 <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
3218 <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
3219 <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
3220 <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
3223 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
3225 <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
3226 <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
3227 <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
3228 <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
3229 <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
3230 <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
3235 <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
3237 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3239 <MODULE HWVERSION="4.01.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="clock_generator">
3240 <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
3241 <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
3243 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_01_a/doc/clock_generator.pdf" TYPE="IP"/>
3246 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
3247 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t"/>
3248 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fgg484"/>
3249 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3"/>
3250 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000"/>
3251 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="600000000"/>
3252 <PARAMETER MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0"/>
3253 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0"/>
3254 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="FALSE"/>
3255 <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3256 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="600000000"/>
3257 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="180"/>
3258 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0"/>
3259 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="FALSE"/>
3260 <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3261 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="100000000"/>
3262 <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0"/>
3263 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0"/>
3264 <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3265 <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3266 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="50000000"/>
3267 <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0"/>
3268 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="PLL0"/>
3269 <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3270 <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3271 <PARAMETER MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0"/>
3272 <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0"/>
3273 <PARAMETER MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE"/>
3274 <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3275 <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3276 <PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0"/>
3277 <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0"/>
3278 <PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE"/>
3279 <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3280 <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3281 <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0"/>
3282 <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0"/>
3283 <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE"/>
3284 <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3285 <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3286 <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0"/>
3287 <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0"/>
3288 <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE"/>
3289 <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3290 <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3291 <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0"/>
3292 <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0"/>
3293 <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE"/>
3294 <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3295 <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3296 <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0"/>
3297 <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0"/>
3298 <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE"/>
3299 <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3300 <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3301 <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0"/>
3302 <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0"/>
3303 <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE"/>
3304 <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3305 <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3306 <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0"/>
3307 <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0"/>
3308 <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE"/>
3309 <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3310 <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3311 <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0"/>
3312 <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0"/>
3313 <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE"/>
3314 <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3315 <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3316 <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0"/>
3317 <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0"/>
3318 <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE"/>
3319 <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3320 <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3321 <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0"/>
3322 <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0"/>
3323 <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE"/>
3324 <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3325 <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3326 <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0"/>
3327 <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0"/>
3328 <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE"/>
3329 <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3330 <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
3331 <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0"/>
3332 <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE"/>
3333 <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0"/>
3334 <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0"/>
3335 <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE"/>
3336 <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
3337 <PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE"/>
3338 <PARAMETER MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
3339 <PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE"/>
3340 <PARAMETER MPD_INDEX="94" NAME="C_CLK_GEN" VALUE="UPDATE"/>
3343 <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="RESET"/>
3344 <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="CLK"/>
3345 <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
3346 <PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
3347 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="24" NAME="LOCKED" SIGNAME="proc_sys_reset_0_Dcm_locked"/>
3348 <PORT CLKFREQUENCY="600000000" DIR="O" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="__NOC__"/>
3349 <PORT CLKFREQUENCY="600000000" DIR="O" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="__NOC__"/>
3350 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
3351 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
3352 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
3353 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
3354 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
3355 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
3356 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
3357 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
3358 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
3359 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
3360 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
3361 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
3362 <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
3363 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
3364 <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
3365 <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
3366 <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
3367 <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
3370 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3372 <MODULE HWVERSION="2.00.b" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="DEBUG" MODTYPE="mdm">
3373 <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
3374 <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
3376 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
3379 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
3380 <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2"/>
3381 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2"/>
3382 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x74800000"/>
3383 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x7480ffff"/>
3384 <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/>
3385 <PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"/>
3386 <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/>
3387 <PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3"/>
3388 <PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8"/>
3389 <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
3390 <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
3391 <PARAMETER MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1"/>
3392 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1"/>
3393 <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
3394 <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
3395 <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
3396 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
3397 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
3398 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
3399 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
3400 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
3403 <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
3404 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst"/>
3405 <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
3406 <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/>
3407 <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/>
3408 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
3409 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
3410 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
3411 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
3412 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
3413 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/>
3414 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
3415 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
3416 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
3417 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
3418 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
3419 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
3420 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
3421 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
3422 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
3423 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
3424 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
3425 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
3426 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
3427 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
3428 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
3429 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
3430 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/>
3431 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/>
3432 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/>
3433 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/>
3434 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
3435 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="__NOC__"/>
3436 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/>
3437 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/>
3438 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
3439 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3440 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
3441 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
3442 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="__NOC__"/>
3443 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
3444 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="__NOC__"/>
3445 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="__NOC__"/>
3446 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="__NOC__"/>
3447 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="__NOC__"/>
3448 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3449 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3450 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3451 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
3452 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="__NOC__"/>
3453 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
3454 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="__NOC__"/>
3455 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="__NOC__"/>
3456 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="__NOC__"/>
3457 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="__NOC__"/>
3458 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="__NOC__"/>
3459 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
3460 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
3461 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="__NOC__"/>
3462 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="__NOC__"/>
3463 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="__NOC__"/>
3464 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
3465 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
3466 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
3467 <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
3468 <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_debug_Dbg_Clk"/>
3469 <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_debug_Dbg_TDI"/>
3470 <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_debug_Dbg_TDO"/>
3471 <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_debug_Dbg_Reg_En" VECFORMULA="[0:7]"/>
3472 <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_debug_Dbg_Capture"/>
3473 <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_debug_Dbg_Shift"/>
3474 <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_debug_Dbg_Update"/>
3475 <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_debug_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_debug_Debug_Rst"/>
3476 <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/>
3477 <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
3478 <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
3479 <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
3480 <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
3481 <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
3482 <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
3483 <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/>
3484 <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/>
3485 <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
3486 <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
3487 <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
3488 <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
3489 <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
3490 <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
3491 <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/>
3492 <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/>
3493 <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
3494 <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
3495 <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
3496 <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
3497 <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
3498 <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
3499 <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/>
3500 <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/>
3501 <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
3502 <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
3503 <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
3504 <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
3505 <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/>
3506 <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/>
3507 <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/>
3508 <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/>
3509 <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/>
3510 <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/>
3511 <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
3512 <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/>
3513 <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/>
3514 <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/>
3515 <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/>
3516 <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/>
3517 <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/>
3518 <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/>
3519 <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
3520 <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/>
3521 <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/>
3522 <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/>
3523 <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/>
3524 <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/>
3525 <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
3526 <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
3527 <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
3528 <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
3529 <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
3530 <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
3531 <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/>
3532 <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/>
3533 <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/>
3534 <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/>
3535 <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/>
3536 <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/>
3537 <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/>
3538 <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/>
3539 <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/>
3540 <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/>
3541 <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/>
3542 <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
3543 <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
3544 <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
3545 <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
3546 <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
3547 <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
3550 <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
3552 <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
3553 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
3554 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
3555 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
3556 <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
3557 <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
3558 <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
3559 <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
3560 <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
3561 <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
3562 <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
3563 <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
3564 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
3565 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
3566 <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
3567 <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
3568 <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
3569 <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
3570 <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
3573 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
3575 <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
3576 <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
3577 <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
3578 <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
3579 <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
3580 <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
3581 <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
3582 <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
3583 <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
3584 <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
3585 <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
3586 <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
3587 <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
3588 <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
3589 <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
3590 <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
3591 <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
3592 <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
3593 <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
3594 <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
3595 <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
3596 <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
3597 <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
3598 <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
3599 <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
3600 <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
3601 <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
3602 <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
3603 <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
3604 <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
3605 <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
3606 <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
3607 <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
3608 <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
3609 <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
3610 <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
3611 <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
3612 <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
3613 <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
3614 <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
3615 <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
3616 <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
3619 <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
3621 <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
3622 <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
3623 <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
3624 <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
3625 <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
3626 <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
3627 <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
3628 <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
3631 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
3633 <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
3634 <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
3635 <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
3636 <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
3637 <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
3638 <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
3639 <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
3640 <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
3643 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
3645 <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
3646 <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
3647 <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
3648 <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
3649 <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
3650 <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
3651 <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
3652 <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
3655 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
3657 <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
3658 <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
3659 <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
3660 <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
3661 <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
3662 <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
3663 <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
3664 <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
3667 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
3669 <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
3670 <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
3671 <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
3672 <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
3673 <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
3674 <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
3675 <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
3676 <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
3679 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
3681 <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
3682 <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
3683 <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
3684 <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
3685 <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
3686 <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
3687 <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
3688 <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
3691 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
3693 <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
3694 <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
3695 <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
3696 <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
3697 <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
3698 <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
3699 <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
3700 <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
3703 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
3705 <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
3706 <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
3707 <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
3708 <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
3709 <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
3710 <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
3711 <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
3712 <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
3715 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR">
3717 <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
3718 <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
3719 <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
3720 <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
3721 <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
3722 <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
3723 <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
3724 <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
3729 <MEMRANGE BASEDECIMAL="1954545664" BASENAME="C_BASEADDR" BASEVALUE="0x74800000" HIGHDECIMAL="1954611199" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7480ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
3731 <SLAVE BUSINTERFACE="SPLB"/>
3732 <SLAVE BUSINTERFACE="S_AXI"/>
3736 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3738 <MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
3739 <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
3740 <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
3742 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_01_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
3745 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
3746 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000"/>
3747 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40600000"/>
3748 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4060ffff"/>
3749 <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
3750 <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
3751 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="115200"/>
3752 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8"/>
3753 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="8" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0"/>
3754 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="9" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="1"/>
3755 <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
3756 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
3757 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
3758 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
3759 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
3760 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
3763 <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="21" NAME="TX" SIGNAME="RS232_Uart_1_sout">
3764 <DESCRIPTION>Serial Data Out</DESCRIPTION>
3766 <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="RX" SIGNAME="RS232_Uart_1_sin">
3767 <DESCRIPTION>Serial Data In</DESCRIPTION>
3769 <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
3770 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt"/>
3771 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
3772 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
3773 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
3774 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
3775 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
3776 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
3777 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
3778 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
3779 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
3780 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
3781 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
3782 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
3783 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
3784 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
3785 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
3786 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
3787 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
3788 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
3791 <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
3793 <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
3794 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
3795 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
3796 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
3797 <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
3798 <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
3799 <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
3800 <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
3801 <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
3802 <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
3803 <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
3804 <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
3805 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
3806 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
3807 <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
3808 <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
3809 <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
3810 <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
3811 <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
3816 <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide">
3818 <PORTMAP DIR="O" PHYSICAL="TX"/>
3819 <PORTMAP DIR="I" PHYSICAL="RX"/>
3823 <INTERRUPTINFO TYPE="SOURCE">
3824 <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="0"/>
3827 <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
3829 <SLAVE BUSINTERFACE="S_AXI"/>
3833 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3835 <MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
3836 <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
3837 <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
3839 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
3842 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
3843 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000"/>
3844 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4002ffff"/>
3845 <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
3846 <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
3847 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4"/>
3848 <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/>
3849 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0"/>
3850 <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/>
3851 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"/>
3852 <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/>
3853 <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/>
3854 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/>
3855 <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/>
3856 <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/>
3857 <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
3858 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
3859 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
3860 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
3861 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
3862 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
3865 <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="LEDs_4Bits_TRI_O" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
3866 <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
3867 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
3868 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
3869 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
3870 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
3871 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
3872 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
3873 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
3874 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
3875 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
3876 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
3877 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
3878 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
3879 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
3880 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
3881 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
3882 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
3883 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
3884 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
3885 <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
3886 <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
3887 <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
3888 <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
3889 <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
3890 <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
3891 <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
3892 <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
3894 <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
3895 <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
3899 <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
3901 <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
3902 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
3903 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
3904 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
3905 <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
3906 <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
3907 <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
3908 <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
3909 <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
3910 <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
3911 <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
3912 <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
3913 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
3914 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
3915 <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
3916 <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
3917 <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
3918 <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
3919 <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
3924 <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
3926 <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
3927 <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
3928 <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
3929 <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
3930 <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
3931 <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
3932 <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
3933 <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
3938 <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
3940 <SLAVE BUSINTERFACE="S_AXI"/>
3944 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
3946 <MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
3947 <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
3948 <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
3950 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
3953 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
3954 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000"/>
3955 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4000ffff"/>
3956 <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
3957 <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
3958 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4"/>
3959 <PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/>
3960 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1"/>
3961 <PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/>
3962 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="1"/>
3963 <PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/>
3964 <PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/>
3965 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/>
3966 <PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/>
3967 <PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/>
3968 <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
3969 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
3970 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
3971 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
3972 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
3973 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
3976 <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
3977 <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
3978 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
3979 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
3980 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
3981 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
3982 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
3983 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
3984 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
3985 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
3986 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
3987 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
3988 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
3989 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
3990 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
3991 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
3992 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
3993 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
3994 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
3995 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
3996 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
3997 <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
3998 <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
3999 <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
4000 <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
4001 <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
4002 <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
4003 <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
4005 <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
4006 <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
4010 <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
4012 <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4013 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4014 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
4015 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
4016 <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
4017 <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
4018 <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
4019 <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
4020 <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
4021 <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
4022 <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
4023 <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
4024 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
4025 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
4026 <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
4027 <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
4028 <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
4029 <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
4030 <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
4035 <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
4037 <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
4038 <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
4039 <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
4040 <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
4041 <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
4042 <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
4043 <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
4044 <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
4048 <INTERRUPTINFO TYPE="SOURCE">
4049 <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="1"/>
4052 <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
4054 <SLAVE BUSINTERFACE="S_AXI"/>
4058 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4060 <MODULE HWVERSION="1.00.a" INSTANCE="Ethernet_Lite" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernetlite">
4061 <DESCRIPTION TYPE="SHORT">AXI 10/100 Ethernet MAC Lite</DESCRIPTION>
4062 <DESCRIPTION TYPE="LONG">'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'</DESCRIPTION>
4064 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernetlite_v1_00_a/doc/ds787_axi_ethernetlite.pdf" TYPE="IP"/>
4067 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE"/>
4068 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
4069 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40e00000"/>
4070 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x40e0ffff"/>
4071 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_S_AXI_ACLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000"/>
4072 <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
4073 <PARAMETER MPD_INDEX="6" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
4074 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
4075 <PARAMETER MPD_INDEX="8" NAME="C_INCLUDE_MDIO" TYPE="INTEGER" VALUE="1"/>
4076 <PARAMETER MPD_INDEX="9" NAME="C_INCLUDE_GLOBAL_BUFFERS" TYPE="INTEGER" VALUE="0"/>
4077 <PARAMETER MPD_INDEX="10" NAME="C_INCLUDE_INTERNAL_LOOPBACK" TYPE="INTEGER" VALUE="0"/>
4078 <PARAMETER MPD_INDEX="11" NAME="C_DUPLEX" TYPE="INTEGER" VALUE="1"/>
4079 <PARAMETER MPD_INDEX="12" NAME="C_TX_PING_PONG" TYPE="INTEGER" VALUE="0"/>
4080 <PARAMETER MPD_INDEX="13" NAME="C_RX_PING_PONG" TYPE="INTEGER" VALUE="0"/>
4081 <PARAMETER MPD_INDEX="14" NAME="C_INCLUDE_PHY_CONSTRAINTS" TYPE="INTEGER" VALUE="1"/>
4082 <PARAMETER MPD_INDEX="15" NAME="C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="1"/>
4083 <PARAMETER MPD_INDEX="16" NAME="C_INTERCONNECT_S_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="1"/>
4084 <PARAMETER MPD_INDEX="17" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
4085 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
4086 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
4087 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
4088 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
4089 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
4092 <PORT DIR="IO" IOS="ethernet_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="0" MPD_INDEX="48" NAME="PHY_MDIO" SIGNAME="Ethernet_Lite_MDIO" TRI_I="PHY_MDIO_I" TRI_O="PHY_MDIO_O" TRI_T="PHY_MDIO_T">
4093 <DESCRIPTION>Ethernet PHY Management Data</DESCRIPTION>
4095 <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="44" NAME="PHY_MDC" SIGNAME="Ethernet_Lite_MDC">
4096 <DESCRIPTION>Ethernet PHY Management Clock</DESCRIPTION>
4098 <PORT DIR="O" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="2" MPD_INDEX="43" MSB="3" NAME="PHY_tx_data" RIGHT="0" SIGNAME="Ethernet_Lite_TXD" VECFORMULA="[3:0]">
4099 <DESCRIPTION>Ethernet Transmit Data Output</DESCRIPTION>
4101 <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="42" NAME="PHY_tx_en" SIGNAME="Ethernet_Lite_TX_EN">
4102 <DESCRIPTION>Ethernet Transmit Enable</DESCRIPTION>
4104 <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="34" NAME="PHY_tx_clk" SIGNAME="Ethernet_Lite_TX_CLK">
4105 <DESCRIPTION>Ethernet Transmit Clock Input</DESCRIPTION>
4107 <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="39" NAME="PHY_col" SIGNAME="Ethernet_Lite_COL">
4108 <DESCRIPTION>Ethernet Collision Input</DESCRIPTION>
4110 <PORT DIR="I" ENDIAN="LITTLE" IOS="ethernet_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="6" MPD_INDEX="38" MSB="3" NAME="PHY_rx_data" RIGHT="0" SIGNAME="Ethernet_Lite_RXD" VECFORMULA="[3:0]">
4111 <DESCRIPTION>Ethernet Receive Data Input</DESCRIPTION>
4113 <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="40" NAME="PHY_rx_er" SIGNAME="Ethernet_Lite_RX_ER">
4114 <DESCRIPTION>Ethernet Receive Error Input</DESCRIPTION>
4116 <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="35" NAME="PHY_rx_clk" SIGNAME="Ethernet_Lite_RX_CLK">
4117 <DESCRIPTION>Ethernet Receive Clock Input</DESCRIPTION>
4119 <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="36" NAME="PHY_crs" SIGNAME="Ethernet_Lite_CRS">
4120 <DESCRIPTION>Ethernet Carrier Sense Input</DESCRIPTION>
4122 <PORT DIR="I" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="37" NAME="PHY_dv" SIGNAME="Ethernet_Lite_RX_DV">
4123 <DESCRIPTION>Ethernet Receive Data Valid</DESCRIPTION>
4125 <PORT DIR="O" IOS="ethernet_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="41" NAME="PHY_rst_n" SIGNAME="Ethernet_Lite_PHY_RST_N">
4126 <DESCRIPTION>Ethernet PHY Reset</DESCRIPTION>
4128 <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
4129 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="2" NAME="IP2INTC_Irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
4130 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
4131 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
4132 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4133 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="5" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[7:0]"/>
4134 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="6" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[2:0]"/>
4135 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="7" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[1:0]"/>
4136 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="8" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[3:0]"/>
4137 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
4138 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="10" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
4139 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="11" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4140 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
4141 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="I" MPD_INDEX="13" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_M_WLAST"/>
4142 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
4143 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
4144 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BID" DIR="O" MPD_INDEX="16" NAME="S_AXI_BID" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
4145 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
4146 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
4147 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
4148 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
4149 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4150 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[7:0]"/>
4151 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="23" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[2:0]"/>
4152 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[1:0]"/>
4153 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[3:0]"/>
4154 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="26" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
4155 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="27" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
4156 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RID" DIR="O" MPD_INDEX="28" NAME="S_AXI_RID" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[(C_S_AXI_ID_WIDTH-1):0]"/>
4157 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4158 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
4159 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="O" MPD_INDEX="31" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_M_RLAST"/>
4160 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="32" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
4161 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="33" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
4162 <PORT DIR="I" IOS="ethernet_0" MPD_INDEX="45" NAME="PHY_MDIO_I" SIGNAME="__NOC__"/>
4163 <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="46" NAME="PHY_MDIO_O" SIGNAME="__NOC__"/>
4164 <PORT DIR="O" IOS="ethernet_0" MPD_INDEX="47" NAME="PHY_MDIO_T" SIGNAME="__NOC__"/>
4167 <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
4169 <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4170 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4171 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
4172 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
4173 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
4174 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
4175 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
4176 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
4177 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
4178 <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
4179 <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
4180 <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
4181 <PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
4182 <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
4183 <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
4184 <PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
4185 <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
4186 <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
4187 <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
4188 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
4189 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
4190 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
4191 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
4192 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
4193 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
4194 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
4195 <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
4196 <PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
4197 <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
4198 <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
4199 <PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
4200 <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
4201 <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
4206 <IOINTERFACE MPD_INDEX="0" NAME="ethernet_0" TYPE="XIL_AXIETHERNET_V1">
4208 <PORTMAP DIR="IO" PHYSICAL="PHY_MDIO"/>
4209 <PORTMAP DIR="O" PHYSICAL="PHY_MDC"/>
4210 <PORTMAP DIR="O" PHYSICAL="PHY_tx_data"/>
4211 <PORTMAP DIR="O" PHYSICAL="PHY_tx_en"/>
4212 <PORTMAP DIR="I" PHYSICAL="PHY_tx_clk"/>
4213 <PORTMAP DIR="I" PHYSICAL="PHY_col"/>
4214 <PORTMAP DIR="I" PHYSICAL="PHY_rx_data"/>
4215 <PORTMAP DIR="I" PHYSICAL="PHY_rx_er"/>
4216 <PORTMAP DIR="I" PHYSICAL="PHY_rx_clk"/>
4217 <PORTMAP DIR="I" PHYSICAL="PHY_crs"/>
4218 <PORTMAP DIR="I" PHYSICAL="PHY_dv"/>
4219 <PORTMAP DIR="O" PHYSICAL="PHY_rst_n"/>
4220 <PORTMAP DIR="I" PHYSICAL="PHY_MDIO_I"/>
4221 <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_O"/>
4222 <PORTMAP DIR="O" PHYSICAL="PHY_MDIO_T"/>
4226 <INTERRUPTINFO TYPE="SOURCE">
4227 <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="2"/>
4230 <MEMRANGE BASEDECIMAL="1088421888" BASENAME="C_BASEADDR" BASEVALUE="0x40e00000" HIGHDECIMAL="1088487423" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x40e0ffff" MEMTYPE="REGISTER" MINSIZE="0x02000" SIZE="65536" SIZEABRV="64K">
4232 <SLAVE BUSINTERFACE="S_AXI"/>
4236 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4238 <MODULE HWVERSION="1.01.a" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
4239 <DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
4240 <DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
4242 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_01_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
4245 <PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
4246 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
4247 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32"/>
4248 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0"/>
4249 <PARAMETER MPD_INDEX="4" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1"/>
4250 <PARAMETER MPD_INDEX="5" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1"/>
4251 <PARAMETER MPD_INDEX="6" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1"/>
4252 <PARAMETER MPD_INDEX="7" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1"/>
4253 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="8" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41c00000"/>
4254 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="9" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x41c0ffff"/>
4255 <PARAMETER MPD_INDEX="10" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
4256 <PARAMETER MPD_INDEX="11" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
4257 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
4258 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
4259 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
4260 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
4261 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
4264 <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
4265 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_Interrupt"/>
4266 <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
4267 <DESCRIPTION>Capture Trig 0</DESCRIPTION>
4269 <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
4270 <DESCRIPTION>Capture Trig 1</DESCRIPTION>
4272 <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
4273 <DESCRIPTION>Generate Out 0</DESCRIPTION>
4275 <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
4276 <DESCRIPTION>Generate Out 1</DESCRIPTION>
4278 <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
4279 <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
4281 <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
4282 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
4283 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4284 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
4285 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
4286 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4287 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
4288 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
4289 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
4290 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
4291 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
4292 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
4293 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4294 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
4295 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
4296 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4297 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
4298 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
4299 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
4302 <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
4304 <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4305 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4306 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
4307 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
4308 <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
4309 <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
4310 <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
4311 <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
4312 <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
4313 <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
4314 <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
4315 <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
4316 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
4317 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
4318 <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
4319 <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
4320 <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
4321 <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
4322 <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
4326 <INTERRUPTINFO TYPE="SOURCE">
4327 <TARGET INSTANCE="microblaze_0_intc" INTC_INDEX="0" PRIORITY="3"/>
4330 <MEMRANGE BASEDECIMAL="1103101952" BASENAME="C_BASEADDR" BASEVALUE="0x41c00000" HIGHDECIMAL="1103167487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
4332 <SLAVE BUSINTERFACE="S_AXI"/>
4336 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4338 <MODULE HWVERSION="1.02.a" INSTANCE="axi_bram_ctrl_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_bram_ctrl">
4339 <DESCRIPTION TYPE="SHORT">AXI BRAM Controller</DESCRIPTION>
4340 <DESCRIPTION TYPE="LONG">Attaches BRAM to the AXI</DESCRIPTION>
4342 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_bram_ctrl_v1_02_a/doc/ds777_axi_bram_ctrl.pdf" TYPE="IP"/>
4345 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
4346 <PARAMETER MPD_INDEX="1" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
4347 <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="2" NAME="C_S_AXI_BASEADDR" TYPE="std_logic_vector" VALUE="0xC4000000"/>
4348 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="3" NAME="C_S_AXI_HIGHADDR" TYPE="std_logic_vector" VALUE="0xC400FFFF"/>
4349 <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
4350 <PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
4351 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
4352 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
4353 <PARAMETER MPD_INDEX="8" NAME="C_SINGLE_PORT_BRAM" TYPE="INTEGER" VALUE="0"/>
4354 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" TYPE="INTEGER" VALUE="1"/>
4355 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="10" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" TYPE="INTEGER" VALUE="1"/>
4356 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" TYPE="INTEGER" VALUE="1"/>
4357 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="12" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" TYPE="INTEGER" VALUE="1"/>
4358 <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="13" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" TYPE="INTEGER" VALUE="1"/>
4359 <PARAMETER MPD_INDEX="14" NAME="C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="2"/>
4360 <PARAMETER MPD_INDEX="15" NAME="C_INTERCONNECT_S_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="2"/>
4361 <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
4362 <PARAMETER MPD_INDEX="17" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
4363 <PARAMETER MPD_INDEX="18" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
4364 <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="19" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff"/>
4365 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="20" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
4366 <PARAMETER MPD_INDEX="21" NAME="C_INTERCONNECT_S_AXI_CTRL_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
4367 <PARAMETER MPD_INDEX="22" NAME="C_INTERCONNECT_S_AXI_CTRL_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
4368 <PARAMETER MPD_INDEX="23" NAME="C_ECC" TYPE="INTEGER" VALUE="0"/>
4369 <PARAMETER MPD_INDEX="24" NAME="C_FAULT_INJECT" TYPE="INTEGER" VALUE="0"/>
4370 <PARAMETER MPD_INDEX="25" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="INTEGER" VALUE="1"/>
4371 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC"/>
4374 <PORT BUS="S_AXI:S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzPLL0"/>
4375 <PORT DIR="O" MPD_INDEX="0" NAME="ECC_Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
4376 <PORT DIR="O" MPD_INDEX="1" NAME="ECC_UE" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
4377 <PORT BUS="S_AXI:S_AXI_CTRL" DEF_SIGNAME="axi4_0_M_ARESETN" DIR="I" MPD_INDEX="3" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4_0_M_ARESETN"/>
4378 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWID" SIGNAME="axi4_0_M_AWID" VECFORMULA="[(C_S_AXI_ID_WIDTH - 1) : 0]"/>
4379 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4380 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="6" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4_0_M_AWLEN" VECFORMULA="[7 : 0]"/>
4381 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="7" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4_0_M_AWSIZE" VECFORMULA="[2 : 0]"/>
4382 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="8" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4_0_M_AWBURST" VECFORMULA="[1 : 0]"/>
4383 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWLOCK" DIR="I" MPD_INDEX="9" NAME="S_AXI_AWLOCK" SIGNAME="axi4_0_M_AWLOCK"/>
4384 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4_0_M_AWCACHE" VECFORMULA="[3 : 0]"/>
4385 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="11" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4_0_M_AWPROT" VECFORMULA="[2 : 0]"/>
4386 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWVALID" DIR="I" MPD_INDEX="12" NAME="S_AXI_AWVALID" SIGNAME="axi4_0_M_AWVALID"/>
4387 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_AWREADY" DIR="O" MPD_INDEX="13" NAME="S_AXI_AWREADY" SIGNAME="axi4_0_M_AWREADY"/>
4388 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="14" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH - 1) : 0]"/>
4389 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="15" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH / 8) - 1) : 0]"/>
4390 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_WLAST" DIR="I" MPD_INDEX="16" NAME="S_AXI_WLAST" SIGNAME="axi4_0_M_WLAST"/>
4391 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_WVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_WVALID" SIGNAME="axi4_0_M_WVALID"/>
4392 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_WREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_WREADY" SIGNAME="axi4_0_M_WREADY"/>
4393 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_BID" DIR="O" MPD_INDEX="19" NAME="S_AXI_BID" SIGNAME="axi4_0_M_BID" VECFORMULA="[(C_S_AXI_ID_WIDTH - 1) : 0]"/>
4394 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4_0_M_BRESP" VECFORMULA="[1 : 0]"/>
4395 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_BVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_BVALID" SIGNAME="axi4_0_M_BVALID"/>
4396 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_BREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_BREADY" SIGNAME="axi4_0_M_BREADY"/>
4397 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARID" DIR="I" MPD_INDEX="23" NAME="S_AXI_ARID" SIGNAME="axi4_0_M_ARID" VECFORMULA="[(C_S_AXI_ID_WIDTH - 1) : 0]"/>
4398 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH - 1) : 0]"/>
4399 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="25" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4_0_M_ARLEN" VECFORMULA="[7 : 0]"/>
4400 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="26" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4_0_M_ARSIZE" VECFORMULA="[2 : 0]"/>
4401 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4_0_M_ARBURST" VECFORMULA="[1 : 0]"/>
4402 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARLOCK" DIR="I" MPD_INDEX="28" NAME="S_AXI_ARLOCK" SIGNAME="axi4_0_M_ARLOCK"/>
4403 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="29" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4_0_M_ARCACHE" VECFORMULA="[3 : 0]"/>
4404 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="30" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4_0_M_ARPROT" VECFORMULA="[2 : 0]"/>
4405 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARVALID" DIR="I" MPD_INDEX="31" NAME="S_AXI_ARVALID" SIGNAME="axi4_0_M_ARVALID"/>
4406 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_ARREADY" DIR="O" MPD_INDEX="32" NAME="S_AXI_ARREADY" SIGNAME="axi4_0_M_ARREADY"/>
4407 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_RID" DIR="O" MPD_INDEX="33" NAME="S_AXI_RID" SIGNAME="axi4_0_M_RID" VECFORMULA="[(C_S_AXI_ID_WIDTH - 1) : 0]"/>
4408 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="34" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH - 1) : 0]"/>
4409 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="35" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4_0_M_RRESP" VECFORMULA="[1 : 0]"/>
4410 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_RVALID" DIR="O" MPD_INDEX="36" NAME="S_AXI_RVALID" SIGNAME="axi4_0_M_RVALID"/>
4411 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_RREADY" DIR="I" MPD_INDEX="37" NAME="S_AXI_RREADY" SIGNAME="axi4_0_M_RREADY"/>
4412 <PORT BUS="S_AXI" DEF_SIGNAME="axi4_0_M_RLAST" DIR="O" MPD_INDEX="38" NAME="S_AXI_RLAST" SIGNAME="axi4_0_M_RLAST"/>
4413 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="39" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
4414 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="40" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
4415 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="41" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXI_CTRL_ADDR_WIDTH-1:0]"/>
4416 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="42" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
4417 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="43" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
4418 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="44" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXI_CTRL_DATA_WIDTH-1:0]"/>
4419 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
4420 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="46" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
4421 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="47" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
4422 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="48" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
4423 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="49" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
4424 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXI_CTRL_ADDR_WIDTH-1:0]"/>
4425 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="51" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
4426 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="52" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
4427 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="53" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXI_CTRL_DATA_WIDTH-1:0]"/>
4428 <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
4429 <PORT BUS="BRAM_PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Rst" DIR="O" MPD_INDEX="55" NAME="BRAM_Rst_A" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Rst"/>
4430 <PORT BUS="BRAM_PORTA" CLKFREQUENCY="100000000" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Clk" DIR="O" MPD_INDEX="56" NAME="BRAM_Clk_A" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Clk"/>
4431 <PORT BUS="BRAM_PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_En" DIR="O" MPD_INDEX="57" NAME="BRAM_En_A" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_En"/>
4432 <PORT BUS="BRAM_PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_WEN" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="BRAM_WE_A" RIGHT="0" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_WEN" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8 + C_ECC) - 1) : 0]"/>
4433 <PORT BUS="BRAM_PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Addr" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="59" MSB="31" NAME="BRAM_Addr_A" RIGHT="0" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Addr" VECFORMULA="[(C_S_AXI_ADDR_WIDTH - 1) : 0]"/>
4434 <PORT BUS="BRAM_PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Dout" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="60" MSB="31" NAME="BRAM_WrData_A" RIGHT="0" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Dout" VECFORMULA="[(C_S_AXI_DATA_WIDTH + (8*C_ECC) - 1) : 0]"/>
4435 <PORT BUS="BRAM_PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Din" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="61" MSB="31" NAME="BRAM_RdData_A" RIGHT="0" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Din" VECFORMULA="[(C_S_AXI_DATA_WIDTH + (8*C_ECC) - 1) : 0]"/>
4436 <PORT BUS="BRAM_PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Rst" DIR="O" MPD_INDEX="62" NAME="BRAM_Rst_B" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Rst"/>
4437 <PORT BUS="BRAM_PORTB" CLKFREQUENCY="100000000" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Clk" DIR="O" MPD_INDEX="63" NAME="BRAM_Clk_B" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Clk"/>
4438 <PORT BUS="BRAM_PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_En" DIR="O" MPD_INDEX="64" NAME="BRAM_En_B" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_En"/>
4439 <PORT BUS="BRAM_PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_WEN" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="65" MSB="3" NAME="BRAM_WE_B" RIGHT="0" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_WEN" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8 + C_ECC) - 1) : 0]"/>
4440 <PORT BUS="BRAM_PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Addr" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="BRAM_Addr_B" RIGHT="0" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Addr" VECFORMULA="[(C_S_AXI_ADDR_WIDTH - 1) : 0]"/>
4441 <PORT BUS="BRAM_PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Dout" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="67" MSB="31" NAME="BRAM_WrData_B" RIGHT="0" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Dout" VECFORMULA="[(C_S_AXI_DATA_WIDTH + (8*C_ECC) - 1) : 0]"/>
4442 <PORT BUS="BRAM_PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Din" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="68" MSB="31" NAME="BRAM_RdData_B" RIGHT="0" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Din" VECFORMULA="[(C_S_AXI_DATA_WIDTH + (8*C_ECC) - 1) : 0]"/>
4445 <BUSINTERFACE BUSNAME="axi4_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
4447 <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4448 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4449 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
4450 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
4451 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
4452 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
4453 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
4454 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWLOCK"/>
4455 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
4456 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWPROT"/>
4457 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
4458 <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
4459 <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
4460 <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
4461 <PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
4462 <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
4463 <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
4464 <PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
4465 <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
4466 <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
4467 <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
4468 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
4469 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
4470 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
4471 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
4472 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
4473 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARLOCK"/>
4474 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
4475 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARPROT"/>
4476 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
4477 <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
4478 <PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
4479 <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
4480 <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
4481 <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
4482 <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
4483 <PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
4486 <MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
4487 <MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
4490 <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
4492 <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4493 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4494 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
4495 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
4496 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
4497 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
4498 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
4499 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
4500 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
4501 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
4502 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
4503 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
4504 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
4505 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
4506 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
4507 <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
4508 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
4509 <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
4512 <BUSINTERFACE BUSNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="BRAM_PORTA" TYPE="INITIATOR">
4514 <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
4515 <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
4516 <PORTMAP DIR="O" PHYSICAL="BRAM_En_A"/>
4517 <PORTMAP DIR="O" PHYSICAL="BRAM_WE_A"/>
4518 <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
4519 <PORTMAP DIR="O" PHYSICAL="BRAM_WrData_A"/>
4520 <PORTMAP DIR="I" PHYSICAL="BRAM_RdData_A"/>
4523 <BUSINTERFACE BUSNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="BRAM_PORTB" TYPE="INITIATOR">
4525 <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_B"/>
4526 <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_B"/>
4527 <PORTMAP DIR="O" PHYSICAL="BRAM_En_B"/>
4528 <PORTMAP DIR="O" PHYSICAL="BRAM_WE_B"/>
4529 <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_B"/>
4530 <PORTMAP DIR="O" PHYSICAL="BRAM_WrData_B"/>
4531 <PORTMAP DIR="I" PHYSICAL="BRAM_RdData_B"/>
4536 <MEMRANGE BASEDECIMAL="3288334336" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0xC4000000" HIGHDECIMAL="3288399871" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0xC400FFFF" IS_CACHEABLE="TRUE" IS_DCACHED="TRUE" IS_ICACHED="TRUE" MEMTYPE="MEMORY" MINSIZE="0xFFF" SIZE="65536" SIZEABRV="64K">
4538 <SLAVE BUSINTERFACE="S_AXI"/>
4541 <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x3FF" SIZE="0" SIZEABRV="U">
4543 <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
4547 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4549 <MODULE HWVERSION="1.00.a" INSTANCE="axi_bram_ctrl_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="MEMORY" MODTYPE="bram_block">
4550 <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
4551 <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
4553 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
4556 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x10000"/>
4557 <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"/>
4558 <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32"/>
4559 <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4"/>
4560 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
4563 <PORT BUS="PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Rst"/>
4564 <PORT BUS="PORTA" CLKFREQUENCY="100000000" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Clk"/>
4565 <PORT BUS="PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_EN"/>
4566 <PORT BUS="PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
4567 <PORT BUS="PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
4568 <PORT BUS="PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
4569 <PORT BUS="PORTA" DEF_SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
4570 <PORT BUS="PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Rst"/>
4571 <PORT BUS="PORTB" CLKFREQUENCY="100000000" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Clk"/>
4572 <PORT BUS="PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_EN"/>
4573 <PORT BUS="PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
4574 <PORT BUS="PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
4575 <PORT BUS="PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
4576 <PORT BUS="PORTB" DEF_SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
4579 <BUSINTERFACE BUSNAME="axi_bram_ctrl_0_bram_porta_2_axi_bram_ctrl_0_bram_block_porta" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
4581 <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
4582 <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
4583 <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
4584 <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
4585 <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
4586 <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
4587 <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
4590 <BUSINTERFACE BUSNAME="axi_bram_ctrl_0_bram_portb_2_axi_bram_ctrl_0_bram_block_portb" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
4592 <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
4593 <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
4594 <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
4595 <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
4596 <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
4597 <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
4598 <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
4602 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4604 <MODULE HWVERSION="1.01.a" INSTANCE="microblaze_0_intc" IPTYPE="PERIPHERAL" MHS_INDEX="18" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
4605 <DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
4606 <DESCRIPTION TYPE="LONG">intc core attached to the AXI</DESCRIPTION>
4608 <DOCUMENT SOURCE="C:/devtools/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
4611 <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
4612 <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41200000"/>
4613 <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4120ffff"/>
4614 <PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
4615 <PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
4616 <PARAMETER MPD_INDEX="5" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="2"/>
4617 <PARAMETER MPD_INDEX="6" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0xffffffff"/>
4618 <PARAMETER MPD_INDEX="7" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0xffffffff"/>
4619 <PARAMETER MPD_INDEX="8" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0xffffffff"/>
4620 <PARAMETER MPD_INDEX="9" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1"/>
4621 <PARAMETER MPD_INDEX="10" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1"/>
4622 <PARAMETER MPD_INDEX="11" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1"/>
4623 <PARAMETER MPD_INDEX="12" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1"/>
4624 <PARAMETER MPD_INDEX="13" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1"/>
4625 <PARAMETER MPD_INDEX="14" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1"/>
4626 <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
4627 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" VALUE="1"/>
4628 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" VALUE="1"/>
4629 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" VALUE="1"/>
4630 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" VALUE="1"/>
4631 <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" VALUE="1"/>
4634 <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="20" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_interrupt">
4635 <DESCRIPTION>Interrupt Request Output</DESCRIPTION>
4637 <PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_50_0000MHzPLL0"/>
4638 <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="1" NAME="INTR" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_Interrupt & Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
4640 <SIGNAL NAME="RS232_Uart_1_Interrupt"/>
4641 <SIGNAL NAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
4642 <SIGNAL NAME="Ethernet_Lite_IP2INTC_Irpt"/>
4643 <SIGNAL NAME="axi_timer_0_Interrupt"/>
4645 <DESCRIPTION>Interrupt Inputs</DESCRIPTION>
4647 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN"/>
4648 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4649 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID"/>
4650 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY"/>
4651 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4652 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
4653 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID"/>
4654 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY"/>
4655 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]"/>
4656 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID"/>
4657 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY"/>
4658 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
4659 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID"/>
4660 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY"/>
4661 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
4662 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]"/>
4663 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID"/>
4664 <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY"/>
4667 <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
4669 <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
4670 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
4671 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
4672 <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
4673 <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
4674 <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
4675 <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
4676 <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
4677 <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
4678 <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
4679 <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
4680 <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
4681 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
4682 <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
4683 <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
4684 <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
4685 <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
4686 <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
4687 <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
4691 <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
4692 <SOURCE INSTANCE="RS232_Uart_1" PRIORITY="0" SIGNAME="RS232_Uart_1_Interrupt"/>
4693 <SOURCE INSTANCE="Push_Buttons_4Bits" PRIORITY="1" SIGNAME="Push_Buttons_4Bits_IP2INTC_Irpt"/>
4694 <SOURCE INSTANCE="Ethernet_Lite" PRIORITY="2" SIGNAME="Ethernet_Lite_IP2INTC_Irpt"/>
4695 <SOURCE INSTANCE="axi_timer_0" PRIORITY="3" SIGNAME="axi_timer_0_Interrupt"/>
4696 <TARGET INSTANCE="microblaze_0"/>
4699 <MEMRANGE BASEDECIMAL="1092616192" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHDECIMAL="1092681727" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
4701 <SLAVE BUSINTERFACE="S_AXI"/>
4705 <LICENSEINFO ICON_NAME="ps_core_preferred"/>
4710 <PORT DIR="I" MHS_INDEX="0" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET"/>
4711 <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="1" NAME="CLK_P" SIGIS="CLK" SIGNAME="CLK"/>
4712 <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="2" NAME="CLK_N" SIGIS="CLK" SIGNAME="CLK"/>
4713 <PORT DIR="O" MHS_INDEX="3" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout"/>
4714 <PORT DIR="I" MHS_INDEX="4" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin"/>
4715 <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="5" MSB="0" NAME="LEDs_4Bits_TRI_O" RIGHT="3" SIGNAME="LEDs_4Bits_TRI_O"/>
4716 <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="6" MSB="0" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="3" SIGNAME="Push_Buttons_4Bits_TRI_I"/>
4717 <PORT DIR="IO" MHS_INDEX="7" NAME="Ethernet_Lite_MDIO" SIGNAME="Ethernet_Lite_MDIO"/>
4718 <PORT DIR="O" MHS_INDEX="8" NAME="Ethernet_Lite_MDC" SIGNAME="Ethernet_Lite_MDC"/>
4719 <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="9" MSB="3" NAME="Ethernet_Lite_TXD" RIGHT="0" SIGNAME="Ethernet_Lite_TXD"/>
4720 <PORT DIR="O" MHS_INDEX="10" NAME="Ethernet_Lite_TX_EN" SIGNAME="Ethernet_Lite_TX_EN"/>
4721 <PORT DIR="I" MHS_INDEX="11" NAME="Ethernet_Lite_TX_CLK" SIGNAME="Ethernet_Lite_TX_CLK"/>
4722 <PORT DIR="I" MHS_INDEX="12" NAME="Ethernet_Lite_COL" SIGNAME="Ethernet_Lite_COL"/>
4723 <PORT DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="13" MSB="3" NAME="Ethernet_Lite_RXD" RIGHT="0" SIGNAME="Ethernet_Lite_RXD"/>
4724 <PORT DIR="I" MHS_INDEX="14" NAME="Ethernet_Lite_RX_ER" SIGNAME="Ethernet_Lite_RX_ER"/>
4725 <PORT DIR="I" MHS_INDEX="15" NAME="Ethernet_Lite_RX_CLK" SIGNAME="Ethernet_Lite_RX_CLK"/>
4726 <PORT DIR="I" MHS_INDEX="16" NAME="Ethernet_Lite_CRS" SIGNAME="Ethernet_Lite_CRS"/>
4727 <PORT DIR="I" MHS_INDEX="17" NAME="Ethernet_Lite_RX_DV" SIGNAME="Ethernet_Lite_RX_DV"/>
4728 <PORT DIR="O" MHS_INDEX="18" NAME="Ethernet_Lite_PHY_RST_N" SIGNAME="Ethernet_Lite_PHY_RST_N"/>
projects / freertos / blob