git.sur5r.net Git - freertos/blob - Demo/MicroBlaze_Spartan-6_SP605/implementation/RTOSDemo_summary.html

   1 <HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
   2 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
   3 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
   4 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
   5 <TD ALIGN=CENTER COLSPAN='4'><B>Project Status (05/30/2011 - 21:01:52)</B></TD></TR>
   6 <TR ALIGN=LEFT>
   7 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
   8 <TD>RTOSDemo.xmp</TD>
   9 <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
  10 <TD>Programming File Generated</TD>
  11 </TR>
  12 <TR ALIGN=LEFT>
  13 <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
  14 <TD>RTOSDemo</TD>
  15 <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
  16 <TD>
  17 No Errors</TD>
  18 </TR>
  19 <TR ALIGN=LEFT>
  20 <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>EDK 13.1</TD>
  21 <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
  22 <TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/*.xmsgs?&DataKey=Warning'>130 Warnings (0 new)</A></TD>
  23 </TR>
  24 </TABLE>
  25
  26
  27
  28 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
  29 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>XPS Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKReports"><B>[-]</B></a></TD></TR>
  30 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Generated</B></TD>
  31 <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
  32 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\platgen.log'>Platgen Log File</A></TD><TD>Mon 30. May 20:53:24 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Warning'>8 Warnings (8 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Info'>28 Infos (25 new)</A></TD></TR>
  33 <TR ALIGN=LEFT><TD>Libgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
  34 <TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
  35 <TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
  36 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\RTOSDemo.log'>System Log File</A></TD><TD>Mon 30. May 21:01:50 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
  37 </TABLE>
  38 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
  39 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
  40 <TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
  41 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\RTOSDemo_xst.srp'>RTOSDemo</A></TD><TD>Mon 30. May 20:53:55 2011</TD><TD ALIGN=RIGHT>7701</TD><TD ALIGN=RIGHT>7505</TD><TD ALIGN=RIGHT>48</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  42 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605/synthesis\clock_generator_0_wrapper_xst.srp'>clock_generator_0_wrapper</A></TD><TD>Mon 30. May 20:53:21 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  43 <TR ALIGN=LEFT><TD>microblaze_0_intc_wrapper</TD><TD>Mon 30. May 19:38:32 2011</TD><TD ALIGN=RIGHT>72</TD><TD ALIGN=RIGHT>88</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  44 <TR ALIGN=LEFT><TD>axi_bram_ctrl_0_bram_block_wrapper</TD><TD>Mon 30. May 19:38:24 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT>32</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  45 <TR ALIGN=LEFT><TD>axi_bram_ctrl_0_wrapper</TD><TD>Mon 30. May 19:38:16 2011</TD><TD ALIGN=RIGHT>406</TD><TD ALIGN=RIGHT>619</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  46 <TR ALIGN=LEFT><TD>axi_timer_0_wrapper</TD><TD>Mon 30. May 19:38:03 2011</TD><TD ALIGN=RIGHT>260</TD><TD ALIGN=RIGHT>272</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  47 <TR ALIGN=LEFT><TD>ethernet_lite_wrapper</TD><TD>Mon 30. May 19:37:52 2011</TD><TD ALIGN=RIGHT>461</TD><TD ALIGN=RIGHT>639</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  48 <TR ALIGN=LEFT><TD>ethernet_lite_wrapper_fifo_generator_v8_1_fifo_generator_v8_1_xst_1</TD><TD>Mon 30. May 19:37:36 2011</TD><TD ALIGN=RIGHT>71</TD><TD ALIGN=RIGHT>44</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  49 <TR ALIGN=LEFT><TD>push_buttons_4bits_wrapper</TD><TD>Mon 30. May 19:35:44 2011</TD><TD ALIGN=RIGHT>72</TD><TD ALIGN=RIGHT>85</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  50 <TR ALIGN=LEFT><TD>leds_4bits_wrapper</TD><TD>Mon 30. May 19:35:34 2011</TD><TD ALIGN=RIGHT>33</TD><TD ALIGN=RIGHT>41</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  51 <TR ALIGN=LEFT><TD>rs232_uart_1_wrapper</TD><TD>Mon 30. May 19:35:24 2011</TD><TD ALIGN=RIGHT>84</TD><TD ALIGN=RIGHT>102</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  52 <TR ALIGN=LEFT><TD>debug_module_wrapper</TD><TD>Mon 30. May 19:35:15 2011</TD><TD ALIGN=RIGHT>131</TD><TD ALIGN=RIGHT>142</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  53 <TR ALIGN=LEFT><TD>proc_sys_reset_0_wrapper</TD><TD>Mon 30. May 19:35:01 2011</TD><TD ALIGN=RIGHT>69</TD><TD ALIGN=RIGHT>55</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  54 <TR ALIGN=LEFT><TD>microblaze_0_bram_block_wrapper</TD><TD>Mon 30. May 19:34:55 2011</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT>4</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  55 <TR ALIGN=LEFT><TD>microblaze_0_d_bram_ctrl_wrapper</TD><TD>Mon 30. May 19:34:50 2011</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT>6</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  56 <TR ALIGN=LEFT><TD>microblaze_0_i_bram_ctrl_wrapper</TD><TD>Mon 30. May 19:34:45 2011</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT>6</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  57 <TR ALIGN=LEFT><TD>microblaze_0_dlmb_wrapper</TD><TD>Mon 30. May 19:34:39 2011</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT>1</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  58 <TR ALIGN=LEFT><TD>microblaze_0_ilmb_wrapper</TD><TD>Mon 30. May 19:34:35 2011</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT>1</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  59 <TR ALIGN=LEFT><TD>microblaze_0_wrapper</TD><TD>Mon 30. May 19:34:30 2011</TD><TD ALIGN=RIGHT>1989</TD><TD ALIGN=RIGHT>2776</TD><TD ALIGN=RIGHT>10</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  60 <TR ALIGN=LEFT><TD>axi4lite_0_wrapper</TD><TD>Mon 30. May 19:33:39 2011</TD><TD ALIGN=RIGHT>2720</TD><TD ALIGN=RIGHT>1760</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  61 <TR ALIGN=LEFT><TD>axi4_0_wrapper</TD><TD>Mon 30. May 19:33:14 2011</TD><TD ALIGN=RIGHT>1256</TD><TD ALIGN=RIGHT>824</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
  62 </TABLE>
  63 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
  64 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary (actual values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
  65 <TR ALIGN=CENTER BGCOLOR='#FFFF99'>
  66 <TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
  67 </TR>
  68 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
  69 <TD ALIGN=RIGHT>5,491</TD>
  70 <TD ALIGN=RIGHT>54,576</TD>
  71 <TD ALIGN=RIGHT>10%</TD>
  72 <TD COLSPAN='2'>&nbsp;</TD>
  73 </TR>
  74 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
  75 <TD ALIGN=RIGHT>5,482</TD>
  76 <TD>&nbsp;</TD>
  77 <TD>&nbsp;</TD>
  78 <TD COLSPAN='2'>&nbsp;</TD>
  79 </TR>
  80 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
  81 <TD ALIGN=RIGHT>0</TD>
  82 <TD>&nbsp;</TD>
  83 <TD>&nbsp;</TD>
  84 <TD COLSPAN='2'>&nbsp;</TD>
  85 </TR>
  86 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
  87 <TD ALIGN=RIGHT>0</TD>
  88 <TD>&nbsp;</TD>
  89 <TD>&nbsp;</TD>
  90 <TD COLSPAN='2'>&nbsp;</TD>
  91 </TR>
  92 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
  93 <TD ALIGN=RIGHT>9</TD>
  94 <TD>&nbsp;</TD>
  95 <TD>&nbsp;</TD>
  96 <TD COLSPAN='2'>&nbsp;</TD>
  97 </TR>
  98 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
  99 <TD ALIGN=RIGHT>5,420</TD>
 100 <TD ALIGN=RIGHT>27,288</TD>
 101 <TD ALIGN=RIGHT>19%</TD>
 102 <TD COLSPAN='2'>&nbsp;</TD>
 103 </TR>
 104 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
 105 <TD ALIGN=RIGHT>4,951</TD>
 106 <TD ALIGN=RIGHT>27,288</TD>
 107 <TD ALIGN=RIGHT>18%</TD>
 108 <TD COLSPAN='2'>&nbsp;</TD>
 109 </TR>
 110 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
 111 <TD ALIGN=RIGHT>3,573</TD>
 112 <TD>&nbsp;</TD>
 113 <TD>&nbsp;</TD>
 114 <TD COLSPAN='2'>&nbsp;</TD>
 115 </TR>
 116 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
 117 <TD ALIGN=RIGHT>99</TD>
 118 <TD>&nbsp;</TD>
 119 <TD>&nbsp;</TD>
 120 <TD COLSPAN='2'>&nbsp;</TD>
 121 </TR>
 122 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
 123 <TD ALIGN=RIGHT>1,279</TD>
 124 <TD>&nbsp;</TD>
 125 <TD>&nbsp;</TD>
 126 <TD COLSPAN='2'>&nbsp;</TD>
 127 </TR>
 128 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
 129 <TD ALIGN=RIGHT>0</TD>
 130 <TD>&nbsp;</TD>
 131 <TD>&nbsp;</TD>
 132 <TD COLSPAN='2'>&nbsp;</TD>
 133 </TR>
 134 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
 135 <TD ALIGN=RIGHT>242</TD>
 136 <TD ALIGN=RIGHT>6,408</TD>
 137 <TD ALIGN=RIGHT>3%</TD>
 138 <TD COLSPAN='2'>&nbsp;</TD>
 139 </TR>
 140 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Dual Port RAM</TD>
 141 <TD ALIGN=RIGHT>96</TD>
 142 <TD>&nbsp;</TD>
 143 <TD>&nbsp;</TD>
 144 <TD COLSPAN='2'>&nbsp;</TD>
 145 </TR>
 146 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
 147 <TD ALIGN=RIGHT>4</TD>
 148 <TD>&nbsp;</TD>
 149 <TD>&nbsp;</TD>
 150 <TD COLSPAN='2'>&nbsp;</TD>
 151 </TR>
 152 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
 153 <TD ALIGN=RIGHT>1</TD>
 154 <TD>&nbsp;</TD>
 155 <TD>&nbsp;</TD>
 156 <TD COLSPAN='2'>&nbsp;</TD>
 157 </TR>
 158 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
 159 <TD ALIGN=RIGHT>91</TD>
 160 <TD>&nbsp;</TD>
 161 <TD>&nbsp;</TD>
 162 <TD COLSPAN='2'>&nbsp;</TD>
 163 </TR>
 164 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Single Port RAM</TD>
 165 <TD ALIGN=RIGHT>4</TD>
 166 <TD>&nbsp;</TD>
 167 <TD>&nbsp;</TD>
 168 <TD COLSPAN='2'>&nbsp;</TD>
 169 </TR>
 170 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
 171 <TD ALIGN=RIGHT>4</TD>
 172 <TD>&nbsp;</TD>
 173 <TD>&nbsp;</TD>
 174 <TD COLSPAN='2'>&nbsp;</TD>
 175 </TR>
 176 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
 177 <TD ALIGN=RIGHT>0</TD>
 178 <TD>&nbsp;</TD>
 179 <TD>&nbsp;</TD>
 180 <TD COLSPAN='2'>&nbsp;</TD>
 181 </TR>
 182 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
 183 <TD ALIGN=RIGHT>0</TD>
 184 <TD>&nbsp;</TD>
 185 <TD>&nbsp;</TD>
 186 <TD COLSPAN='2'>&nbsp;</TD>
 187 </TR>
 188 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift Register</TD>
 189 <TD ALIGN=RIGHT>142</TD>
 190 <TD>&nbsp;</TD>
 191 <TD>&nbsp;</TD>
 192 <TD COLSPAN='2'>&nbsp;</TD>
 193 </TR>
 194 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
 195 <TD ALIGN=RIGHT>48</TD>
 196 <TD>&nbsp;</TD>
 197 <TD>&nbsp;</TD>
 198 <TD COLSPAN='2'>&nbsp;</TD>
 199 </TR>
 200 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
 201 <TD ALIGN=RIGHT>1</TD>
 202 <TD>&nbsp;</TD>
 203 <TD>&nbsp;</TD>
 204 <TD COLSPAN='2'>&nbsp;</TD>
 205 </TR>
 206 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
 207 <TD ALIGN=RIGHT>93</TD>
 208 <TD>&nbsp;</TD>
 209 <TD>&nbsp;</TD>
 210 <TD COLSPAN='2'>&nbsp;</TD>
 211 </TR>
 212 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
 213 <TD ALIGN=RIGHT>227</TD>
 214 <TD>&nbsp;</TD>
 215 <TD>&nbsp;</TD>
 216 <TD COLSPAN='2'>&nbsp;</TD>
 217 </TR>
 218 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
 219 <TD ALIGN=RIGHT>217</TD>
 220 <TD>&nbsp;</TD>
 221 <TD>&nbsp;</TD>
 222 <TD COLSPAN='2'>&nbsp;</TD>
 223 </TR>
 224 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
 225 <TD ALIGN=RIGHT>10</TD>
 226 <TD>&nbsp;</TD>
 227 <TD>&nbsp;</TD>
 228 <TD COLSPAN='2'>&nbsp;</TD>
 229 </TR>
 230 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
 231 <TD ALIGN=RIGHT>0</TD>
 232 <TD>&nbsp;</TD>
 233 <TD>&nbsp;</TD>
 234 <TD COLSPAN='2'>&nbsp;</TD>
 235 </TR>
 236 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
 237 <TD ALIGN=RIGHT>2,280</TD>
 238 <TD ALIGN=RIGHT>6,822</TD>
 239 <TD ALIGN=RIGHT>33%</TD>
 240 <TD COLSPAN='2'>&nbsp;</TD>
 241 </TR>
 242 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
 243 <TD ALIGN=RIGHT>6,801</TD>
 244 <TD>&nbsp;</TD>
 245 <TD>&nbsp;</TD>
 246 <TD COLSPAN='2'>&nbsp;</TD>
 247 </TR>
 248 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
 249 <TD ALIGN=RIGHT>2,068</TD>
 250 <TD ALIGN=RIGHT>6,801</TD>
 251 <TD ALIGN=RIGHT>30%</TD>
 252 <TD COLSPAN='2'>&nbsp;</TD>
 253 </TR>
 254 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
 255 <TD ALIGN=RIGHT>1,381</TD>
 256 <TD ALIGN=RIGHT>6,801</TD>
 257 <TD ALIGN=RIGHT>20%</TD>
 258 <TD COLSPAN='2'>&nbsp;</TD>
 259 </TR>
 260 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
 261 <TD ALIGN=RIGHT>3,352</TD>
 262 <TD ALIGN=RIGHT>6,801</TD>
 263 <TD ALIGN=RIGHT>49%</TD>
 264 <TD COLSPAN='2'>&nbsp;</TD>
 265 </TR>
 266 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
 267 <TD ALIGN=RIGHT>364</TD>
 268 <TD>&nbsp;</TD>
 269 <TD>&nbsp;</TD>
 270 <TD COLSPAN='2'>&nbsp;</TD>
 271 </TR>
 272 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
 273 <TD ALIGN=RIGHT>1,396</TD>
 274 <TD ALIGN=RIGHT>54,576</TD>
 275 <TD ALIGN=RIGHT>2%</TD>
 276 <TD COLSPAN='2'>&nbsp;</TD>
 277 </TR>
 278 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
 279 <TD ALIGN=RIGHT>30</TD>
 280 <TD ALIGN=RIGHT>296</TD>
 281 <TD ALIGN=RIGHT>10%</TD>
 282 <TD COLSPAN='2'>&nbsp;</TD>
 283 </TR>
 284 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
 285 <TD ALIGN=RIGHT>30</TD>
 286 <TD ALIGN=RIGHT>30</TD>
 287 <TD ALIGN=RIGHT>100%</TD>
 288 <TD COLSPAN='2'>&nbsp;</TD>
 289 </TR>
 290 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;IOB Flip Flops</TD>
 291 <TD ALIGN=RIGHT>18</TD>
 292 <TD>&nbsp;</TD>
 293 <TD>&nbsp;</TD>
 294 <TD COLSPAN='2'>&nbsp;</TD>
 295 </TR>
 296 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
 297 <TD ALIGN=RIGHT>48</TD>
 298 <TD ALIGN=RIGHT>116</TD>
 299 <TD ALIGN=RIGHT>41%</TD>
 300 <TD COLSPAN='2'>&nbsp;</TD>
 301 </TR>
 302 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
 303 <TD ALIGN=RIGHT>0</TD>
 304 <TD ALIGN=RIGHT>232</TD>
 305 <TD ALIGN=RIGHT>0%</TD>
 306 <TD COLSPAN='2'>&nbsp;</TD>
 307 </TR>
 308 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
 309 <TD ALIGN=RIGHT>1</TD>
 310 <TD ALIGN=RIGHT>32</TD>
 311 <TD ALIGN=RIGHT>3%</TD>
 312 <TD COLSPAN='2'>&nbsp;</TD>
 313 </TR>
 314 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFIO2s</TD>
 315 <TD ALIGN=RIGHT>1</TD>
 316 <TD>&nbsp;</TD>
 317 <TD>&nbsp;</TD>
 318 <TD COLSPAN='2'>&nbsp;</TD>
 319 </TR>
 320 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFIO2_2CLKs</TD>
 321 <TD ALIGN=RIGHT>0</TD>
 322 <TD>&nbsp;</TD>
 323 <TD>&nbsp;</TD>
 324 <TD COLSPAN='2'>&nbsp;</TD>
 325 </TR>
 326 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
 327 <TD ALIGN=RIGHT>0</TD>
 328 <TD ALIGN=RIGHT>32</TD>
 329 <TD ALIGN=RIGHT>0%</TD>
 330 <TD COLSPAN='2'>&nbsp;</TD>
 331 </TR>
 332 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
 333 <TD ALIGN=RIGHT>3</TD>
 334 <TD ALIGN=RIGHT>16</TD>
 335 <TD ALIGN=RIGHT>18%</TD>
 336 <TD COLSPAN='2'>&nbsp;</TD>
 337 </TR>
 338 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
 339 <TD ALIGN=RIGHT>3</TD>
 340 <TD>&nbsp;</TD>
 341 <TD>&nbsp;</TD>
 342 <TD COLSPAN='2'>&nbsp;</TD>
 343 </TR>
 344 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
 345 <TD ALIGN=RIGHT>0</TD>
 346 <TD>&nbsp;</TD>
 347 <TD>&nbsp;</TD>
 348 <TD COLSPAN='2'>&nbsp;</TD>
 349 </TR>
 350 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
 351 <TD ALIGN=RIGHT>0</TD>
 352 <TD ALIGN=RIGHT>8</TD>
 353 <TD ALIGN=RIGHT>0%</TD>
 354 <TD COLSPAN='2'>&nbsp;</TD>
 355 </TR>
 356 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
 357 <TD ALIGN=RIGHT>10</TD>
 358 <TD ALIGN=RIGHT>376</TD>
 359 <TD ALIGN=RIGHT>2%</TD>
 360 <TD COLSPAN='2'>&nbsp;</TD>
 361 </TR>
 362 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as ILOGIC2s</TD>
 363 <TD ALIGN=RIGHT>10</TD>
 364 <TD>&nbsp;</TD>
 365 <TD>&nbsp;</TD>
 366 <TD COLSPAN='2'>&nbsp;</TD>
 367 </TR>
 368 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as ISERDES2s</TD>
 369 <TD ALIGN=RIGHT>0</TD>
 370 <TD>&nbsp;</TD>
 371 <TD>&nbsp;</TD>
 372 <TD COLSPAN='2'>&nbsp;</TD>
 373 </TR>
 374 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
 375 <TD ALIGN=RIGHT>0</TD>
 376 <TD ALIGN=RIGHT>376</TD>
 377 <TD ALIGN=RIGHT>0%</TD>
 378 <TD COLSPAN='2'>&nbsp;</TD>
 379 </TR>
 380 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
 381 <TD ALIGN=RIGHT>7</TD>
 382 <TD ALIGN=RIGHT>376</TD>
 383 <TD ALIGN=RIGHT>1%</TD>
 384 <TD COLSPAN='2'>&nbsp;</TD>
 385 </TR>
 386 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as OLOGIC2s</TD>
 387 <TD ALIGN=RIGHT>7</TD>
 388 <TD>&nbsp;</TD>
 389 <TD>&nbsp;</TD>
 390 <TD COLSPAN='2'>&nbsp;</TD>
 391 </TR>
 392 <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as OSERDES2s</TD>
 393 <TD ALIGN=RIGHT>0</TD>
 394 <TD>&nbsp;</TD>
 395 <TD>&nbsp;</TD>
 396 <TD COLSPAN='2'>&nbsp;</TD>
 397 </TR>
 398 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
 399 <TD ALIGN=RIGHT>1</TD>
 400 <TD ALIGN=RIGHT>4</TD>
 401 <TD ALIGN=RIGHT>25%</TD>
 402 <TD COLSPAN='2'>&nbsp;</TD>
 403 </TR>
 404 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
 405 <TD ALIGN=RIGHT>0</TD>
 406 <TD ALIGN=RIGHT>256</TD>
 407 <TD ALIGN=RIGHT>0%</TD>
 408 <TD COLSPAN='2'>&nbsp;</TD>
 409 </TR>
 410 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
 411 <TD ALIGN=RIGHT>0</TD>
 412 <TD ALIGN=RIGHT>8</TD>
 413 <TD ALIGN=RIGHT>0%</TD>
 414 <TD COLSPAN='2'>&nbsp;</TD>
 415 </TR>
 416 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
 417 <TD ALIGN=RIGHT>0</TD>
 418 <TD ALIGN=RIGHT>4</TD>
 419 <TD ALIGN=RIGHT>0%</TD>
 420 <TD COLSPAN='2'>&nbsp;</TD>
 421 </TR>
 422 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
 423 <TD ALIGN=RIGHT>8</TD>
 424 <TD ALIGN=RIGHT>58</TD>
 425 <TD ALIGN=RIGHT>13%</TD>
 426 <TD COLSPAN='2'>&nbsp;</TD>
 427 </TR>
 428 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GTPA1_DUALs</TD>
 429 <TD ALIGN=RIGHT>0</TD>
 430 <TD ALIGN=RIGHT>2</TD>
 431 <TD ALIGN=RIGHT>0%</TD>
 432 <TD COLSPAN='2'>&nbsp;</TD>
 433 </TR>
 434 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
 435 <TD ALIGN=RIGHT>0</TD>
 436 <TD ALIGN=RIGHT>1</TD>
 437 <TD ALIGN=RIGHT>0%</TD>
 438 <TD COLSPAN='2'>&nbsp;</TD>
 439 </TR>
 440 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
 441 <TD ALIGN=RIGHT>0</TD>
 442 <TD ALIGN=RIGHT>2</TD>
 443 <TD ALIGN=RIGHT>0%</TD>
 444 <TD COLSPAN='2'>&nbsp;</TD>
 445 </TR>
 446 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCIE_A1s</TD>
 447 <TD ALIGN=RIGHT>0</TD>
 448 <TD ALIGN=RIGHT>1</TD>
 449 <TD ALIGN=RIGHT>0%</TD>
 450 <TD COLSPAN='2'>&nbsp;</TD>
 451 </TR>
 452 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
 453 <TD ALIGN=RIGHT>0</TD>
 454 <TD ALIGN=RIGHT>2</TD>
 455 <TD ALIGN=RIGHT>0%</TD>
 456 <TD COLSPAN='2'>&nbsp;</TD>
 457 </TR>
 458 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
 459 <TD ALIGN=RIGHT>1</TD>
 460 <TD ALIGN=RIGHT>4</TD>
 461 <TD ALIGN=RIGHT>25%</TD>
 462 <TD COLSPAN='2'>&nbsp;</TD>
 463 </TR>
 464 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
 465 <TD ALIGN=RIGHT>0</TD>
 466 <TD ALIGN=RIGHT>1</TD>
 467 <TD ALIGN=RIGHT>0%</TD>
 468 <TD COLSPAN='2'>&nbsp;</TD>
 469 </TR>
 470 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
 471 <TD ALIGN=RIGHT>0</TD>
 472 <TD ALIGN=RIGHT>1</TD>
 473 <TD ALIGN=RIGHT>0%</TD>
 474 <TD COLSPAN='2'>&nbsp;</TD>
 475 </TR>
 476 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
 477 <TD ALIGN=RIGHT>0</TD>
 478 <TD ALIGN=RIGHT>1</TD>
 479 <TD ALIGN=RIGHT>0%</TD>
 480 <TD COLSPAN='2'>&nbsp;</TD>
 481 </TR>
 482 <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
 483 <TD ALIGN=RIGHT>3.93</TD>
 484 <TD>&nbsp;</TD>
 485 <TD>&nbsp;</TD>
 486 <TD COLSPAN='2'>&nbsp;</TD>
 487 </TR>
 488 </TABLE>
 489
 490
 491
 492 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 493 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
 494 <TR ALIGN=LEFT>
 495 <TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
 496 <TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
 497 <TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
 498 <TD COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
 499 </TR>
 500 <TR ALIGN=LEFT>
 501 <TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
 502 <A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo.unroutes'>All Signals Completely Routed</A></TD>
 503 <TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
 504 <TD COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
 505 </TR>
 506 <TR ALIGN=LEFT>
 507 <TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
 508 <TD>
 509 <A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
 510 <TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
 511 <TD COLSPAN='2'>&nbsp;</TD>
 512 </TABLE>
 513
 514
 515
 516 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 517 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
 518 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
 519 <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
 520 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon 30. May 20:54:28 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>51 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
 521 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon 30. May 20:59:03 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/map.xmsgs?&DataKey=Warning'>26 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/map.xmsgs?&DataKey=Info'>842 Infos (0 new)</A></TD></TR>
 522 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon 30. May 21:00:37 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/par.xmsgs?&DataKey=Warning'>28 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
 523 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon 30. May 21:01:05 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
 524 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\RTOSDemo.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon 30. May 21:01:52 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>25 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
 525 </TABLE>
 526 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 527 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
 528 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
 529 <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_SP605\implementation\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 30. May 21:01:52 2011</TD></TR>
 530 </TABLE>
 531
 532
 533 <br><center><b>Date Generated:</b> 05/30/2011 - 21:01:52</center>
 534 </BODY></HTML>