3 System_Wizard_Version = "8.00";
\r
4 System_Wizard_Build = "215";
\r
5 Builder_Application = "sopc_builder_ca";
\r
6 WIZARD_SCRIPT_ARGUMENTS
\r
8 hdl_language = "vhdl";
\r
9 device_family = "CYCLONEIII";
\r
10 device_family_id = "CYCLONEIII";
\r
13 hardcopy_compatible = "0";
\r
18 frequency = "75000000";
\r
19 source = "External";
\r
20 Is_Clock_Source = "0";
\r
21 display_name = "clk";
\r
23 clock_module_connection_point_for_c2h = "clk.clk";
\r
26 clock_freq = "75000000";
\r
27 clock_freq = "75000000";
\r
29 view_master_columns = "1";
\r
30 view_master_priorities = "0";
\r
32 bustype_column_width = "0";
\r
33 clock_column_width = "80";
\r
34 name_column_width = "75";
\r
35 desc_column_width = "75";
\r
36 base_column_width = "75";
\r
37 end_column_width = "75";
\r
40 altera_avalon_epcs_flash_controller
\r
42 reference_designators = "";
\r
44 altera_avalon_cfi_flash
\r
46 reference_designators = "";
\r
49 do_log_history = "0";
\r
53 MASTER instruction_master
\r
61 direction = "input";
\r
68 direction = "input";
\r
75 direction = "output";
\r
82 direction = "output";
\r
89 direction = "input";
\r
92 PORT i_readdatavalid
\r
94 type = "readdatavalid";
\r
96 direction = "input";
\r
101 type = "waitrequest";
\r
103 direction = "input";
\r
107 SYSTEM_BUILDER_INFO
\r
109 Bus_Type = "avalon";
\r
110 Is_Asynchronous = "0";
\r
111 DBS_Big_Endian = "0";
\r
113 Do_Stream_Reads = "0";
\r
114 Do_Stream_Writes = "0";
\r
115 Max_Address_Width = "32";
\r
117 Address_Width = "25";
\r
118 Maximum_Burst_Size = "1";
\r
119 Register_Incoming_Signals = "0";
\r
120 Register_Outgoing_Signals = "0";
\r
121 Interleave_Bursts = "";
\r
122 Linewrap_Bursts = "";
\r
123 Burst_On_Burst_Boundaries_Only = "";
\r
124 Always_Burst_Max_Burst = "";
\r
125 Is_Big_Endian = "0";
\r
127 Is_Instruction_Master = "1";
\r
129 Is_Writeable = "0";
\r
130 Address_Group = "0";
\r
132 Irq_Scheme = "individual_requests";
\r
133 Interrupt_Range = "0-0";
\r
137 Entry cpu_0/jtag_debug_module
\r
139 address = "0x00901800";
\r
140 span = "0x00000800";
\r
143 Entry onchip_memory/s1
\r
145 address = "0x00904000";
\r
146 span = "0x00002000";
\r
151 address = "0x01000000";
\r
152 span = "0x01000000";
\r
155 Entry epcs_controller/epcs_control_port
\r
157 address = "0x00906000";
\r
158 span = "0x00000800";
\r
163 address = "0x00000000";
\r
164 span = "0x00800000";
\r
167 Entry DBC3C40_SRAM_inst/avalon_tristate_slave
\r
169 address = "0x00800000";
\r
170 span = "0x00100000";
\r
175 MASTER custom_instruction_master
\r
177 SYSTEM_BUILDER_INFO
\r
179 Bus_Type = "nios_custom_instruction";
\r
181 Address_Width = "8";
\r
182 Is_Custom_Instruction = "1";
\r
184 Max_Address_Width = "8";
\r
185 Base_Address = "N/A";
\r
194 direction = "output";
\r
200 direction = "output";
\r
206 direction = "input";
\r
212 direction = "output";
\r
218 direction = "output";
\r
224 direction = "output";
\r
230 direction = "input";
\r
236 direction = "output";
\r
242 direction = "output";
\r
248 direction = "output";
\r
254 direction = "output";
\r
260 direction = "output";
\r
266 direction = "output";
\r
272 direction = "output";
\r
276 SLAVE jtag_debug_module
\r
278 SYSTEM_BUILDER_INFO
\r
280 Bus_Type = "avalon";
\r
281 Write_Wait_States = "0cycles";
\r
282 Read_Wait_States = "1cycles";
\r
283 Hold_Time = "0cycles";
\r
284 Setup_Time = "0cycles";
\r
285 Is_Printable_Device = "0";
\r
286 Address_Alignment = "dynamic";
\r
287 Well_Behaved_Waitrequest = "0";
\r
288 Is_Nonvolatile_Storage = "0";
\r
289 Address_Span = "2048";
\r
290 Read_Latency = "0";
\r
291 Is_Memory_Device = "1";
\r
292 Maximum_Pending_Read_Transactions = "0";
\r
293 Minimum_Uninterrupted_Run_Length = "1";
\r
294 Accepts_Internal_Connections = "1";
\r
295 Write_Latency = "0";
\r
298 Address_Width = "9";
\r
299 Maximum_Burst_Size = "1";
\r
300 Register_Incoming_Signals = "0";
\r
301 Register_Outgoing_Signals = "0";
\r
302 Interleave_Bursts = "0";
\r
303 Linewrap_Bursts = "0";
\r
304 Burst_On_Burst_Boundaries_Only = "0";
\r
305 Always_Burst_Max_Burst = "0";
\r
306 Is_Big_Endian = "0";
\r
308 Accepts_External_Connections = "1";
\r
309 Requires_Internal_Connections = "";
\r
310 MASTERED_BY cpu_0/instruction_master
\r
313 Offset_Address = "0x00901800";
\r
315 MASTERED_BY cpu_0/data_master
\r
318 Offset_Address = "0x00901800";
\r
320 Base_Address = "0x00901800";
\r
322 Is_Writeable = "1";
\r
323 Uses_Tri_State_Data_Bus = "0";
\r
325 JTAG_Hub_Base_Id = "1118278";
\r
326 JTAG_Hub_Instance_Id = "0";
\r
327 Address_Group = "0";
\r
328 IRQ_MASTER cpu_0/data_master
\r
335 PORT jtag_debug_module_address
\r
339 direction = "input";
\r
342 PORT jtag_debug_module_begintransfer
\r
344 type = "begintransfer";
\r
346 direction = "input";
\r
349 PORT jtag_debug_module_byteenable
\r
351 type = "byteenable";
\r
353 direction = "input";
\r
356 PORT jtag_debug_module_clk
\r
360 direction = "input";
\r
363 PORT jtag_debug_module_debugaccess
\r
365 type = "debugaccess";
\r
367 direction = "input";
\r
370 PORT jtag_debug_module_readdata
\r
374 direction = "output";
\r
377 PORT jtag_debug_module_reset
\r
381 direction = "input";
\r
384 PORT jtag_debug_module_resetrequest
\r
386 type = "resetrequest";
\r
388 direction = "output";
\r
391 PORT jtag_debug_module_select
\r
393 type = "chipselect";
\r
395 direction = "input";
\r
398 PORT jtag_debug_module_write
\r
402 direction = "input";
\r
405 PORT jtag_debug_module_writedata
\r
407 type = "writedata";
\r
409 direction = "input";
\r
415 direction = "input";
\r
423 SYSTEM_BUILDER_INFO
\r
426 Irq_Scheme = "individual_requests";
\r
427 Bus_Type = "avalon";
\r
428 Is_Asynchronous = "0";
\r
429 DBS_Big_Endian = "0";
\r
431 Do_Stream_Reads = "0";
\r
432 Do_Stream_Writes = "0";
\r
433 Max_Address_Width = "32";
\r
435 Address_Width = "25";
\r
436 Maximum_Burst_Size = "1";
\r
437 Register_Incoming_Signals = "1";
\r
438 Register_Outgoing_Signals = "0";
\r
439 Interleave_Bursts = "0";
\r
440 Linewrap_Bursts = "0";
\r
441 Burst_On_Burst_Boundaries_Only = "";
\r
442 Always_Burst_Max_Burst = "0";
\r
443 Is_Big_Endian = "0";
\r
445 Is_Data_Master = "1";
\r
446 Address_Group = "0";
\r
448 Is_Writeable = "1";
\r
449 Interrupt_Range = "0-31";
\r
457 direction = "input";
\r
464 direction = "output";
\r
469 type = "byteenable";
\r
471 direction = "output";
\r
478 direction = "output";
\r
485 direction = "input";
\r
488 PORT d_readdatavalid
\r
490 type = "readdatavalid";
\r
492 direction = "input";
\r
497 type = "waitrequest";
\r
499 direction = "input";
\r
506 direction = "output";
\r
511 type = "writedata";
\r
513 direction = "output";
\r
516 PORT jtag_debug_module_debugaccess_to_roms
\r
518 type = "debugaccess";
\r
520 direction = "output";
\r
526 Entry cpu_0/jtag_debug_module
\r
528 address = "0x00901800";
\r
529 span = "0x00000800";
\r
532 Entry onchip_memory/s1
\r
534 address = "0x00904000";
\r
535 span = "0x00002000";
\r
538 Entry jtag_uart_0/avalon_jtag_slave
\r
540 address = "0x009000d0";
\r
541 span = "0x00000008";
\r
546 address = "0x01000000";
\r
547 span = "0x01000000";
\r
550 Entry sysid/control_slave
\r
552 address = "0x009000d8";
\r
553 span = "0x00000008";
\r
558 address = "0x00900080";
\r
559 span = "0x00000010";
\r
564 address = "0x00900090";
\r
565 span = "0x00000010";
\r
570 address = "0x009000a0";
\r
571 span = "0x00000010";
\r
574 Entry Button_Pio/s1
\r
576 address = "0x009000b0";
\r
577 span = "0x00000010";
\r
582 address = "0x00900040";
\r
583 span = "0x00000020";
\r
588 address = "0x009000c0";
\r
589 span = "0x00000010";
\r
592 Entry epcs_controller/epcs_control_port
\r
594 address = "0x00906000";
\r
595 span = "0x00000800";
\r
600 address = "0x00000000";
\r
601 span = "0x00800000";
\r
604 Entry DBC3C40_SRAM_inst/avalon_tristate_slave
\r
606 address = "0x00800000";
\r
607 span = "0x00100000";
\r
612 address = "0x00900060";
\r
613 span = "0x00000020";
\r
616 Entry nios_vga_inst/vga_regs
\r
618 address = "0x00900000";
\r
619 span = "0x00000040";
\r
624 WIZARD_SCRIPT_ARGUMENTS
\r
626 cache_has_dcache = "0";
\r
627 cache_dcache_size = "0";
\r
628 cache_dcache_line_size = "0";
\r
629 cache_dcache_bursts = "0";
\r
630 cache_dcache_ram_block_type = "AUTO";
\r
631 num_tightly_coupled_data_masters = "0";
\r
632 gui_num_tightly_coupled_data_masters = "0";
\r
633 gui_include_tightly_coupled_data_masters = "0";
\r
634 gui_omit_avalon_data_master = "0";
\r
635 cache_has_icache = "1";
\r
636 cache_icache_size = "16384";
\r
637 cache_icache_line_size = "32";
\r
638 cache_icache_ram_block_type = "AUTO";
\r
639 cache_icache_bursts = "0";
\r
640 num_tightly_coupled_instruction_masters = "0";
\r
641 gui_num_tightly_coupled_instruction_masters = "0";
\r
642 gui_include_tightly_coupled_instruction_masters = "0";
\r
645 oci_sbi_enabled = "1";
\r
646 oci_num_xbrk = "2";
\r
647 oci_num_dbrk = "2";
\r
648 oci_dbrk_trace = "0";
\r
649 oci_dbrk_pairs = "1";
\r
650 oci_onchip_trace = "0";
\r
651 oci_offchip_trace = "0";
\r
652 oci_data_trace = "0";
\r
653 include_third_party_debug_port = "0";
\r
654 oci_trace_addr_width = "7";
\r
655 oci_trigger_arming = "1";
\r
656 oci_debugreq_signals = "0";
\r
657 oci_embedded_pll = "0";
\r
659 oci_pm_width = "32";
\r
660 performance_counters_present = "0";
\r
661 performance_counters_width = "32";
\r
662 always_encrypt = "1";
\r
663 debug_simgen = "0";
\r
664 activate_model_checker = "0";
\r
665 activate_test_end_checker = "0";
\r
666 activate_trace = "1";
\r
667 activate_monitors = "1";
\r
668 clear_x_bits_ld_non_bypass = "1";
\r
669 bit_31_bypass_dcache = "1";
\r
670 hdl_sim_caches_cleared = "1";
\r
672 allow_full_address_range = "0";
\r
673 extra_exc_info = "0";
\r
674 branch_prediction_type = "Static";
\r
676 bht_index_pc_only = "0";
\r
677 gui_branch_prediction_type = "Static";
\r
678 full_waveform_signals = "0";
\r
680 avalon_debug_port_present = "0";
\r
681 illegal_instructions_trap = "0";
\r
682 illegal_memory_access_detection = "0";
\r
683 illegal_mem_exc = "0";
\r
684 slave_access_error_exc = "0";
\r
685 division_error_exc = "0";
\r
686 advanced_exc = "0";
\r
687 gui_mmu_present = "0";
\r
689 process_id_num_bits = "8";
\r
691 tlb_num_ways = "16";
\r
692 udtlb_num_entries = "6";
\r
693 uitlb_num_entries = "4";
\r
694 fast_tlb_miss_exc_slave = "";
\r
695 fast_tlb_miss_exc_offset = "0x00000000";
\r
697 mpu_num_data_regions = "8";
\r
698 mpu_num_inst_regions = "8";
\r
699 mpu_min_data_region_size_log2 = "12";
\r
700 mpu_min_inst_region_size_log2 = "12";
\r
701 mpu_use_limit = "0";
\r
702 hardware_divide_present = "0";
\r
703 gui_hardware_divide_setting = "0";
\r
704 hardware_multiply_present = "1";
\r
705 hardware_multiply_impl = "embedded_mul";
\r
706 shift_rot_impl = "fast_le_shift";
\r
707 gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";
\r
708 reset_slave = "cfi_flash/s1";
\r
709 break_slave = "cpu_0/jtag_debug_module";
\r
710 exc_slave = "sdram/s1";
\r
711 reset_offset = "0x00000000";
\r
712 break_offset = "0x00000020";
\r
713 exc_offset = "0x00000020";
\r
715 CPU_Implementation = "small";
\r
716 cpu_selection = "s";
\r
717 device_family_id = "CYCLONEIII";
\r
718 address_stall_present = "1";
\r
719 dsp_block_supports_shift = "0";
\r
720 mrams_present = "0";
\r
724 dont_overwrite_cpuid = "1";
\r
725 allow_legacy_sdk = "1";
\r
726 legacy_sdk_support = "1";
\r
727 inst_addr_width = "25";
\r
728 data_addr_width = "25";
\r
730 asp_core_debug = "0";
\r
731 CPU_Architecture = "nios2";
\r
732 cache_icache_burst_type = "none";
\r
733 include_debug = "0";
\r
734 include_trace = "0";
\r
735 hardware_multiply_uses_les = "0";
\r
736 hardware_multiply_omits_msw = "1";
\r
738 break_slave_override = "";
\r
739 break_offset_override = "0x20";
\r
740 altera_show_unreleased_features = "0";
\r
741 altera_show_unpublished_features = "0";
\r
742 altera_internal_test = "0";
\r
743 alt_log_port_base = "";
\r
744 alt_log_port_type = "";
\r
745 gui_illegal_instructions_trap = "0";
\r
746 atomic_mem_present = "0";
\r
748 fast_intr_present = "0";
\r
749 num_shadow_regs = "0";
\r
750 gui_illegal_memory_access_detection = "0";
\r
751 cache_omit_dcache = "0";
\r
752 cache_omit_icache = "0";
\r
753 omit_instruction_master = "0";
\r
754 omit_data_master = "0";
\r
758 always_bypass_dcache = "0";
\r
759 iss_trace_on = "0";
\r
760 iss_trace_warning = "1";
\r
761 iss_trace_info = "1";
\r
762 iss_trace_disassembly = "0";
\r
763 iss_trace_registers = "0";
\r
764 iss_trace_instr_count = "0";
\r
765 iss_software_debug = "0";
\r
766 iss_software_debug_port = "9996";
\r
767 iss_memory_dump_start = "";
\r
768 iss_memory_dump_end = "";
\r
769 Boot_Copier = "boot_loader_cfi.srec";
\r
770 Boot_Copier_EPCS = "boot_loader_epcs.srec";
\r
771 Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec";
\r
772 Boot_Copier_BE = "boot_loader_cfi_be.srec";
\r
773 Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
\r
774 Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec";
\r
777 CONSTANT __nios_catch_irqs__
\r
780 comment = "Include panic handler for all irqs (needs uart)";
\r
782 CONSTANT __nios_use_constructors__
\r
785 comment = "Call c++ static constructors";
\r
787 CONSTANT __nios_use_small_printf__
\r
790 comment = "Smaller non-ANSI printf, with no floating point";
\r
792 CONSTANT nasys_has_icache
\r
795 comment = "True if instruction cache present";
\r
797 CONSTANT nasys_icache_size
\r
800 comment = "Size in bytes of instruction cache";
\r
802 CONSTANT nasys_icache_line_size
\r
805 comment = "Size in bytes of each icache line";
\r
807 CONSTANT nasys_icache_line_size_log2
\r
810 comment = "Log2 size in bytes of each icache line";
\r
812 CONSTANT nasys_has_dcache
\r
815 comment = "True if instruction cache present";
\r
817 CONSTANT nasys_dcache_size
\r
820 comment = "Size in bytes of data cache";
\r
822 CONSTANT nasys_dcache_line_size
\r
825 comment = "Size in bytes of each dcache line";
\r
827 CONSTANT nasys_dcache_line_size_log2
\r
829 value = "-Infinity";
\r
830 comment = "Log2 size in bytes of each dcache line";
\r
833 license_status = "encrypted";
\r
834 mainmem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";
\r
835 datamem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";
\r
836 maincomm_slave = "uart/s1";
\r
837 germs_monitor_id = "";
\r
839 class = "altera_nios2";
\r
840 class_version = "7.08";
\r
841 SYSTEM_BUILDER_INFO
\r
844 Clock_Source = "clk";
\r
846 Parameters_Signature = "";
\r
848 Instantiate_In_System_Module = "1";
\r
849 Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII";
\r
850 Default_Module_Name = "cpu";
\r
851 Top_Level_Ports_Are_Enumerated = "1";
\r
854 Settings_Summary = "Nios II/s
855 <br> 16-Kbyte Instruction Cache
857 <br> JTAG Debug Module
864 iss_model_name = "altera_nios2";
\r
868 Precompiled_Simulation_Library_Files = "";
\r
869 Simulation_HDL_Files = "";
\r
870 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_0_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_tck.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_sysclk.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu_0.vhd";
\r
871 Synthesis_Only_Files = "";
\r
873 MASTER tightly_coupled_instruction_master_0
\r
878 SYSTEM_BUILDER_INFO
\r
880 Register_Incoming_Signals = "0";
\r
881 Bus_Type = "avalon";
\r
883 Max_Address_Width = "31";
\r
884 Address_Width = "8";
\r
885 Is_Instruction_Master = "1";
\r
888 Is_Big_Endian = "0";
\r
889 Connection_Limit = "1";
\r
893 MASTER tightly_coupled_instruction_master_1
\r
898 SYSTEM_BUILDER_INFO
\r
900 Register_Incoming_Signals = "0";
\r
901 Bus_Type = "avalon";
\r
903 Max_Address_Width = "31";
\r
904 Address_Width = "8";
\r
905 Address_Group = "0";
\r
906 Is_Instruction_Master = "1";
\r
908 Is_Writeable = "0";
\r
911 Is_Big_Endian = "0";
\r
912 Connection_Limit = "1";
\r
916 MASTER tightly_coupled_instruction_master_2
\r
921 SYSTEM_BUILDER_INFO
\r
923 Register_Incoming_Signals = "0";
\r
924 Bus_Type = "avalon";
\r
926 Max_Address_Width = "31";
\r
927 Address_Width = "8";
\r
928 Address_Group = "0";
\r
929 Is_Instruction_Master = "1";
\r
931 Is_Writeable = "0";
\r
934 Is_Big_Endian = "0";
\r
935 Connection_Limit = "1";
\r
939 MASTER tightly_coupled_instruction_master_3
\r
944 SYSTEM_BUILDER_INFO
\r
946 Register_Incoming_Signals = "0";
\r
947 Bus_Type = "avalon";
\r
949 Max_Address_Width = "31";
\r
950 Address_Width = "8";
\r
951 Address_Group = "0";
\r
952 Is_Instruction_Master = "1";
\r
954 Is_Writeable = "0";
\r
957 Is_Big_Endian = "0";
\r
958 Connection_Limit = "1";
\r
962 MASTER data_master2
\r
967 SYSTEM_BUILDER_INFO
\r
969 Register_Incoming_Signals = "1";
\r
970 Bus_Type = "avalon";
\r
972 Max_Address_Width = "31";
\r
973 Address_Width = "8";
\r
974 Address_Group = "0";
\r
975 Is_Data_Master = "1";
\r
977 Is_Writeable = "1";
\r
980 Is_Big_Endian = "0";
\r
983 MASTER tightly_coupled_data_master_0
\r
988 SYSTEM_BUILDER_INFO
\r
990 Register_Incoming_Signals = "0";
\r
991 Bus_Type = "avalon";
\r
993 Max_Address_Width = "31";
\r
994 Address_Width = "8";
\r
995 Address_Group = "0";
\r
996 Is_Data_Master = "1";
\r
998 Is_Writeable = "1";
\r
1001 Is_Big_Endian = "0";
\r
1002 Connection_Limit = "1";
\r
1006 MASTER tightly_coupled_data_master_1
\r
1011 SYSTEM_BUILDER_INFO
\r
1013 Register_Incoming_Signals = "0";
\r
1014 Bus_Type = "avalon";
\r
1015 Data_Width = "32";
\r
1016 Max_Address_Width = "31";
\r
1017 Address_Width = "8";
\r
1018 Address_Group = "0";
\r
1019 Is_Data_Master = "1";
\r
1020 Is_Readable = "1";
\r
1021 Is_Writeable = "1";
\r
1024 Is_Big_Endian = "0";
\r
1025 Connection_Limit = "1";
\r
1029 MASTER tightly_coupled_data_master_2
\r
1034 SYSTEM_BUILDER_INFO
\r
1036 Register_Incoming_Signals = "0";
\r
1037 Bus_Type = "avalon";
\r
1038 Data_Width = "32";
\r
1039 Max_Address_Width = "31";
\r
1040 Address_Width = "8";
\r
1041 Address_Group = "0";
\r
1042 Is_Data_Master = "1";
\r
1043 Is_Readable = "1";
\r
1044 Is_Writeable = "1";
\r
1047 Is_Big_Endian = "0";
\r
1048 Connection_Limit = "1";
\r
1052 MASTER tightly_coupled_data_master_3
\r
1057 SYSTEM_BUILDER_INFO
\r
1059 Register_Incoming_Signals = "0";
\r
1060 Bus_Type = "avalon";
\r
1061 Data_Width = "32";
\r
1062 Max_Address_Width = "31";
\r
1063 Address_Width = "8";
\r
1064 Address_Group = "0";
\r
1065 Is_Data_Master = "1";
\r
1066 Is_Readable = "1";
\r
1067 Is_Writeable = "1";
\r
1070 Is_Big_Endian = "0";
\r
1071 Connection_Limit = "1";
\r
1077 PORT jtag_debug_trigout
\r
1080 direction = "output";
\r
1083 PORT jtag_debug_offchip_trace_clk
\r
1086 direction = "output";
\r
1089 PORT jtag_debug_offchip_trace_data
\r
1092 direction = "output";
\r
1098 direction = "input";
\r
1110 name = "i_readdata";
\r
1111 radix = "hexadecimal";
\r
1116 name = "i_readdatavalid";
\r
1117 radix = "hexadecimal";
\r
1122 name = "i_waitrequest";
\r
1123 radix = "hexadecimal";
\r
1128 name = "i_address";
\r
1129 radix = "hexadecimal";
\r
1135 radix = "hexadecimal";
\r
1141 radix = "hexadecimal";
\r
1147 radix = "hexadecimal";
\r
1152 name = "d_readdata";
\r
1153 radix = "hexadecimal";
\r
1158 name = "d_waitrequest";
\r
1159 radix = "hexadecimal";
\r
1165 radix = "hexadecimal";
\r
1170 name = "d_address";
\r
1171 radix = "hexadecimal";
\r
1176 name = "d_byteenable";
\r
1177 radix = "hexadecimal";
\r
1183 radix = "hexadecimal";
\r
1189 radix = "hexadecimal";
\r
1194 name = "d_writedata";
\r
1195 radix = "hexadecimal";
\r
1199 format = "Divider";
\r
1200 name = "base pipeline";
\r
1207 radix = "hexadecimal";
\r
1213 radix = "hexadecimal";
\r
1219 radix = "hexadecimal";
\r
1224 name = "F_pcb_nxt";
\r
1225 radix = "hexadecimal";
\r
1231 radix = "hexadecimal";
\r
1237 radix = "hexadecimal";
\r
1243 radix = "hexadecimal";
\r
1249 radix = "hexadecimal";
\r
1255 radix = "hexadecimal";
\r
1290 name = "F_inst_ram_hit";
\r
1291 radix = "hexadecimal";
\r
1297 radix = "hexadecimal";
\r
1303 radix = "hexadecimal";
\r
1309 radix = "hexadecimal";
\r
1314 name = "D_refetch";
\r
1315 radix = "hexadecimal";
\r
1321 radix = "hexadecimal";
\r
1327 radix = "hexadecimal";
\r
1333 radix = "hexadecimal";
\r
1339 radix = "hexadecimal";
\r
1345 radix = "hexadecimal";
\r
1350 name = "W_wr_dst_reg";
\r
1351 radix = "hexadecimal";
\r
1356 name = "W_dst_regnum";
\r
1357 radix = "hexadecimal";
\r
1362 name = "W_wr_data";
\r
1363 radix = "hexadecimal";
\r
1369 radix = "hexadecimal";
\r
1375 radix = "hexadecimal";
\r
1381 radix = "hexadecimal";
\r
1387 radix = "hexadecimal";
\r
1393 radix = "hexadecimal";
\r
1399 radix = "hexadecimal";
\r
1405 radix = "hexadecimal";
\r
1410 name = "E_valid_prior_to_hbreak";
\r
1411 radix = "hexadecimal";
\r
1416 name = "M_pipe_flush_nxt";
\r
1417 radix = "hexadecimal";
\r
1422 name = "M_pipe_flush_baddr_nxt";
\r
1423 radix = "hexadecimal";
\r
1428 name = "M_status_reg_pie";
\r
1429 radix = "hexadecimal";
\r
1434 name = "M_ienable_reg";
\r
1435 radix = "hexadecimal";
\r
1440 name = "intr_req";
\r
1441 radix = "hexadecimal";
\r
1446 MODULE onchip_memory
\r
1456 direction = "input";
\r
1463 direction = "input";
\r
1470 direction = "input";
\r
1475 type = "chipselect";
\r
1477 direction = "input";
\r
1484 direction = "input";
\r
1486 default_value = "1'b1";
\r
1492 direction = "input";
\r
1497 type = "readdata";
\r
1499 direction = "output";
\r
1506 direction = "input";
\r
1511 type = "writedata";
\r
1513 direction = "input";
\r
1518 type = "debugaccess";
\r
1520 direction = "input";
\r
1525 type = "byteenable";
\r
1527 direction = "input";
\r
1531 SYSTEM_BUILDER_INFO
\r
1533 Bus_Type = "avalon";
\r
1534 Write_Wait_States = "0cycles";
\r
1535 Read_Wait_States = "0cycles";
\r
1536 Hold_Time = "0cycles";
\r
1537 Setup_Time = "0cycles";
\r
1538 Is_Printable_Device = "0";
\r
1539 Address_Alignment = "dynamic";
\r
1540 Well_Behaved_Waitrequest = "0";
\r
1541 Is_Nonvolatile_Storage = "0";
\r
1542 Address_Span = "8192";
\r
1543 Read_Latency = "1";
\r
1544 Is_Memory_Device = "1";
\r
1545 Maximum_Pending_Read_Transactions = "0";
\r
1546 Minimum_Uninterrupted_Run_Length = "1";
\r
1547 Accepts_Internal_Connections = "1";
\r
1548 Write_Latency = "0";
\r
1550 Data_Width = "32";
\r
1551 Address_Width = "11";
\r
1552 Maximum_Burst_Size = "1";
\r
1553 Register_Incoming_Signals = "0";
\r
1554 Register_Outgoing_Signals = "0";
\r
1555 Interleave_Bursts = "0";
\r
1556 Linewrap_Bursts = "0";
\r
1557 Burst_On_Burst_Boundaries_Only = "0";
\r
1558 Always_Burst_Max_Burst = "0";
\r
1559 Is_Big_Endian = "0";
\r
1561 MASTERED_BY cpu_0/instruction_master
\r
1564 Offset_Address = "0x00904000";
\r
1566 MASTERED_BY cpu_0/data_master
\r
1569 Offset_Address = "0x00904000";
\r
1571 Base_Address = "0x00904000";
\r
1572 Address_Group = "0";
\r
1575 Is_Writable = "1";
\r
1576 IRQ_MASTER cpu_0/data_master
\r
1578 IRQ_Number = "NC";
\r
1582 iss_model_name = "altera_memory";
\r
1583 WIZARD_SCRIPT_ARGUMENTS
\r
1585 allow_mram_sim_contents_only_file = "0";
\r
1586 ram_block_type = "AUTO";
\r
1587 init_contents_file = "onchip_memory";
\r
1588 non_default_init_file_enabled = "0";
\r
1589 gui_ram_block_type = "Automatic";
\r
1592 Size_Value = "8192";
\r
1593 Size_Multiple = "1";
\r
1594 use_shallow_mem_blocks = "0";
\r
1595 init_mem_content = "1";
\r
1596 allow_in_system_memory_content_editor = "0";
\r
1597 instance_id = "NONE";
\r
1598 read_during_write_mode = "DONT_CARE";
\r
1599 ignore_auto_block_type_assignment = "1";
\r
1602 TARGET delete_placeholder_warning
\r
1606 Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
\r
1608 Target_File = "do_delete_placeholder_warning";
\r
1615 Command1 = "@echo Post-processing to create $(notdir $@)";
\r
1616 Command2 = "elf2hex $(ELF) 0x00904000 0x905FFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory.hex --create-lanes=0 ";
\r
1617 Dependency = "$(ELF)";
\r
1618 Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory.hex";
\r
1625 Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
\r
1626 Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
\r
1627 Command3 = "touch $(SIMDIR)/dummy_file";
\r
1628 Dependency = "$(ELF)";
\r
1629 Target_File = "$(SIMDIR)/dummy_file";
\r
1633 contents_info = "";
\r
1641 name = "chipselect";
\r
1642 conditional = "1";
\r
1647 radix = "hexadecimal";
\r
1651 name = "byteenable";
\r
1653 conditional = "1";
\r
1657 name = "readdata";
\r
1658 radix = "hexadecimal";
\r
1663 conditional = "1";
\r
1667 name = "writedata";
\r
1668 radix = "hexadecimal";
\r
1669 conditional = "1";
\r
1673 SYSTEM_BUILDER_INFO
\r
1675 Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
\r
1676 Instantiate_In_System_Module = "1";
\r
1678 Default_Module_Name = "onchip_memory";
\r
1679 Top_Level_Ports_Are_Enumerated = "1";
\r
1680 Clock_Source = "clk";
\r
1689 class = "altera_avalon_onchip_memory2";
\r
1690 class_version = "7.08";
\r
1693 Precompiled_Simulation_Library_Files = "";
\r
1694 Simulation_HDL_Files = "";
\r
1695 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory.vhd";
\r
1696 Synthesis_Only_Files = "";
\r
1703 SYSTEM_BUILDER_INFO
\r
1705 Bus_Type = "avalon";
\r
1706 Is_Memory_Device = "1";
\r
1707 Address_Group = "0";
\r
1708 Address_Alignment = "dynamic";
\r
1709 Address_Width = "11";
\r
1710 Data_Width = "32";
\r
1712 Read_Wait_States = "0";
\r
1713 Write_Wait_States = "0";
\r
1714 Address_Span = "8192";
\r
1715 Read_Latency = "1";
\r
1718 Is_Writable = "1";
\r
1725 MODULE jtag_uart_0
\r
1727 SLAVE avalon_jtag_slave
\r
1735 direction = "input";
\r
1742 direction = "input";
\r
1749 direction = "output";
\r
1752 PORT av_chipselect
\r
1754 type = "chipselect";
\r
1756 direction = "input";
\r
1763 direction = "input";
\r
1770 direction = "input";
\r
1775 type = "readdata";
\r
1777 direction = "output";
\r
1784 direction = "input";
\r
1789 type = "writedata";
\r
1791 direction = "input";
\r
1794 PORT av_waitrequest
\r
1796 type = "waitrequest";
\r
1798 direction = "output";
\r
1801 PORT dataavailable
\r
1803 type = "dataavailable";
\r
1805 direction = "output";
\r
1810 type = "readyfordata";
\r
1812 direction = "output";
\r
1818 direction = "input";
\r
1823 SYSTEM_BUILDER_INFO
\r
1826 Bus_Type = "avalon";
\r
1827 Read_Wait_States = "peripheral_controlled";
\r
1828 Write_Wait_States = "peripheral_controlled";
\r
1829 Hold_Time = "0cycles";
\r
1830 Setup_Time = "0cycles";
\r
1831 Is_Printable_Device = "1";
\r
1832 Address_Alignment = "native";
\r
1833 Well_Behaved_Waitrequest = "0";
\r
1834 Is_Nonvolatile_Storage = "0";
\r
1835 Read_Latency = "0";
\r
1836 Is_Memory_Device = "0";
\r
1837 Maximum_Pending_Read_Transactions = "0";
\r
1838 Minimum_Uninterrupted_Run_Length = "1";
\r
1839 Accepts_Internal_Connections = "1";
\r
1840 Write_Latency = "0";
\r
1842 Data_Width = "32";
\r
1843 Address_Width = "1";
\r
1844 Maximum_Burst_Size = "1";
\r
1845 Register_Incoming_Signals = "0";
\r
1846 Register_Outgoing_Signals = "0";
\r
1847 Interleave_Bursts = "0";
\r
1848 Linewrap_Bursts = "0";
\r
1849 Burst_On_Burst_Boundaries_Only = "0";
\r
1850 Always_Burst_Max_Burst = "0";
\r
1851 Is_Big_Endian = "0";
\r
1853 JTAG_Hub_Base_Id = "262254";
\r
1854 JTAG_Hub_Instance_Id = "0";
\r
1855 Connection_Limit = "1";
\r
1856 MASTERED_BY cpu_0/data_master
\r
1859 Offset_Address = "0x009000d0";
\r
1861 IRQ_MASTER cpu_0/data_master
\r
1865 Base_Address = "0x009000d0";
\r
1866 Address_Group = "0";
\r
1869 class = "altera_avalon_jtag_uart";
\r
1870 class_version = "7.08";
\r
1871 iss_model_name = "altera_avalon_jtag_uart";
\r
1872 WIZARD_SCRIPT_ARGUMENTS
\r
1874 write_depth = "64";
\r
1875 read_depth = "64";
\r
1876 write_threshold = "8";
\r
1877 read_threshold = "8";
\r
1878 read_char_stream = "";
\r
1882 altera_show_unreleased_jtag_uart_features = "0";
\r
1888 SIGNAL av_chipselect
\r
1890 name = "av_chipselect";
\r
1894 name = "av_address";
\r
1895 radix = "hexadecimal";
\r
1899 name = "av_read_n";
\r
1901 SIGNAL av_readdata
\r
1903 name = "av_readdata";
\r
1904 radix = "hexadecimal";
\r
1908 name = "av_write_n";
\r
1910 SIGNAL av_writedata
\r
1912 name = "av_writedata";
\r
1913 radix = "hexadecimal";
\r
1915 SIGNAL av_waitrequest
\r
1917 name = "av_waitrequest";
\r
1919 SIGNAL dataavailable
\r
1921 name = "dataavailable";
\r
1923 SIGNAL readyfordata
\r
1925 name = "readyfordata";
\r
1932 INTERACTIVE_IN drive
\r
1935 file = "_input_data_stream.dat";
\r
1936 mutex = "_input_data_mutex.dat";
\r
1939 signals = "temp,list";
\r
1940 exe = "nios2-terminal";
\r
1942 INTERACTIVE_OUT log
\r
1945 exe = "perl -- atail-f.pl";
\r
1946 file = "_output_stream.dat";
\r
1948 signals = "temp,list";
\r
1952 SYSTEM_BUILDER_INFO
\r
1955 Clock_Source = "clk";
\r
1957 Instantiate_In_System_Module = "1";
\r
1958 Iss_Launch_Telnet = "0";
\r
1959 Top_Level_Ports_Are_Enumerated = "1";
\r
1965 Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
1966 <br>Read Depth: 64; Read IRQ Threshold: 8";
\r
1971 Precompiled_Simulation_Library_Files = "";
\r
1972 Simulation_HDL_Files = "";
\r
1973 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.vhd";
\r
1974 Synthesis_Only_Files = "";
\r
1990 direction = "input";
\r
1997 direction = "input";
\r
2004 direction = "input";
\r
2009 type = "byteenable_n";
\r
2011 direction = "input";
\r
2016 type = "chipselect";
\r
2018 direction = "input";
\r
2023 type = "writedata";
\r
2025 direction = "input";
\r
2032 direction = "input";
\r
2039 direction = "input";
\r
2044 type = "readdata";
\r
2046 direction = "output";
\r
2051 type = "readdatavalid";
\r
2053 direction = "output";
\r
2056 PORT za_waitrequest
\r
2058 type = "waitrequest";
\r
2060 direction = "output";
\r
2065 direction = "output";
\r
2071 direction = "output";
\r
2077 direction = "output";
\r
2083 direction = "output";
\r
2089 direction = "output";
\r
2095 direction = "inout";
\r
2101 direction = "output";
\r
2107 direction = "output";
\r
2113 direction = "output";
\r
2118 SYSTEM_BUILDER_INFO
\r
2120 Bus_Type = "avalon";
\r
2121 Read_Wait_States = "peripheral_controlled";
\r
2122 Write_Wait_States = "peripheral_controlled";
\r
2123 Hold_Time = "0cycles";
\r
2124 Setup_Time = "0cycles";
\r
2125 Is_Printable_Device = "0";
\r
2126 Address_Alignment = "dynamic";
\r
2127 Well_Behaved_Waitrequest = "0";
\r
2128 Is_Nonvolatile_Storage = "0";
\r
2129 Address_Span = "16777216";
\r
2130 Read_Latency = "0";
\r
2131 Is_Memory_Device = "1";
\r
2132 Maximum_Pending_Read_Transactions = "6";
\r
2133 Minimum_Uninterrupted_Run_Length = "1";
\r
2134 Accepts_Internal_Connections = "1";
\r
2135 Write_Latency = "0";
\r
2137 Data_Width = "32";
\r
2138 Address_Width = "22";
\r
2139 Maximum_Burst_Size = "1";
\r
2140 Register_Incoming_Signals = "0";
\r
2141 Register_Outgoing_Signals = "0";
\r
2142 Interleave_Bursts = "0";
\r
2143 Linewrap_Bursts = "0";
\r
2144 Burst_On_Burst_Boundaries_Only = "0";
\r
2145 Always_Burst_Max_Burst = "0";
\r
2146 Is_Big_Endian = "0";
\r
2148 MASTERED_BY cpu_0/instruction_master
\r
2151 Offset_Address = "0x01000000";
\r
2153 MASTERED_BY cpu_0/data_master
\r
2156 Offset_Address = "0x01000000";
\r
2158 Base_Address = "0x01000000";
\r
2160 Simulation_Num_Lanes = "1";
\r
2161 Address_Group = "0";
\r
2162 IRQ_MASTER cpu_0/data_master
\r
2164 IRQ_Number = "NC";
\r
2174 direction = "output";
\r
2181 direction = "output";
\r
2188 direction = "output";
\r
2195 direction = "output";
\r
2202 direction = "output";
\r
2209 direction = "output";
\r
2216 direction = "output";
\r
2223 direction = "output";
\r
2230 direction = "output";
\r
2234 iss_model_name = "altera_memory";
\r
2235 WIZARD_SCRIPT_ARGUMENTS
\r
2237 register_data_in = "1";
\r
2238 sim_model_base = "0";
\r
2239 sdram_data_width = "32";
\r
2240 sdram_addr_width = "12";
\r
2241 sdram_row_width = "12";
\r
2242 sdram_col_width = "8";
\r
2243 sdram_num_chipselects = "1";
\r
2244 sdram_num_banks = "4";
\r
2245 refresh_period = "15.625";
\r
2246 powerup_delay = "100.0";
\r
2247 cas_latency = "2";
\r
2254 init_refresh_commands = "2";
\r
2255 init_nop_delay = "0.0";
\r
2256 shared_data = "0";
\r
2257 sdram_bank_width = "2";
\r
2258 tristate_bridge_slave = "";
\r
2259 starvation_indicator = "0";
\r
2260 is_initialized = "1";
\r
2269 radix = "hexadecimal";
\r
2274 radix = "hexadecimal";
\r
2283 radix = "hexadecimal";
\r
2296 radix = "hexadecimal";
\r
2300 name = "za_valid";
\r
2304 name = "za_waitrequest";
\r
2317 name = "za_cannotrefresh";
\r
2323 radix = "hexadecimal";
\r
2329 radix = "hexadecimal";
\r
2335 radix = "hexadecimal";
\r
2340 name = "zs_ras_n";
\r
2345 name = "zs_cas_n";
\r
2356 radix = "hexadecimal";
\r
2362 radix = "hexadecimal";
\r
2368 radix = "hexadecimal";
\r
2374 radix = "hexadecimal";
\r
2389 name = "zt_chipselect";
\r
2394 name = "zt_lock_n";
\r
2399 name = "zt_ras_n";
\r
2404 name = "zt_cas_n";
\r
2415 radix = "hexadecimal";
\r
2421 radix = "hexadecimal";
\r
2427 radix = "hexadecimal";
\r
2433 radix = "hexadecimal";
\r
2438 name = "tz_waitrequest";
\r
2444 SYSTEM_BUILDER_INFO
\r
2446 Instantiate_In_System_Module = "1";
\r
2448 Default_Module_Name = "sdram";
\r
2449 Top_Level_Ports_Are_Enumerated = "1";
\r
2450 Clock_Source = "clk";
\r
2452 Disable_Simulation_Port_Wiring = "0";
\r
2458 Settings_Summary = "4194304 x 32<br>
2459 Memory size: 16 MBytes<br>
2464 class = "altera_avalon_new_sdram_controller";
\r
2465 class_version = "7.08";
\r
2468 Precompiled_Simulation_Library_Files = "";
\r
2469 Simulation_HDL_Files = "";
\r
2470 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.vhd";
\r
2471 Synthesis_Only_Files = "";
\r
2476 SLAVE control_slave
\r
2484 direction = "input";
\r
2491 direction = "input";
\r
2498 direction = "input";
\r
2503 type = "readdata";
\r
2505 direction = "output";
\r
2509 SYSTEM_BUILDER_INFO
\r
2511 Bus_Type = "avalon";
\r
2512 Write_Wait_States = "0cycles";
\r
2513 Read_Wait_States = "1cycles";
\r
2514 Hold_Time = "0cycles";
\r
2515 Setup_Time = "0cycles";
\r
2516 Is_Printable_Device = "0";
\r
2517 Address_Alignment = "native";
\r
2518 Well_Behaved_Waitrequest = "0";
\r
2519 Is_Nonvolatile_Storage = "0";
\r
2520 Read_Latency = "0";
\r
2521 Is_Memory_Device = "0";
\r
2522 Maximum_Pending_Read_Transactions = "0";
\r
2523 Minimum_Uninterrupted_Run_Length = "1";
\r
2524 Accepts_Internal_Connections = "1";
\r
2525 Write_Latency = "0";
\r
2527 Data_Width = "32";
\r
2528 Address_Width = "1";
\r
2529 Maximum_Burst_Size = "1";
\r
2530 Register_Incoming_Signals = "0";
\r
2531 Register_Outgoing_Signals = "0";
\r
2532 Interleave_Bursts = "0";
\r
2533 Linewrap_Bursts = "0";
\r
2534 Burst_On_Burst_Boundaries_Only = "0";
\r
2535 Always_Burst_Max_Burst = "0";
\r
2536 Is_Big_Endian = "0";
\r
2538 MASTERED_BY cpu_0/data_master
\r
2541 Offset_Address = "0x009000d8";
\r
2543 Base_Address = "0x009000d8";
\r
2545 Address_Group = "0";
\r
2546 IRQ_MASTER cpu_0/data_master
\r
2548 IRQ_Number = "NC";
\r
2552 class = "altera_avalon_sysid";
\r
2553 class_version = "7.08";
\r
2554 SYSTEM_BUILDER_INFO
\r
2556 Date_Modified = "";
\r
2558 Instantiate_In_System_Module = "1";
\r
2559 Fixed_Module_Name = "sysid";
\r
2560 Top_Level_Ports_Are_Enumerated = "1";
\r
2561 Clock_Source = "clk";
\r
2565 Settings_Summary = "System ID (at last Generate):<br> <b>2A1C5786</b> (unique ID tag) <br> <b>485BC1C0</b> (timestamp: Fri Jun 20, 2008 @4:42 PM)";
\r
2571 WIZARD_SCRIPT_ARGUMENTS
\r
2573 id = "706500486u";
\r
2574 timestamp = "1213972928u";
\r
2575 regenerate_values = "0";
\r
2578 TARGET verifysysid
\r
2582 All_Depends_On = "0";
\r
2583 Command = "nios2-download $(JTAG_CABLE) --sidp=0x009000d8 --id=706500486 --timestamp=1213972928";
\r
2585 Target_File = "dummy_verifysysid_file";
\r
2592 Precompiled_Simulation_Library_Files = "";
\r
2593 Simulation_HDL_Files = "";
\r
2594 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";
\r
2595 Synthesis_Only_Files = "";
\r
2611 direction = "input";
\r
2618 direction = "input";
\r
2625 direction = "input";
\r
2632 direction = "input";
\r
2637 type = "writedata";
\r
2639 direction = "input";
\r
2644 type = "chipselect";
\r
2646 direction = "input";
\r
2650 SYSTEM_BUILDER_INFO
\r
2652 Bus_Type = "avalon";
\r
2653 Write_Wait_States = "0cycles";
\r
2654 Read_Wait_States = "1cycles";
\r
2655 Hold_Time = "0cycles";
\r
2656 Setup_Time = "0cycles";
\r
2657 Is_Printable_Device = "0";
\r
2658 Address_Alignment = "native";
\r
2659 Well_Behaved_Waitrequest = "0";
\r
2660 Is_Nonvolatile_Storage = "0";
\r
2661 Read_Latency = "0";
\r
2662 Is_Memory_Device = "0";
\r
2663 Maximum_Pending_Read_Transactions = "0";
\r
2664 Minimum_Uninterrupted_Run_Length = "1";
\r
2665 Accepts_Internal_Connections = "1";
\r
2666 Write_Latency = "0";
\r
2669 Address_Width = "2";
\r
2670 Maximum_Burst_Size = "1";
\r
2671 Register_Incoming_Signals = "0";
\r
2672 Register_Outgoing_Signals = "0";
\r
2673 Interleave_Bursts = "0";
\r
2674 Linewrap_Bursts = "0";
\r
2675 Burst_On_Burst_Boundaries_Only = "0";
\r
2676 Always_Burst_Max_Burst = "0";
\r
2677 Is_Big_Endian = "0";
\r
2679 MASTERED_BY cpu_0/data_master
\r
2682 Offset_Address = "0x00900080";
\r
2684 Base_Address = "0x00900080";
\r
2686 Address_Group = "0";
\r
2687 IRQ_MASTER cpu_0/data_master
\r
2689 IRQ_Number = "NC";
\r
2691 Is_Readable = "0";
\r
2692 Is_Writable = "1";
\r
2701 direction = "output";
\r
2706 direction = "input";
\r
2712 direction = "inout";
\r
2717 class = "altera_avalon_pio";
\r
2718 class_version = "7.08";
\r
2719 SYSTEM_BUILDER_INFO
\r
2722 Instantiate_In_System_Module = "1";
\r
2723 Wire_Test_Bench_Values = "1";
\r
2724 Top_Level_Ports_Are_Enumerated = "1";
\r
2725 Clock_Source = "clk";
\r
2727 Date_Modified = "";
\r
2733 Settings_Summary = " 8-bit PIO using <br>
2739 WIZARD_SCRIPT_ARGUMENTS
\r
2741 Do_Test_Bench_Wiring = "0";
\r
2742 Driven_Sim_Value = "0";
\r
2748 reset_value = "0";
\r
2749 edge_type = "NONE";
\r
2750 irq_type = "NONE";
\r
2751 bit_clearing_edge_register = "0";
\r
2755 Precompiled_Simulation_Library_Files = "";
\r
2756 Simulation_HDL_Files = "";
\r
2757 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LED_Pio.vhd";
\r
2758 Synthesis_Only_Files = "";
\r
2771 direction = "input";
\r
2778 direction = "input";
\r
2785 direction = "input";
\r
2792 direction = "input";
\r
2797 type = "writedata";
\r
2799 direction = "input";
\r
2804 type = "chipselect";
\r
2806 direction = "input";
\r
2810 SYSTEM_BUILDER_INFO
\r
2812 Bus_Type = "avalon";
\r
2813 Write_Wait_States = "0cycles";
\r
2814 Read_Wait_States = "1cycles";
\r
2815 Hold_Time = "0cycles";
\r
2816 Setup_Time = "0cycles";
\r
2817 Is_Printable_Device = "0";
\r
2818 Address_Alignment = "native";
\r
2819 Well_Behaved_Waitrequest = "0";
\r
2820 Is_Nonvolatile_Storage = "0";
\r
2821 Read_Latency = "0";
\r
2822 Is_Memory_Device = "0";
\r
2823 Maximum_Pending_Read_Transactions = "0";
\r
2824 Minimum_Uninterrupted_Run_Length = "1";
\r
2825 Accepts_Internal_Connections = "1";
\r
2826 Write_Latency = "0";
\r
2828 Data_Width = "14";
\r
2829 Address_Width = "2";
\r
2830 Maximum_Burst_Size = "1";
\r
2831 Register_Incoming_Signals = "0";
\r
2832 Register_Outgoing_Signals = "0";
\r
2833 Interleave_Bursts = "0";
\r
2834 Linewrap_Bursts = "0";
\r
2835 Burst_On_Burst_Boundaries_Only = "0";
\r
2836 Always_Burst_Max_Burst = "0";
\r
2837 Is_Big_Endian = "0";
\r
2839 MASTERED_BY cpu_0/data_master
\r
2842 Offset_Address = "0x00900090";
\r
2844 Base_Address = "0x00900090";
\r
2846 Address_Group = "0";
\r
2847 IRQ_MASTER cpu_0/data_master
\r
2849 IRQ_Number = "NC";
\r
2851 Is_Readable = "0";
\r
2852 Is_Writable = "1";
\r
2861 direction = "output";
\r
2866 direction = "input";
\r
2872 direction = "inout";
\r
2877 class = "altera_avalon_pio";
\r
2878 class_version = "7.08";
\r
2879 SYSTEM_BUILDER_INFO
\r
2882 Instantiate_In_System_Module = "1";
\r
2883 Wire_Test_Bench_Values = "1";
\r
2884 Top_Level_Ports_Are_Enumerated = "1";
\r
2885 Clock_Source = "clk";
\r
2887 Date_Modified = "";
\r
2893 Settings_Summary = " 14-bit PIO using <br>
2899 WIZARD_SCRIPT_ARGUMENTS
\r
2901 Do_Test_Bench_Wiring = "0";
\r
2902 Driven_Sim_Value = "0";
\r
2907 Data_Width = "14";
\r
2908 reset_value = "0";
\r
2909 edge_type = "NONE";
\r
2910 irq_type = "NONE";
\r
2911 bit_clearing_edge_register = "0";
\r
2915 Precompiled_Simulation_Library_Files = "";
\r
2916 Simulation_HDL_Files = "";
\r
2917 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SG_Pio.vhd";
\r
2918 Synthesis_Only_Files = "";
\r
2931 direction = "input";
\r
2938 direction = "input";
\r
2945 direction = "input";
\r
2952 direction = "input";
\r
2957 type = "writedata";
\r
2959 direction = "input";
\r
2964 type = "chipselect";
\r
2966 direction = "input";
\r
2971 type = "readdata";
\r
2973 direction = "output";
\r
2977 SYSTEM_BUILDER_INFO
\r
2979 Bus_Type = "avalon";
\r
2980 Write_Wait_States = "0cycles";
\r
2981 Read_Wait_States = "1cycles";
\r
2982 Hold_Time = "0cycles";
\r
2983 Setup_Time = "0cycles";
\r
2984 Is_Printable_Device = "0";
\r
2985 Address_Alignment = "native";
\r
2986 Well_Behaved_Waitrequest = "0";
\r
2987 Is_Nonvolatile_Storage = "0";
\r
2988 Read_Latency = "0";
\r
2989 Is_Memory_Device = "0";
\r
2990 Maximum_Pending_Read_Transactions = "0";
\r
2991 Minimum_Uninterrupted_Run_Length = "1";
\r
2992 Accepts_Internal_Connections = "1";
\r
2993 Write_Latency = "0";
\r
2995 Data_Width = "32";
\r
2996 Address_Width = "2";
\r
2997 Maximum_Burst_Size = "1";
\r
2998 Register_Incoming_Signals = "0";
\r
2999 Register_Outgoing_Signals = "0";
\r
3000 Interleave_Bursts = "0";
\r
3001 Linewrap_Bursts = "0";
\r
3002 Burst_On_Burst_Boundaries_Only = "0";
\r
3003 Always_Burst_Max_Burst = "0";
\r
3004 Is_Big_Endian = "0";
\r
3006 MASTERED_BY cpu_0/data_master
\r
3009 Offset_Address = "0x009000a0";
\r
3011 Base_Address = "0x009000a0";
\r
3013 Address_Group = "0";
\r
3014 IRQ_MASTER cpu_0/data_master
\r
3016 IRQ_Number = "NC";
\r
3018 Is_Readable = "1";
\r
3019 Is_Writable = "1";
\r
3028 direction = "inout";
\r
3033 direction = "input";
\r
3039 direction = "output";
\r
3044 class = "altera_avalon_pio";
\r
3045 class_version = "7.08";
\r
3046 SYSTEM_BUILDER_INFO
\r
3049 Instantiate_In_System_Module = "1";
\r
3050 Wire_Test_Bench_Values = "1";
\r
3051 Top_Level_Ports_Are_Enumerated = "1";
\r
3052 Clock_Source = "clk";
\r
3054 Date_Modified = "";
\r
3060 Settings_Summary = " 32-bit PIO using <br>
3061 tri-state pins with edge type NONE and interrupt source NONE
3066 WIZARD_SCRIPT_ARGUMENTS
\r
3068 Do_Test_Bench_Wiring = "0";
\r
3069 Driven_Sim_Value = "0";
\r
3074 Data_Width = "32";
\r
3075 reset_value = "0";
\r
3076 edge_type = "NONE";
\r
3077 irq_type = "NONE";
\r
3078 bit_clearing_edge_register = "0";
\r
3082 Precompiled_Simulation_Library_Files = "";
\r
3083 Simulation_HDL_Files = "";
\r
3084 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/IO_Pio.vhd";
\r
3085 Synthesis_Only_Files = "";
\r
3098 direction = "input";
\r
3105 direction = "input";
\r
3112 direction = "input";
\r
3117 type = "readdata";
\r
3119 direction = "output";
\r
3123 SYSTEM_BUILDER_INFO
\r
3125 Bus_Type = "avalon";
\r
3126 Write_Wait_States = "0cycles";
\r
3127 Read_Wait_States = "1cycles";
\r
3128 Hold_Time = "0cycles";
\r
3129 Setup_Time = "0cycles";
\r
3130 Is_Printable_Device = "0";
\r
3131 Address_Alignment = "native";
\r
3132 Well_Behaved_Waitrequest = "0";
\r
3133 Is_Nonvolatile_Storage = "0";
\r
3134 Read_Latency = "0";
\r
3135 Is_Memory_Device = "0";
\r
3136 Maximum_Pending_Read_Transactions = "0";
\r
3137 Minimum_Uninterrupted_Run_Length = "1";
\r
3138 Accepts_Internal_Connections = "1";
\r
3139 Write_Latency = "0";
\r
3142 Address_Width = "2";
\r
3143 Maximum_Burst_Size = "1";
\r
3144 Register_Incoming_Signals = "0";
\r
3145 Register_Outgoing_Signals = "0";
\r
3146 Interleave_Bursts = "0";
\r
3147 Linewrap_Bursts = "0";
\r
3148 Burst_On_Burst_Boundaries_Only = "0";
\r
3149 Always_Burst_Max_Burst = "0";
\r
3150 Is_Big_Endian = "0";
\r
3152 MASTERED_BY cpu_0/data_master
\r
3155 Offset_Address = "0x009000b0";
\r
3157 Base_Address = "0x009000b0";
\r
3159 Address_Group = "0";
\r
3160 IRQ_MASTER cpu_0/data_master
\r
3162 IRQ_Number = "NC";
\r
3164 Is_Readable = "1";
\r
3165 Is_Writable = "0";
\r
3174 direction = "input";
\r
3179 direction = "output";
\r
3185 direction = "inout";
\r
3190 class = "altera_avalon_pio";
\r
3191 class_version = "7.08";
\r
3192 SYSTEM_BUILDER_INFO
\r
3195 Instantiate_In_System_Module = "1";
\r
3196 Wire_Test_Bench_Values = "1";
\r
3197 Top_Level_Ports_Are_Enumerated = "1";
\r
3198 Clock_Source = "clk";
\r
3200 Date_Modified = "";
\r
3206 Settings_Summary = " 9-bit PIO using <br>
3208 input pins with edge type NONE and interrupt source NONE
3212 WIZARD_SCRIPT_ARGUMENTS
\r
3214 Do_Test_Bench_Wiring = "0";
\r
3215 Driven_Sim_Value = "0";
\r
3221 reset_value = "0";
\r
3222 edge_type = "NONE";
\r
3223 irq_type = "NONE";
\r
3224 bit_clearing_edge_register = "0";
\r
3228 Precompiled_Simulation_Library_Files = "";
\r
3229 Simulation_HDL_Files = "";
\r
3230 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Button_Pio.vhd";
\r
3231 Synthesis_Only_Files = "";
\r
3244 direction = "input";
\r
3251 direction = "input";
\r
3258 direction = "output";
\r
3265 direction = "input";
\r
3268 PORT begintransfer
\r
3270 type = "begintransfer";
\r
3272 direction = "input";
\r
3277 type = "chipselect";
\r
3279 direction = "input";
\r
3286 direction = "input";
\r
3293 direction = "input";
\r
3298 type = "writedata";
\r
3300 direction = "input";
\r
3305 type = "readdata";
\r
3307 direction = "output";
\r
3310 PORT dataavailable
\r
3312 type = "dataavailable";
\r
3314 direction = "output";
\r
3319 type = "readyfordata";
\r
3321 direction = "output";
\r
3325 SYSTEM_BUILDER_INFO
\r
3328 Bus_Type = "avalon";
\r
3329 Write_Wait_States = "1cycles";
\r
3330 Read_Wait_States = "1cycles";
\r
3331 Hold_Time = "0cycles";
\r
3332 Setup_Time = "0cycles";
\r
3333 Is_Printable_Device = "1";
\r
3334 Address_Alignment = "native";
\r
3335 Well_Behaved_Waitrequest = "0";
\r
3336 Is_Nonvolatile_Storage = "0";
\r
3337 Read_Latency = "0";
\r
3338 Is_Memory_Device = "0";
\r
3339 Maximum_Pending_Read_Transactions = "0";
\r
3340 Minimum_Uninterrupted_Run_Length = "1";
\r
3341 Accepts_Internal_Connections = "1";
\r
3342 Write_Latency = "0";
\r
3344 Data_Width = "16";
\r
3345 Address_Width = "3";
\r
3346 Maximum_Burst_Size = "1";
\r
3347 Register_Incoming_Signals = "0";
\r
3348 Register_Outgoing_Signals = "0";
\r
3349 Interleave_Bursts = "0";
\r
3350 Linewrap_Bursts = "0";
\r
3351 Burst_On_Burst_Boundaries_Only = "0";
\r
3352 Always_Burst_Max_Burst = "0";
\r
3353 Is_Big_Endian = "0";
\r
3355 MASTERED_BY cpu_0/data_master
\r
3358 Offset_Address = "0x00900040";
\r
3360 IRQ_MASTER cpu_0/data_master
\r
3364 Base_Address = "0x00900040";
\r
3365 Address_Group = "0";
\r
3374 direction = "input";
\r
3381 direction = "output";
\r
3386 direction = "input";
\r
3392 direction = "output";
\r
3397 class = "altera_avalon_uart";
\r
3398 class_version = "7.08";
\r
3399 iss_model_name = "altera_avalon_uart";
\r
3400 SYSTEM_BUILDER_INFO
\r
3402 Instantiate_In_System_Module = "1";
\r
3404 Iss_Launch_Telnet = "0";
\r
3405 Top_Level_Ports_Are_Enumerated = "1";
\r
3408 Settings_Summary = "8-bit UART with 115200 baud, <br>
3409 1 stop bits and N parity";
\r
3410 Is_Collapsed = "1";
\r
3415 Clock_Source = "clk";
\r
3424 name = " Bus Interface";
\r
3425 format = "Divider";
\r
3429 name = "chipselect";
\r
3434 radix = "hexadecimal";
\r
3438 name = "writedata";
\r
3439 radix = "hexadecimal";
\r
3443 name = "readdata";
\r
3444 radix = "hexadecimal";
\r
3448 name = " Internals";
\r
3449 format = "Divider";
\r
3453 name = "tx_ready";
\r
3462 name = "rx_char_ready";
\r
3470 INTERACTIVE_OUT log
\r
3473 file = "_log_module.txt";
\r
3475 signals = "temp,list";
\r
3476 exe = "perl -- tail-f.pl";
\r
3478 INTERACTIVE_IN drive
\r
3481 file = "_input_data_stream.dat";
\r
3482 mutex = "_input_data_mutex.dat";
\r
3485 signals = "temp,list";
\r
3486 exe = "perl -- uart.pl";
\r
3489 WIZARD_SCRIPT_ARGUMENTS
\r
3496 use_cts_rts = "0";
\r
3497 use_eop_register = "0";
\r
3498 sim_true_baud = "0";
\r
3499 sim_char_stream = "";
\r
3503 Precompiled_Simulation_Library_Files = "";
\r
3504 Simulation_HDL_Files = "";
\r
3505 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart.vhd";
\r
3506 Synthesis_Only_Files = "";
\r
3519 direction = "input";
\r
3526 direction = "input";
\r
3533 direction = "input";
\r
3540 direction = "input";
\r
3545 type = "writedata";
\r
3547 direction = "input";
\r
3552 type = "chipselect";
\r
3554 direction = "input";
\r
3559 type = "readdata";
\r
3561 direction = "output";
\r
3565 SYSTEM_BUILDER_INFO
\r
3567 Bus_Type = "avalon";
\r
3568 Write_Wait_States = "0cycles";
\r
3569 Read_Wait_States = "1cycles";
\r
3570 Hold_Time = "0cycles";
\r
3571 Setup_Time = "0cycles";
\r
3572 Is_Printable_Device = "0";
\r
3573 Address_Alignment = "native";
\r
3574 Well_Behaved_Waitrequest = "0";
\r
3575 Is_Nonvolatile_Storage = "0";
\r
3576 Read_Latency = "0";
\r
3577 Is_Memory_Device = "0";
\r
3578 Maximum_Pending_Read_Transactions = "0";
\r
3579 Minimum_Uninterrupted_Run_Length = "1";
\r
3580 Accepts_Internal_Connections = "1";
\r
3581 Write_Latency = "0";
\r
3584 Address_Width = "2";
\r
3585 Maximum_Burst_Size = "1";
\r
3586 Register_Incoming_Signals = "0";
\r
3587 Register_Outgoing_Signals = "0";
\r
3588 Interleave_Bursts = "0";
\r
3589 Linewrap_Bursts = "0";
\r
3590 Burst_On_Burst_Boundaries_Only = "0";
\r
3591 Always_Burst_Max_Burst = "0";
\r
3592 Is_Big_Endian = "0";
\r
3594 MASTERED_BY cpu_0/data_master
\r
3597 Offset_Address = "0x009000c0";
\r
3599 Base_Address = "0x009000c0";
\r
3601 Address_Group = "0";
\r
3602 IRQ_MASTER cpu_0/data_master
\r
3604 IRQ_Number = "NC";
\r
3606 Is_Readable = "1";
\r
3607 Is_Writable = "1";
\r
3616 direction = "inout";
\r
3621 direction = "input";
\r
3627 direction = "output";
\r
3632 class = "altera_avalon_pio";
\r
3633 class_version = "7.08";
\r
3634 SYSTEM_BUILDER_INFO
\r
3637 Instantiate_In_System_Module = "1";
\r
3638 Wire_Test_Bench_Values = "1";
\r
3639 Top_Level_Ports_Are_Enumerated = "1";
\r
3640 Clock_Source = "clk";
\r
3642 Date_Modified = "";
\r
3648 Settings_Summary = " 3-bit PIO using <br>
3649 tri-state pins with edge type NONE and interrupt source NONE
3654 WIZARD_SCRIPT_ARGUMENTS
\r
3656 Do_Test_Bench_Wiring = "0";
\r
3657 Driven_Sim_Value = "0";
\r
3663 reset_value = "0";
\r
3664 edge_type = "NONE";
\r
3665 irq_type = "NONE";
\r
3666 bit_clearing_edge_register = "0";
\r
3670 Precompiled_Simulation_Library_Files = "";
\r
3671 Simulation_HDL_Files = "";
\r
3672 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LM74_Pio.vhd";
\r
3673 Synthesis_Only_Files = "";
\r
3676 MODULE epcs_controller
\r
3678 SLAVE epcs_control_port
\r
3686 direction = "input";
\r
3693 direction = "input";
\r
3700 direction = "output";
\r
3707 direction = "input";
\r
3712 type = "chipselect";
\r
3714 direction = "input";
\r
3717 PORT dataavailable
\r
3719 type = "dataavailable";
\r
3721 direction = "output";
\r
3726 type = "endofpacket";
\r
3728 direction = "output";
\r
3735 direction = "input";
\r
3740 type = "readdata";
\r
3742 direction = "output";
\r
3747 type = "readyfordata";
\r
3749 direction = "output";
\r
3756 direction = "input";
\r
3761 type = "writedata";
\r
3763 direction = "input";
\r
3766 PORT data_from_cpu
\r
3769 direction = "input";
\r
3770 type = "writedata";
\r
3776 direction = "output";
\r
3777 type = "readdata";
\r
3783 direction = "input";
\r
3784 type = "chipselect";
\r
3790 direction = "input";
\r
3795 SYSTEM_BUILDER_INFO
\r
3798 Bus_Type = "avalon";
\r
3799 Write_Wait_States = "1cycles";
\r
3800 Read_Wait_States = "1cycles";
\r
3801 Hold_Time = "0cycles";
\r
3802 Setup_Time = "0cycles";
\r
3803 Is_Printable_Device = "0";
\r
3804 Address_Alignment = "dynamic";
\r
3805 Well_Behaved_Waitrequest = "0";
\r
3806 Is_Nonvolatile_Storage = "1";
\r
3807 Address_Span = "2048";
\r
3808 Read_Latency = "0";
\r
3809 Is_Memory_Device = "1";
\r
3810 Maximum_Pending_Read_Transactions = "0";
\r
3811 Minimum_Uninterrupted_Run_Length = "1";
\r
3812 Accepts_Internal_Connections = "1";
\r
3813 Write_Latency = "0";
\r
3815 Data_Width = "32";
\r
3816 Address_Width = "9";
\r
3817 Maximum_Burst_Size = "1";
\r
3818 Register_Incoming_Signals = "0";
\r
3819 Register_Outgoing_Signals = "0";
\r
3820 Interleave_Bursts = "0";
\r
3821 Linewrap_Bursts = "0";
\r
3822 Burst_On_Burst_Boundaries_Only = "0";
\r
3823 Always_Burst_Max_Burst = "0";
\r
3824 Is_Big_Endian = "0";
\r
3826 MASTERED_BY cpu_0/instruction_master
\r
3829 Offset_Address = "0x00906000";
\r
3831 MASTERED_BY cpu_0/data_master
\r
3834 Offset_Address = "0x00906000";
\r
3836 IRQ_MASTER cpu_0/data_master
\r
3840 Base_Address = "0x00906000";
\r
3841 Address_Group = "0";
\r
3843 WIZARD_SCRIPT_ARGUMENTS
\r
3845 class = "altera_avalon_epcs_flash_controller";
\r
3846 flash_reference_designator = "";
\r
3855 direction = "output";
\r
3862 direction = "output";
\r
3869 direction = "output";
\r
3876 direction = "input";
\r
3880 WIZARD_SCRIPT_ARGUMENTS
\r
3883 targetclock = "20";
\r
3884 clockunits = "MHz";
\r
3885 clockmult = "1000000";
\r
3888 clockpolarity = "0";
\r
3892 targetssdelay = "100";
\r
3893 delayunits = "us";
\r
3894 delaymult = "1e-006";
\r
3896 register_offset = "0x400";
\r
3897 use_asmi_atom = "0";
\r
3902 EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)";
\r
3903 EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
\r
3909 BOOTS_FROM_EPCS = "0";
\r
3910 BOOT_COPIER_EPCS = "boot_loader_epcs.srec";
\r
3911 CPU_CLASS = "altera_nios2";
\r
3912 CPU_RESET_ADDRESS = "0x0";
\r
3915 TARGET delete_placeholder_warning
\r
3919 Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
\r
3921 Target_File = "do_delete_placeholder_warning";
\r
3928 Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS)$(DBL_QUOTE) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF ; fi";
\r
3929 Dependency = "$(ELF)";
\r
3930 Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
\r
3937 Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
\r
3938 Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
\r
3939 Command3 = "touch $(SIMDIR)/dummy_file";
\r
3940 Dependency = "$(ELF)";
\r
3941 Target_File = "$(SIMDIR)/dummy_file";
\r
3945 clockunit = "kHz";
\r
3948 class = "altera_avalon_epcs_flash_controller";
\r
3949 class_version = "7.08";
\r
3950 SYSTEM_BUILDER_INFO
\r
3953 Clock_Source = "clk";
\r
3955 Instantiate_In_System_Module = "1";
\r
3956 Required_Device_Family = "STRATIX,CYCLONE,CYCLONEII,CYCLONEIII,STRATIXIII,STRATIXII,STRATIXIIGX,ARRIAGX,STRATIXIIGXLITE";
\r
3957 Fixed_Module_Name = "epcs_controller";
\r
3958 Top_Level_Ports_Are_Enumerated = "1";
\r
3968 Precompiled_Simulation_Library_Files = "";
\r
3969 Simulation_HDL_Files = "";
\r
3970 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs_controller.vhd";
\r
3971 Synthesis_Only_Files = "";
\r
3974 MODULE tri_state_bridge_0
\r
3976 SLAVE avalon_slave
\r
3981 SYSTEM_BUILDER_INFO
\r
3983 Bus_Type = "avalon";
\r
3984 Write_Wait_States = "0cycles";
\r
3985 Read_Wait_States = "1cycles";
\r
3986 Hold_Time = "0cycles";
\r
3987 Setup_Time = "0cycles";
\r
3988 Is_Printable_Device = "0";
\r
3989 Address_Alignment = "dynamic";
\r
3990 Well_Behaved_Waitrequest = "0";
\r
3991 Is_Nonvolatile_Storage = "0";
\r
3992 Address_Span = "1";
\r
3993 Read_Latency = "0";
\r
3994 Is_Memory_Device = "0";
\r
3995 Maximum_Pending_Read_Transactions = "0";
\r
3996 Minimum_Uninterrupted_Run_Length = "1";
\r
3997 Accepts_Internal_Connections = "1";
\r
3998 Write_Latency = "0";
\r
4000 Maximum_Burst_Size = "1";
\r
4001 Register_Incoming_Signals = "1";
\r
4002 Register_Outgoing_Signals = "1";
\r
4003 Interleave_Bursts = "0";
\r
4004 Linewrap_Bursts = "0";
\r
4005 Burst_On_Burst_Boundaries_Only = "0";
\r
4006 Always_Burst_Max_Burst = "0";
\r
4007 Is_Big_Endian = "0";
\r
4009 MASTERED_BY cpu_0/data_master
\r
4012 Offset_Address = "0x00000000";
\r
4014 MASTERED_BY cpu_0/instruction_master
\r
4017 Offset_Address = "0x00000000";
\r
4019 MASTERED_BY nios_vga_inst/vga_dma
\r
4022 Offset_Address = "0x00000000";
\r
4024 Bridges_To = "tristate_master";
\r
4025 Base_Address = "N/A";
\r
4028 Address_Group = "0";
\r
4029 IRQ_MASTER cpu_0/data_master
\r
4031 IRQ_Number = "NC";
\r
4035 MASTER tristate_master
\r
4037 SYSTEM_BUILDER_INFO
\r
4039 Bus_Type = "avalon_tristate";
\r
4040 Is_Asynchronous = "0";
\r
4041 DBS_Big_Endian = "0";
\r
4043 Maximum_Burst_Size = "1";
\r
4044 Register_Incoming_Signals = "0";
\r
4045 Register_Outgoing_Signals = "0";
\r
4046 Interleave_Bursts = "0";
\r
4047 Linewrap_Bursts = "0";
\r
4048 Burst_On_Burst_Boundaries_Only = "0";
\r
4049 Always_Burst_Max_Burst = "0";
\r
4050 Is_Big_Endian = "0";
\r
4052 Bridges_To = "avalon_slave";
\r
4059 Entry cfi_flash/s1
\r
4061 address = "0x00000000";
\r
4062 span = "0x00800000";
\r
4065 Entry DBC3C40_SRAM_inst/avalon_tristate_slave
\r
4067 address = "0x00800000";
\r
4068 span = "0x00100000";
\r
4073 WIZARD_SCRIPT_ARGUMENTS
\r
4076 class = "altera_avalon_tri_state_bridge";
\r
4077 class_version = "7.08";
\r
4078 SYSTEM_BUILDER_INFO
\r
4081 Clock_Source = "clk";
\r
4083 Instantiate_In_System_Module = "1";
\r
4085 Top_Level_Ports_Are_Enumerated = "1";
\r
4104 direction = "input";
\r
4111 direction = "input";
\r
4118 direction = "output";
\r
4125 direction = "input";
\r
4130 type = "writedata";
\r
4132 direction = "input";
\r
4137 type = "readdata";
\r
4139 direction = "output";
\r
4144 type = "chipselect";
\r
4146 direction = "input";
\r
4153 direction = "input";
\r
4157 SYSTEM_BUILDER_INFO
\r
4160 Bus_Type = "avalon";
\r
4161 Write_Wait_States = "0cycles";
\r
4162 Read_Wait_States = "1cycles";
\r
4163 Hold_Time = "0cycles";
\r
4164 Setup_Time = "0cycles";
\r
4165 Is_Printable_Device = "0";
\r
4166 Address_Alignment = "native";
\r
4167 Well_Behaved_Waitrequest = "0";
\r
4168 Is_Nonvolatile_Storage = "0";
\r
4169 Read_Latency = "0";
\r
4170 Is_Memory_Device = "0";
\r
4171 Maximum_Pending_Read_Transactions = "0";
\r
4172 Minimum_Uninterrupted_Run_Length = "1";
\r
4173 Accepts_Internal_Connections = "1";
\r
4174 Write_Latency = "0";
\r
4176 Data_Width = "16";
\r
4177 Address_Width = "3";
\r
4178 Maximum_Burst_Size = "1";
\r
4179 Register_Incoming_Signals = "0";
\r
4180 Register_Outgoing_Signals = "0";
\r
4181 Interleave_Bursts = "0";
\r
4182 Linewrap_Bursts = "0";
\r
4183 Burst_On_Burst_Boundaries_Only = "0";
\r
4184 Always_Burst_Max_Burst = "0";
\r
4185 Is_Big_Endian = "0";
\r
4187 MASTERED_BY cpu_0/data_master
\r
4190 Offset_Address = "0x00900060";
\r
4192 IRQ_MASTER cpu_0/data_master
\r
4196 Base_Address = "0x00900060";
\r
4197 Address_Group = "0";
\r
4200 class = "altera_avalon_timer";
\r
4201 class_version = "7.08";
\r
4202 iss_model_name = "altera_avalon_timer";
\r
4203 SYSTEM_BUILDER_INFO
\r
4205 Instantiate_In_System_Module = "1";
\r
4207 Top_Level_Ports_Are_Enumerated = "1";
\r
4210 Settings_Summary = "Timer with 1 ms timeout period.";
\r
4211 Is_Collapsed = "1";
\r
4216 Clock_Source = "clk";
\r
4219 WIZARD_SCRIPT_ARGUMENTS
\r
4222 fixed_period = "0";
\r
4225 period_units = "ms";
\r
4226 reset_output = "0";
\r
4227 timeout_pulse_output = "0";
\r
4228 load_value = "74999";
\r
4229 counter_size = "32";
\r
4231 ticks_per_sec = "1000";
\r
4235 Precompiled_Simulation_Library_Files = "";
\r
4236 Simulation_HDL_Files = "";
\r
4237 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk.vhd";
\r
4238 Synthesis_Only_Files = "";
\r
4254 direction = "inout";
\r
4262 direction = "input";
\r
4270 direction = "input";
\r
4278 direction = "input";
\r
4284 type = "chipselect_n";
\r
4286 direction = "input";
\r
4291 SYSTEM_BUILDER_INFO
\r
4293 Bus_Type = "avalon_tristate";
\r
4294 Write_Wait_States = "100ns";
\r
4295 Read_Wait_States = "100ns";
\r
4296 Hold_Time = "20ns";
\r
4297 Setup_Time = "20ns";
\r
4298 Is_Printable_Device = "0";
\r
4299 Address_Alignment = "dynamic";
\r
4300 Well_Behaved_Waitrequest = "0";
\r
4301 Is_Nonvolatile_Storage = "1";
\r
4302 Address_Span = "8388608";
\r
4303 Read_Latency = "0";
\r
4304 Is_Memory_Device = "1";
\r
4305 Maximum_Pending_Read_Transactions = "0";
\r
4306 Minimum_Uninterrupted_Run_Length = "1";
\r
4307 Accepts_Internal_Connections = "1";
\r
4308 Write_Latency = "0";
\r
4310 Active_CS_Through_Read_Latency = "0";
\r
4311 Data_Width = "16";
\r
4312 Address_Width = "22";
\r
4313 Maximum_Burst_Size = "1";
\r
4314 Register_Incoming_Signals = "0";
\r
4315 Register_Outgoing_Signals = "0";
\r
4316 Interleave_Bursts = "0";
\r
4317 Linewrap_Bursts = "0";
\r
4318 Burst_On_Burst_Boundaries_Only = "0";
\r
4319 Always_Burst_Max_Burst = "0";
\r
4320 Is_Big_Endian = "0";
\r
4322 MASTERED_BY tri_state_bridge_0/tristate_master
\r
4325 Offset_Address = "0x00000000";
\r
4327 Base_Address = "0x00000000";
\r
4329 Simulation_Num_Lanes = "1";
\r
4330 Convert_Xs_To_0 = "1";
\r
4331 Address_Group = "0";
\r
4332 IRQ_MASTER cpu_0/data_master
\r
4334 IRQ_Number = "NC";
\r
4337 WIZARD_SCRIPT_ARGUMENTS
\r
4339 class = "altera_avalon_cfi_flash";
\r
4340 Supports_Flash_File_System = "1";
\r
4341 flash_reference_designator = "";
\r
4344 WIZARD_SCRIPT_ARGUMENTS
\r
4346 Setup_Value = "20";
\r
4347 Wait_Value = "100";
\r
4348 Hold_Value = "20";
\r
4349 Timing_Units = "ns";
\r
4350 Unit_Multiplier = "1";
\r
4356 CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(CFI_FLASH_FLASHTARGET_TMP1:0=)";
\r
4357 CFI_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
\r
4363 BOOT_COPIER = "boot_loader_cfi.srec";
\r
4364 CPU_CLASS = "altera_nios2";
\r
4365 CPU_RESET_ADDRESS = "0x0";
\r
4368 TARGET delete_placeholder_warning
\r
4372 Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
\r
4374 Target_File = "do_delete_placeholder_warning";
\r
4381 Command1 = "@echo Post-processing to create $(notdir $@)";
\r
4382 Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";
\r
4383 Dependency = "$(ELF)";
\r
4384 Target_File = "$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash";
\r
4391 Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
\r
4392 Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
\r
4393 Command3 = "touch $(SIMDIR)/dummy_file";
\r
4394 Dependency = "$(ELF)";
\r
4395 Target_File = "$(SIMDIR)/dummy_file";
\r
4400 SYSTEM_BUILDER_INFO
\r
4402 Simulation_Num_Lanes = "2";
\r
4404 Clock_Source = "clk";
\r
4406 Make_Memory_Model = "1";
\r
4407 Instantiate_In_System_Module = "0";
\r
4408 Top_Level_Ports_Are_Enumerated = "1";
\r
4416 class = "altera_avalon_cfi_flash";
\r
4417 class_version = "7.08";
\r
4418 iss_model_name = "altera_avalon_flash";
\r
4423 MODULE nios_vga_inst
\r
4433 direction = "input";
\r
4440 direction = "input";
\r
4445 type = "readdata";
\r
4447 direction = "input";
\r
4452 type = "waitrequest";
\r
4454 direction = "input";
\r
4459 type = "chipselect";
\r
4461 direction = "output";
\r
4468 direction = "output";
\r
4475 direction = "output";
\r
4482 direction = "output";
\r
4487 type = "writedata";
\r
4489 direction = "output";
\r
4493 SYSTEM_BUILDER_INFO
\r
4495 Bus_Type = "avalon";
\r
4496 Is_Asynchronous = "0";
\r
4497 DBS_Big_Endian = "0";
\r
4499 Do_Stream_Reads = "0";
\r
4500 Do_Stream_Writes = "0";
\r
4501 Max_Address_Width = "32";
\r
4502 Data_Width = "32";
\r
4503 Address_Width = "26";
\r
4504 Maximum_Burst_Size = "1";
\r
4505 Register_Incoming_Signals = "0";
\r
4506 Register_Outgoing_Signals = "0";
\r
4507 Interleave_Bursts = "0";
\r
4508 Linewrap_Bursts = "0";
\r
4509 Burst_On_Burst_Boundaries_Only = "0";
\r
4510 Always_Burst_Max_Burst = "0";
\r
4511 Is_Big_Endian = "0";
\r
4516 Entry cfi_flash/s1
\r
4518 address = "0x00000000";
\r
4519 span = "0x00800000";
\r
4522 Entry DBC3C40_SRAM_inst/avalon_tristate_slave
\r
4524 address = "0x00800000";
\r
4525 span = "0x00100000";
\r
4532 SYSTEM_BUILDER_INFO
\r
4534 Bus_Type = "avalon";
\r
4535 Write_Wait_States = "1cycles";
\r
4536 Read_Wait_States = "1cycles";
\r
4537 Hold_Time = "0cycles";
\r
4538 Setup_Time = "0cycles";
\r
4539 Is_Printable_Device = "0";
\r
4540 Address_Alignment = "native";
\r
4541 Well_Behaved_Waitrequest = "0";
\r
4542 Is_Nonvolatile_Storage = "0";
\r
4543 Read_Latency = "0";
\r
4544 Is_Memory_Device = "0";
\r
4545 Maximum_Pending_Read_Transactions = "0";
\r
4546 Minimum_Uninterrupted_Run_Length = "1";
\r
4547 Accepts_Internal_Connections = "1";
\r
4548 Write_Latency = "0";
\r
4550 Data_Width = "32";
\r
4551 Address_Width = "4";
\r
4552 Maximum_Burst_Size = "1";
\r
4553 Register_Incoming_Signals = "0";
\r
4554 Register_Outgoing_Signals = "0";
\r
4555 Interleave_Bursts = "0";
\r
4556 Linewrap_Bursts = "0";
\r
4557 Burst_On_Burst_Boundaries_Only = "0";
\r
4558 Always_Burst_Max_Burst = "0";
\r
4559 Is_Big_Endian = "0";
\r
4561 MASTERED_BY cpu_0/data_master
\r
4564 Offset_Address = "0x00900000";
\r
4566 Base_Address = "0x00900000";
\r
4567 Address_Group = "0";
\r
4568 IRQ_MASTER cpu_0/data_master
\r
4570 IRQ_Number = "NC";
\r
4577 type = "chipselect";
\r
4579 direction = "input";
\r
4586 direction = "input";
\r
4593 direction = "input";
\r
4598 type = "writedata";
\r
4600 direction = "input";
\r
4605 type = "readdata";
\r
4607 direction = "output";
\r
4618 direction = "output";
\r
4625 direction = "output";
\r
4632 direction = "output";
\r
4639 direction = "output";
\r
4646 direction = "output";
\r
4653 direction = "output";
\r
4660 direction = "output";
\r
4667 direction = "output";
\r
4674 direction = "output";
\r
4681 direction = "output";
\r
4688 direction = "output";
\r
4695 direction = "input";
\r
4699 class = "no_legacy_module";
\r
4700 class_version = "7.08";
\r
4701 gtf_class_name = "nios_vga";
\r
4702 gtf_class_version = "1.0.1";
\r
4703 SYSTEM_BUILDER_INFO
\r
4705 Do_Not_Generate = "1";
\r
4706 Instantiate_In_System_Module = "1";
\r
4708 Clock_Source = "clk";
\r
4719 Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_vga_inst.vhd";
\r
4721 WIZARD_SCRIPT_ARGUMENTS
\r
4728 MODULE DBC3C40_SRAM_inst
\r
4730 SLAVE avalon_tristate_slave
\r
4732 SYSTEM_BUILDER_INFO
\r
4734 Bus_Type = "avalon_tristate";
\r
4735 Write_Wait_States = "1cycles";
\r
4736 Read_Wait_States = "1cycles";
\r
4737 Hold_Time = "1cycles";
\r
4738 Setup_Time = "0cycles";
\r
4739 Is_Printable_Device = "0";
\r
4740 Address_Alignment = "dynamic";
\r
4741 Well_Behaved_Waitrequest = "0";
\r
4742 Is_Nonvolatile_Storage = "0";
\r
4743 Address_Span = "1048576";
\r
4744 Read_Latency = "0";
\r
4745 Is_Memory_Device = "1";
\r
4746 Maximum_Pending_Read_Transactions = "0";
\r
4747 Minimum_Uninterrupted_Run_Length = "1";
\r
4748 Accepts_Internal_Connections = "1";
\r
4749 Write_Latency = "0";
\r
4751 Active_CS_Through_Read_Latency = "0";
\r
4752 Data_Width = "16";
\r
4753 Address_Width = "19";
\r
4754 Maximum_Burst_Size = "1";
\r
4755 Register_Incoming_Signals = "0";
\r
4756 Register_Outgoing_Signals = "0";
\r
4757 Interleave_Bursts = "0";
\r
4758 Linewrap_Bursts = "0";
\r
4759 Burst_On_Burst_Boundaries_Only = "0";
\r
4760 Always_Burst_Max_Burst = "0";
\r
4761 Is_Big_Endian = "0";
\r
4763 MASTERED_BY tri_state_bridge_0/tristate_master
\r
4766 Offset_Address = "0x00800000";
\r
4768 Base_Address = "0x00800000";
\r
4769 Address_Group = "0";
\r
4770 IRQ_MASTER cpu_0/data_master
\r
4772 IRQ_Number = "NC";
\r
4781 direction = "input";
\r
4789 direction = "inout";
\r
4795 type = "chipselect_n";
\r
4797 direction = "input";
\r
4805 direction = "input";
\r
4813 direction = "input";
\r
4819 type = "byteenable_n";
\r
4821 direction = "input";
\r
4827 class = "no_legacy_module";
\r
4828 class_version = "7.08";
\r
4829 gtf_class_name = "DBC3C40_SRAM";
\r
4830 gtf_class_version = "1.0";
\r
4831 SYSTEM_BUILDER_INFO
\r
4833 Do_Not_Generate = "1";
\r
4834 Instantiate_In_System_Module = "0";
\r
4836 Clock_Source = "clk";
\r
4846 Simulation_HDL_Files = "";
\r
4848 WIZARD_SCRIPT_ARGUMENTS
\r