2 This serial port driver is borrowed heavily from DZComm. I have
\r
3 simplified it by removing a lot of the functionality (hardware
\r
4 flow control, etc.). For more details and the full version see
\r
5 http://dzcomm.sourceforge.net
\r
8 FreeRTOS V5.4.0 - Copyright (C) 2003-2009 Richard Barry.
\r
10 This file is part of the FreeRTOS distribution.
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12 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
13 the terms of the GNU General Public License (version 2) as published by the
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14 Free Software Foundation and modified by the FreeRTOS exception.
\r
15 **NOTE** The exception to the GPL is included to allow you to distribute a
\r
16 combined work that includes FreeRTOS without being obliged to provide the
\r
17 source code for proprietary components outside of the FreeRTOS kernel.
\r
18 Alternative commercial license and support terms are also available upon
\r
19 request. See the licensing section of http://www.FreeRTOS.org for full
\r
22 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
\r
23 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
\r
24 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
27 You should have received a copy of the GNU General Public License along
\r
28 with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
\r
29 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
\r
32 ***************************************************************************
\r
34 * Looking for a quick start? Then check out the FreeRTOS eBook! *
\r
35 * See http://www.FreeRTOS.org/Documentation for details *
\r
37 ***************************************************************************
\r
41 Please ensure to read the configuration and relevant port sections of the
\r
42 online documentation.
\r
44 http://www.FreeRTOS.org - Documentation, latest information, license and
\r
47 http://www.SafeRTOS.com - A version that is certified for use in safety
\r
50 http://www.OpenRTOS.com - Commercial support, development, porting,
\r
51 licensing and training services.
\r
57 + Call to the more efficient portSWITCH_CONTEXT() replaces the call to
\r
58 taskYIELD() in the ISR.
\r
60 Changes from V1.2.0:
\r
62 + Added vSerialPutString().
\r
66 + The function xPortInitMinimal() has been renamed to
\r
67 xSerialPortInitMinimal() and the function xPortInit() has been renamed
\r
68 to xSerialPortInit().
\r
72 + Use portTickType in place of unsigned pdLONG for delay periods.
\r
73 + cQueueReieveFromISR() used in place of xQueueReceive() in ISR.
\r
79 #include "FreeRTOS.h"
\r
83 #include "portasm.h"
\r
85 #define serMAX_IRQs ( 16 )
\r
86 #define serTRANSMIT_HOLD_EMPTY_INT ( 0x02 )
\r
87 #define serCOM1_STANDARD_IRQ ( ( unsigned portCHAR ) 4 )
\r
88 #define serCOM2_STANDARD_IRQ ( ( unsigned portCHAR ) 3 )
\r
91 #define serIMR_8259_0 ( ( unsigned portCHAR ) 0x21 )
\r
92 #define serIMR_8259_1 ( ( unsigned portCHAR ) 0xa1 )
\r
93 #define serISR_8259_0 ( ( unsigned portCHAR ) 0x20 )
\r
94 #define serISR_8259_1 ( ( unsigned portCHAR ) 0xa0 )
\r
95 #define serALL_COMS_INTERRUPTS ( ( unsigned portCHAR ) 0x0f )
\r
96 #define serALL_MODEM_CTRL_INTERRUPTS ( ( unsigned portCHAR ) 0x0f )
\r
98 #define serTRANSMIT_HOLD_OFFSET ( 0 )
\r
99 #define serRECEIVE_DATA_OFFSET ( 0 )
\r
100 #define serBAUD_RATE_DIVISOR_LOW_OFFSET ( 0 )
\r
101 #define serBAUD_RATE_DIVISOR_HIGH_OFFSET ( 1 )
\r
102 #define serINTERRUPT_ENABLE_OFFSET ( 1 )
\r
103 #define serINTERRUPT_ID_OFFSET ( 2 )
\r
104 #define serFIFO_CTRL_OFFSET ( 2 )
\r
105 #define serLINE_CTRL_OFFSET ( 3 )
\r
106 #define serMODEM_CTRL_OFFSET ( 4 )
\r
107 #define serLINE_STATUS_OFFSET ( 5 )
\r
108 #define serMODEM_STATUS_OFFSET ( 6 )
\r
109 #define serSCR_OFFSET ( 7 )
\r
111 #define serMAX_BAUD ( ( unsigned portLONG ) 115200UL )
\r
113 #define serNO_INTERRUPTS ( 0x00 )
\r
115 #define vInterruptOn( pxPort, ucInterrupt ) \
\r
117 unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \
\r
118 if( !( ucIn & ucInterrupt ) ) \
\r
120 portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn | ucInterrupt ); \
\r
123 /*-----------------------------------------------------------*/
\r
125 #define vInterruptOff( pxPort, ucInterrupt ) \
\r
127 unsigned portCHAR ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \
\r
128 if( ucIn & ucInterrupt ) \
\r
130 portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn & ~ucInterrupt); \
\r
133 /*-----------------------------------------------------------*/
\r
191 /* This *MUST* match the order in the eBaud definition. */
\r
192 unsigned portLONG ulBaudFromEnum[] =
\r
194 ( unsigned portLONG ) 50,
\r
195 ( unsigned portLONG ) 75,
\r
196 ( unsigned portLONG ) 110,
\r
197 ( unsigned portLONG ) 134,
\r
198 ( unsigned portLONG ) 150,
\r
199 ( unsigned portLONG ) 200,
\r
200 ( unsigned portLONG ) 300,
\r
201 ( unsigned portLONG ) 600,
\r
202 ( unsigned portLONG ) 1200,
\r
203 ( unsigned portLONG ) 1800,
\r
204 ( unsigned portLONG ) 2400,
\r
205 ( unsigned portLONG ) 4800,
\r
206 ( unsigned portLONG ) 9600,
\r
207 ( unsigned portLONG ) 19200,
\r
208 ( unsigned portLONG ) 38400UL,
\r
209 ( unsigned portLONG ) 57600UL,
\r
210 ( unsigned portLONG ) 115200UL
\r
213 typedef struct xCOM_PORT
\r
215 unsigned portSHORT sPort; /* comm port address eg. 0x3f8 */
\r
216 unsigned portCHAR ucIRQ; /* comm IRQ eg. 3 */
\r
218 /* Next two fields used for setting up the IRQ routine and
\r
219 * (un)masking the interrupt in certain circumstances.
\r
221 unsigned portSHORT usIRQVector;
\r
222 unsigned portCHAR ucInterruptEnableMast;
\r
224 /* Read/Write buffers. */
\r
225 xQueueHandle xRxedChars;
\r
226 xQueueHandle xCharsForTx;
\r
228 /* This lot are set up to minimise CPU time where accessing the comm
\r
229 * port's registers.
\r
231 unsigned portSHORT usTransmitHoldReg;
\r
232 unsigned portSHORT usReceiveDataRegister;
\r
233 unsigned portSHORT usBaudRateDivisorLow;
\r
234 unsigned portSHORT usBaudRateDivisorHigh;
\r
235 unsigned portSHORT usInterruptEnableReg;
\r
236 unsigned portSHORT usInterruptIDReg;
\r
237 unsigned portSHORT usFIFOCtrlReg;
\r
238 unsigned portSHORT usLineCtrlReg;
\r
239 unsigned portSHORT usModemCtrlReg;
\r
240 unsigned portSHORT usLineStatusReg;
\r
241 unsigned portSHORT usModemStatusReg;
\r
242 unsigned portSHORT usSCRReg;
\r
243 unsigned portSHORT us8259InterruptServiceReg;
\r
244 unsigned portSHORT us8259InterruptMaskReg;
\r
246 /* This semaphore does nothing useful except test a feature of the
\r
248 xSemaphoreHandle xTestSem;
\r
252 typedef xComPort *xComPortHandle;
\r
254 /* A xComPort structure can be associated with each IRQ. Initially none
\r
255 are create/installed. */
\r
256 xComPort *xPortStatus[ serMAX_IRQs ] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
\r
258 /*-----------------------------------------------------------*/
\r
260 /* These prototypes are repeated here so we don't have to include the serial header. This allows
\r
261 the xComPortHandle structure details to be private to this file. */
\r
262 xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );
\r
263 portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime );
\r
264 portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime );
\r
265 portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort );
\r
267 static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits );
\r
268 static portSHORT sComPortISR( const xComPort * const pxPort );
\r
270 /*-----------------------------------------------------------*/
\r
272 /* Define an interrupt handler for each slot in the xPortStatus array. */
\r
274 #define COM_IRQ_WRAPPER(N) \
\r
275 static void __interrupt COM_IRQ##N##_WRAPPER( void ) \
\r
277 portDISABLE_INTERRUPTS(); \
\r
278 if( sComPortISR( xPortStatus[##N##] ) ) \
\r
280 portSWITCH_CONTEXT(); \
\r
284 COM_IRQ_WRAPPER( 0 )
\r
285 COM_IRQ_WRAPPER( 1 )
\r
286 COM_IRQ_WRAPPER( 2 )
\r
287 COM_IRQ_WRAPPER( 3 )
\r
288 COM_IRQ_WRAPPER( 4 )
\r
289 COM_IRQ_WRAPPER( 5 )
\r
290 COM_IRQ_WRAPPER( 6 )
\r
291 COM_IRQ_WRAPPER( 7 )
\r
292 COM_IRQ_WRAPPER( 8 )
\r
293 COM_IRQ_WRAPPER( 9 )
\r
294 COM_IRQ_WRAPPER( 10 )
\r
295 COM_IRQ_WRAPPER( 11 )
\r
296 COM_IRQ_WRAPPER( 12 )
\r
297 COM_IRQ_WRAPPER( 13 )
\r
298 COM_IRQ_WRAPPER( 14 )
\r
299 COM_IRQ_WRAPPER( 15 )
\r
301 static pxISR xISRs[ serMAX_IRQs ] =
\r
313 COM_IRQ10_WRAPPER,
\r
314 COM_IRQ11_WRAPPER,
\r
315 COM_IRQ12_WRAPPER,
\r
316 COM_IRQ13_WRAPPER,
\r
321 static pxISR xOldISRs[ serMAX_IRQs ] = { NULL };
\r
323 /*-----------------------------------------------------------*/
\r
326 xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength )
\r
330 /* Create a structure to handle this port. */
\r
331 pxPort = ( xComPort * ) pvPortMalloc( sizeof( xComPort ) );
\r
333 if( pxPort != NULL )
\r
335 /* Create the queues used by the comtest task. */
\r
336 pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );
\r
337 pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( portCHAR ) );
\r
339 /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */
\r
340 vSemaphoreCreateBinary( pxPort->xTestSem );
\r
342 prvSetupPortHardware( pxPort, ePort, eWantedBaud, eWantedParity, eWantedDataBits, eWantedStopBits );
\r
349 /*-----------------------------------------------------------*/
\r
351 static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits )
\r
354 unsigned portLONG ulDivisor;
\r
355 unsigned portCHAR ucDivisorLow;
\r
356 unsigned portCHAR ucDivisorHigh;
\r
357 unsigned portCHAR ucCommParam;
\r
359 /* IRQ numbers - standard */
\r
360 if( ( ePort == serCOM1 ) || ( ePort == serCOM3 ) || ( ePort == serCOM5 ) || ( ePort == serCOM7 ) )
\r
362 pxPort->ucIRQ = serCOM1_STANDARD_IRQ;
\r
363 pxPort->sPort = 0x3f8;
\r
367 pxPort->ucIRQ = serCOM2_STANDARD_IRQ;
\r
368 pxPort->sPort = 0x2f8;
\r
371 /* Set up variables in port making it easy to see which sIn/o address is which */
\r
372 pxPort->usTransmitHoldReg = pxPort->sPort + serTRANSMIT_HOLD_OFFSET;
\r
373 pxPort->usReceiveDataRegister = pxPort->sPort + serRECEIVE_DATA_OFFSET;
\r
374 pxPort->usBaudRateDivisorLow = pxPort->sPort + serBAUD_RATE_DIVISOR_LOW_OFFSET;
\r
375 pxPort->usBaudRateDivisorHigh = pxPort->sPort + serBAUD_RATE_DIVISOR_HIGH_OFFSET;
\r
376 pxPort->usInterruptEnableReg = pxPort->sPort + serINTERRUPT_ENABLE_OFFSET;
\r
377 pxPort->usInterruptIDReg = pxPort->sPort + serINTERRUPT_ID_OFFSET;
\r
378 pxPort->usFIFOCtrlReg = pxPort->sPort + serFIFO_CTRL_OFFSET;
\r
379 pxPort->usLineCtrlReg = pxPort->sPort + serLINE_CTRL_OFFSET;
\r
380 pxPort->usModemCtrlReg = pxPort->sPort + serMODEM_CTRL_OFFSET;
\r
381 pxPort->usLineStatusReg = pxPort->sPort + serLINE_STATUS_OFFSET;
\r
382 pxPort->usModemStatusReg = pxPort->sPort + serMODEM_STATUS_OFFSET;
\r
383 pxPort->usSCRReg = pxPort->sPort + serSCR_OFFSET;
\r
385 /* Set communication parameters. */
\r
386 ulDivisor = serMAX_BAUD / ulBaudFromEnum[ eWantedBaud ];
\r
387 ucDivisorLow = ( unsigned portCHAR ) ulDivisor & ( unsigned portCHAR ) 0xff;
\r
388 ucDivisorHigh = ( unsigned portCHAR ) ( ( ( unsigned portSHORT ) ulDivisor >> 8 ) & 0xff );
\r
390 switch( eWantedParity )
\r
392 case serNO_PARITY: ucCommParam = 0x00;
\r
394 case serODD_PARITY: ucCommParam = 0x08;
\r
396 case serEVEN_PARITY: ucCommParam = 0x18;
\r
398 case serMARK_PARITY: ucCommParam = 0x28;
\r
400 case serSPACE_PARITY: ucCommParam = 0x38;
\r
402 default: ucCommParam = 0x00;
\r
406 switch ( eWantedDataBits )
\r
408 case serBITS_5: ucCommParam |= 0x00;
\r
410 case serBITS_6: ucCommParam |= 0x01;
\r
412 case serBITS_7: ucCommParam |= 0x02;
\r
414 case serBITS_8: ucCommParam |= 0x03;
\r
416 default: ucCommParam |= 0x03;
\r
420 if( eWantedStopBits == serSTOP_2 )
\r
422 ucCommParam |= 0x04;
\r
425 /* Reset UART into known state - Thanks to Bradley Town */
\r
426 portOUTPUT_BYTE( pxPort->usLineCtrlReg, 0x00 ); /* Access usTransmitHoldReg/RBR/usInterruptEnableReg */
\r
427 portOUTPUT_BYTE( pxPort->usInterruptEnableReg, 0x00 ); /* Disable interrupts from UART */
\r
428 portOUTPUT_BYTE( pxPort->usModemCtrlReg, 0x04 ); /* Enable some multi-port cards */
\r
430 /* Code based on stuff from SVAsync lib. Clear UART Status and data registers
\r
431 setting up FIFO if possible */
\r
432 sIn = portINPUT_BYTE( pxPort->usSCRReg );
\r
433 portOUTPUT_BYTE( pxPort->usSCRReg, 0x55 );
\r
435 if( portINPUT_BYTE( pxPort->usSCRReg ) == 0x55 )
\r
437 /* The chip is better than an 8250 */
\r
438 portOUTPUT_BYTE( pxPort->usSCRReg, sIn ); /* Set usSCRReg back to what it was before */
\r
439 portINPUT_BYTE( pxPort->usSCRReg); /* Give slow motherboards a chance */
\r
441 /* Try and start the FIFO. It appears that some chips need a two call
\r
442 protocol, but those that don't seem to work even if you do start it twice.
\r
443 The first call is simply to start it, the second starts it and sets an 8
\r
444 byte FIFO trigger level. */
\r
445 portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x01 );
\r
446 portINPUT_BYTE( pxPort->usFIFOCtrlReg ); /* Give slow motherboards a chance to catch up */
\r
447 portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x87 );
\r
449 /* Check that the FIFO initialised */
\r
450 if( ( portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0xc0 ) != 0xc0 )
\r
452 /* It didn't so we assume it isn't there but disable it to be on the
\r
454 portOUTPUT_BYTE( pxPort->usInterruptIDReg, 0xfe );
\r
458 /* End of (modified) SVAsync code.
\r
459 Set interrupt parameters calculating mask for 8259 controller's
\r
460 IMR and number of interrupt handler for given irq level */
\r
461 if (pxPort->ucIRQ <= 7)
\r
463 /* if 0<=irq<=7 first IMR address used */
\r
464 pxPort->ucInterruptEnableMast = ~(0x01 << pxPort->ucIRQ);
\r
465 pxPort->usIRQVector = pxPort->ucIRQ + 8;
\r
466 pxPort->us8259InterruptMaskReg = serIMR_8259_0;
\r
467 pxPort->us8259InterruptServiceReg = serISR_8259_0;
\r
471 pxPort->ucInterruptEnableMast = ~( 0x01 << ( pxPort->ucIRQ % 8 ) );
\r
472 pxPort->usIRQVector = 0x70 + ( pxPort->ucIRQ - 8) ;
\r
473 pxPort->us8259InterruptMaskReg = serIMR_8259_1;
\r
474 pxPort->us8259InterruptServiceReg = serISR_8259_1;
\r
477 /* Set Port Toggle to usBaudRateDivisorLow/usBaudRateDivisorHigh registers
\r
478 to set baud rate */
\r
479 portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam | 0x80 );
\r
480 portOUTPUT_BYTE( pxPort->usBaudRateDivisorLow, ucDivisorLow );
\r
481 portOUTPUT_BYTE( pxPort->usBaudRateDivisorHigh, ucDivisorHigh );
\r
483 /* reset usLineCtrlReg and Port Toggleout */
\r
484 portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam & 0x7F );
\r
486 portENTER_CRITICAL();
\r
488 if( xPortStatus[ pxPort->ucIRQ ] == NULL )
\r
490 xPortStatus[ pxPort->ucIRQ ] = pxPort;
\r
493 xOldISRs[ pxPort->ucIRQ ] = _dos_getvect( pxPort->usIRQVector );
\r
494 _dos_setvect( pxPort->usIRQVector, xISRs[ pxPort->ucIRQ ] );
\r
496 /* enable interrupt pxPort->ucIRQ level */
\r
497 portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast );
\r
499 /* And allow interrupts again now the hairy bit's done */
\r
500 portEXIT_CRITICAL();
\r
502 /* This version does not allow flow control. */
\r
503 portOUTPUT_BYTE( pxPort->usModemCtrlReg, serALL_MODEM_CTRL_INTERRUPTS );
\r
505 /* enable all communication's interrupts */
\r
506 portOUTPUT_BYTE( pxPort->usInterruptEnableReg, serALL_COMS_INTERRUPTS );
\r
508 /*-----------------------------------------------------------*/
\r
510 static portSHORT sComPortISR( const xComPort * const pxPort )
\r
512 portSHORT sInterruptID;
\r
513 portCHAR cIn, cOut;
\r
514 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
\r
515 extern void vComTestUnsuspendTask( void );
\r
517 portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, ( portINPUT_BYTE( pxPort->us8259InterruptMaskReg) | ~pxPort->ucInterruptEnableMast ) );
\r
519 /* Decide which UART has issued the interrupt */
\r
520 sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg );
\r
522 /* service whatever requests the calling UART may have. The top 4 bits are
\r
523 either unused or indicate the presence of a functioning FIFO, which we don't
\r
524 need to know. So trim them off to simplify the switch statement below. */
\r
525 sInterruptID &= 0x0f;
\r
528 switch( sInterruptID )
\r
530 case 0x0c: /* Timeout
\r
531 Called when FIFO not up to trigger level but no activity for
\r
532 a while. Handled exactly as RDAINT, see below for
\r
536 cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister );
\r
537 xQueueSendFromISR( pxPort->xRxedChars, &cIn, &xHigherPriorityTaskWoken );
\r
539 /* Also release the semaphore - this does nothing interesting and is just a test.
\r
540 We first attempt to unsuspend the task to check the scheduler correctely detects
\r
541 this as an invalid call, then give the semaphore for real. */
\r
542 vComTestUnsuspendTask();
\r
543 xSemaphoreGiveFromISR( pxPort->xTestSem, &xHigherPriorityTaskWoken );
\r
545 } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 );
\r
548 case 0x06: /* LSINT */
\r
549 portINPUT_BYTE( pxPort->usLineStatusReg );
\r
552 case 0x04: /* RDAINT */
\r
553 /* The usInterruptIDReg flag tested above stops when the
\r
554 FIFO is below the trigger level rather than empty, whereas
\r
555 this flag allows one to empty it: (do loop because there
\r
556 must be at least one to read by virtue of having got here.) */
\r
559 cIn = ( portCHAR ) portINPUT_BYTE( pxPort->usReceiveDataRegister );
\r
560 xQueueSendFromISR( pxPort->xRxedChars, &cIn, &xHigherPriorityTaskWoken );
\r
562 /* Also release the semaphore - this does nothing interesting and is just a test.
\r
563 We first attempt to unsuspend the task to check the scheduler correctely detects
\r
564 this as an invalid call, then give the semaphore for real. */
\r
565 vComTestUnsuspendTask();
\r
566 xSemaphoreGiveFromISR( pxPort->xTestSem, &xHigherPriorityTaskWoken );
\r
568 } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 );
\r
571 case 0x02: /* serTRANSMIT_HOLD_EMPTY_INT */
\r
572 if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cOut, &xHigherPriorityTaskWoken ) != pdTRUE )
\r
574 /* Queue empty, nothing to send */
\r
575 vInterruptOff( pxPort, serTRANSMIT_HOLD_EMPTY_INT);
\r
579 portOUTPUT_BYTE( pxPort->usTransmitHoldReg, ( portSHORT ) cOut );
\r
583 case 0x00: /* MSINT */
\r
584 portINPUT_BYTE( pxPort->usModemStatusReg );
\r
588 /* Get the next instruction, trimming as above */
\r
589 sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0x0f;
\r
591 } while( !( sInterruptID & 0x01 ) );
\r
593 if( pxPort->ucIRQ > 7 )
\r
595 portOUTPUT_BYTE( 0xA0, 0x60 + ( pxPort->ucIRQ & 0x07 ) );
\r
596 portOUTPUT_BYTE( 0x20, 0x62);
\r
600 portOUTPUT_BYTE( 0x20, 0x60 + pxPort->ucIRQ );
\r
603 portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast );
\r
605 /* If posting any of the characters to a queue woke a task that was blocked on
\r
606 the queue we may want to return to the task just woken (depending on its
\r
607 priority relative to the task this ISR interrupted. */
\r
608 return xHigherPriorityTaskWoken;
\r
610 /*-----------------------------------------------------------*/
\r
612 portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, portCHAR *pcRxedChar, portTickType xBlockTime )
\r
614 /* Get the next character from the buffer, note that this routine is only
\r
615 called having checked that the is (at least) one to get */
\r
616 if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) )
\r
625 /*-----------------------------------------------------------*/
\r
627 portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, portCHAR cOutChar, portTickType xBlockTime )
\r
629 if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
\r
634 vInterruptOn( pxPort, serTRANSMIT_HOLD_EMPTY_INT );
\r
638 /*-----------------------------------------------------------*/
\r
640 void vSerialPutString( xComPortHandle pxPort, const portCHAR * const pcString, unsigned portSHORT usStringLength )
\r
642 portCHAR * pcNextChar;
\r
643 const portTickType xNoBlock = ( portTickType ) 0;
\r
645 /* Stop warnings. */
\r
646 ( void ) usStringLength;
\r
648 pcNextChar = ( portCHAR * ) pcString;
\r
649 while( *pcNextChar )
\r
651 xSerialPutChar( pxPort, *pcNextChar, xNoBlock );
\r
655 /*-----------------------------------------------------------*/
\r
657 portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort )
\r
659 const portTickType xBlockTime = ( portTickType ) 0xffff;
\r
661 /* This function does nothing interesting, but test the
\r
662 semaphore from ISR mechanism. */
\r
663 return xSemaphoreTake( xPort->xTestSem, xBlockTime );
\r
665 /*-----------------------------------------------------------*/
\r
667 void vSerialClose( xComPortHandle xPort )
\r
669 portENTER_CRITICAL();
\r
671 /* Turn off the interrupts. */
\r
672 portOUTPUT_BYTE( xPort->usModemCtrlReg, serNO_INTERRUPTS );
\r
673 portOUTPUT_BYTE( xPort->usInterruptEnableReg, serNO_INTERRUPTS );
\r
675 /* Put back the original ISR. */
\r
676 _dos_setvect( xPort->usIRQVector, xOldISRs[ xPort->ucIRQ ] );
\r
678 /* Remove the reference in the array of xComPort structures. */
\r
679 xPortStatus[ xPort->ucIRQ ] = NULL;
\r
681 /* Delete the queues. */
\r
682 vQueueDelete( xPort->xRxedChars );
\r
683 vQueueDelete( xPort->xCharsForTx );
\r
685 vPortFree( ( void * ) xPort );
\r
687 portEXIT_CRITICAL();
\r