1 ############################################################################
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2 ## This system.ucf file is generated by Base System Builder based on the
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3 ## settings in the selected Xilinx Board Definition file. Please add other
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4 ## user constraints to this file based on customer design specifications.
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5 ############################################################################
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7 Net sys_clk_pin LOC=AE14;
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8 Net sys_clk_pin IOSTANDARD = LVCMOS33;
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9 Net sys_rst_pin LOC=D6;
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10 Net sys_rst_pin PULLUP;
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11 ## System level constraints
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12 Net sys_clk_pin TNM_NET = sys_clk_pin;
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13 TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
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14 Net sys_rst_pin TIG;
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15 NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP";
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16 NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP";
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17 NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP";
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18 TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;
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19 Net fpga_0_SRAM_CLOCK LOC=AF7;
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20 Net fpga_0_SRAM_CLOCK SLEW = FAST;
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21 Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33;
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22 Net fpga_0_SRAM_CLOCK DRIVE = 16;
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24 ## IO Devices constraints
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26 #### Module RS232_Uart constraints
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28 Net fpga_0_RS232_Uart_RX_pin LOC=W2;
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29 Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;
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30 Net fpga_0_RS232_Uart_TX_pin LOC=W1;
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31 Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;
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33 #### Module LEDs_4Bit constraints
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35 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;
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36 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
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37 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;
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38 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
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39 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;
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40 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;
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41 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;
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42 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
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43 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;
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44 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
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45 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;
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46 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;
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47 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;
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48 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
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49 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;
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50 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
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51 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;
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52 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;
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53 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;
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54 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
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55 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;
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56 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
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57 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;
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58 Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;
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60 #### Module LEDs_Positions constraints
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62 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;
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63 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
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64 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;
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65 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;
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66 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;
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67 Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;
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68 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;
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69 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
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70 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;
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71 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;
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72 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;
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73 Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;
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74 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;
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75 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
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76 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;
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77 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;
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78 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;
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79 Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;
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80 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;
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81 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
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82 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;
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83 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;
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84 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;
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85 Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;
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86 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;
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87 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
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88 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;
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89 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;
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90 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;
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91 Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;
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93 #### Module SRAM constraints
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95 Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1;
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96 Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33;
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97 Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST;
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98 Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8;
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99 Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2;
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100 Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33;
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101 Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST;
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102 Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8;
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103 Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1;
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104 Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33;
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105 Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST;
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106 Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8;
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107 Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1;
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108 Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33;
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109 Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST;
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110 Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8;
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111 Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2;
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112 Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33;
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113 Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST;
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114 Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8;
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115 Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1;
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116 Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33;
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117 Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST;
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118 Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8;
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119 Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2;
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120 Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33;
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121 Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST;
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122 Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8;
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123 Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1;
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124 Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33;
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125 Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST;
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126 Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8;
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127 Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2;
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128 Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33;
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129 Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST;
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130 Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8;
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131 Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3;
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132 Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33;
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133 Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST;
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134 Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8;
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135 Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3;
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136 Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33;
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137 Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST;
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138 Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8;
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139 Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3;
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140 Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33;
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141 Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST;
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142 Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8;
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143 Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6;
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144 Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33;
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145 Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST;
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146 Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8;
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147 Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5;
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148 Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33;
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149 Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST;
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150 Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8;
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151 Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3;
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152 Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33;
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153 Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST;
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154 Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8;
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155 Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4;
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156 Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33;
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157 Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST;
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158 Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8;
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159 Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3;
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160 Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33;
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161 Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST;
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162 Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8;
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163 Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4;
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164 Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33;
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165 Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST;
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166 Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8;
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167 Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4;
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168 Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33;
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169 Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST;
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170 Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8;
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171 Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5;
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172 Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33;
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173 Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST;
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174 Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8;
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175 Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5;
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176 Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33;
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177 Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST;
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178 Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8;
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179 Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6;
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180 Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33;
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181 Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST;
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182 Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8;
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183 Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5;
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184 Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33;
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185 Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST;
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186 Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8;
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187 Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4;
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188 Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33;
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189 Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST;
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190 Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8;
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191 Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3;
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192 Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33;
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193 Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST;
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194 Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8;
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195 Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6;
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196 Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33;
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197 Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST;
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198 Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8;
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199 Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13;
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200 Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST;
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201 Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33;
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202 Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12;
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203 Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13;
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204 Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST;
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205 Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33;
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206 Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12;
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207 Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15;
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208 Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST;
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209 Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33;
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210 Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12;
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211 Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16;
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212 Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST;
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213 Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33;
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214 Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12;
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215 Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11;
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216 Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST;
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217 Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33;
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218 Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12;
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219 Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12;
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220 Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST;
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221 Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33;
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222 Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12;
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223 Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14;
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224 Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST;
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225 Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33;
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226 Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12;
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227 Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14;
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228 Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST;
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229 Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33;
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230 Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12;
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231 Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13;
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232 Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST;
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233 Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33;
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234 Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12;
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235 Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13;
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236 Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST;
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237 Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33;
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238 Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12;
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239 Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15;
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240 Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST;
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241 Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33;
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242 Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12;
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243 Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16;
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244 Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST;
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245 Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33;
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246 Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12;
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247 Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11;
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248 Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST;
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249 Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33;
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250 Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12;
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251 Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12;
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252 Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST;
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253 Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33;
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254 Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12;
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255 Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14;
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256 Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST;
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257 Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33;
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258 Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12;
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259 Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14;
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260 Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST;
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261 Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33;
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262 Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12;
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263 Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12;
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264 Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST;
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265 Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33;
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266 Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12;
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267 Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13;
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268 Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST;
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269 Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33;
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270 Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12;
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271 Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16;
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272 Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST;
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273 Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33;
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274 Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12;
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275 Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16;
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276 Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST;
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277 Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33;
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278 Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12;
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279 Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11;
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280 Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST;
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281 Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33;
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282 Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12;
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283 Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11;
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284 Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST;
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285 Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33;
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286 Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12;
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287 Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14;
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288 Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST;
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289 Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33;
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290 Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12;
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291 Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15;
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292 Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST;
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293 Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33;
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294 Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12;
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295 Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13;
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296 Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST;
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297 Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33;
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298 Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12;
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299 Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14;
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300 Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST;
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301 Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33;
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302 Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12;
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303 Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15;
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304 Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST;
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305 Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33;
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306 Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12;
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307 Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16;
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308 Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST;
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309 Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33;
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310 Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12;
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311 Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11;
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312 Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST;
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313 Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33;
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314 Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12;
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315 Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12;
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316 Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST;
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317 Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33;
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318 Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12;
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319 Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13;
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320 Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST;
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321 Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33;
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322 Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12;
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323 Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14;
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324 Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST;
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325 Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33;
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326 Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12;
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327 Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6;
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328 Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33;
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329 Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST;
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330 Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8;
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331 Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7;
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332 Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33;
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333 Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST;
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334 Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8;
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335 Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4;
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336 Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33;
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337 Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST;
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338 Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8;
\r
projects / freertos / blob