1 #################################################################
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2 # Makefile generated by Xilinx Platform Studio
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3 # Project:C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp
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5 # WARNING : This file will be re-generated every time a command
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6 # to run a make target is invoked. So, any changes made to this
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7 # file manually, will be lost when make is invoked next.
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8 #################################################################
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10 # Name of the Microprocessor system
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11 # The hardware specification of the system is in file :
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12 # C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.mhs
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13 # The software specification of the system is in file :
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14 # C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.mss
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16 include system_incl.make
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18 #################################################################
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20 #################################################################
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22 .PHONY: netlistclean
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27 #################################################################
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29 #################################################################
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31 @echo "Makefile to build a Microprocessor system :"
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32 @echo "Run make with any of the following targets"
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34 @echo " netlist : Generates the netlist for the given MHS "
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35 @echo " bits : Runs Implementation tools to generate the bitstream"
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37 @echo " libs : Configures the sw libraries for this system"
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38 @echo " program : Compiles the program sources for all the processor instances"
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40 @echo " init_bram: Initializes bitstream with BRAM data"
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41 @echo " ace : Generate ace file from bitstream and elf"
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42 @echo " download : Downloads the bitstream onto the board"
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44 @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"
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45 @echo " simmodel : Generates HDL simulation models for chosen simulation mode"
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46 @echo " behavioral_model : Generates behavioral HDL models with BRAM initialization"
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47 @echo " structural_model : Generates structural simulation HDL models with BRAM initialization"
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48 @echo " timing : Generates timing simulation HDL models with BRAM initialization"
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49 @echo " vp : Generates virtual platform model"
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51 @echo " netlistclean: Deletes netlist"
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52 @echo " bitsclean: Deletes bit, ncd, bmm files"
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53 @echo " hwclean : Deletes implementation dir"
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54 @echo " libsclean: Deletes sw libraries"
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55 @echo " programclean: Deletes compiled ELF files"
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56 @echo " swclean : Deletes sw libraries and ELF files"
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57 @echo " simclean : Deletes simulation dir"
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58 @echo " vpclean : Deletes virtualplatform dir"
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59 @echo " clean : Deletes all generated files/directories"
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61 @echo " make <target> : (Default)"
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62 @echo " Creates a Microprocessor system using default initializations"
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63 @echo " specified for each processor in MSS file"
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70 netlist: $(POSTSYN_NETLIST)
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74 program: $(ALL_USER_ELF_FILES)
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76 download: $(DOWNLOAD_BIT) dummy
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77 @echo "*********************************************"
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78 @echo "Downloading Bitstream onto the target board"
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79 @echo "*********************************************"
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80 impact -batch etc/download.cmd
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82 init_bram: $(DOWNLOAD_BIT)
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84 sim: $(DEFAULT_SIM_SCRIPT)
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85 cd simulation/behavioral; \
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88 simmodel: $(DEFAULT_SIM_SCRIPT)
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90 behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
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92 structural_model: $(STRUCTURAL_SIM_SCRIPT)
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96 clean: hwclean libsclean programclean simclean vpclean
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100 hwclean: netlistclean bitsclean
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101 rm -rf implementation synthesis xst hdl
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102 rm -rf xst.srp $(SYSTEM).srp
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105 rm -f $(POSTSYN_NETLIST)
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110 rm -f $(SYSTEM_BIT)
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111 rm -f implementation/$(SYSTEM).ncd
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112 rm -f implementation/$(SYSTEM)_bd.bmm
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113 rm -f implementation/$(SYSTEM)_map.ncd
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116 rm -rf simulation/behavioral
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119 swclean: libsclean programclean
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122 libsclean: $(LIBSCLEAN_TARGETS)
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125 programclean: $(PROGRAMCLEAN_TARGETS)
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128 rm -rf virtualplatform
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131 #################################################################
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132 # SOFTWARE PLATFORM FLOW
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133 #################################################################
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136 $(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt
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137 @echo "*********************************************"
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138 @echo "Creating software libraries..."
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139 @echo "*********************************************"
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140 libgen $(LIBGEN_OPTIONS) $(MSSFILE)
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143 ppc405_0_libsclean:
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146 #################################################################
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147 # SOFTWARE APPLICATION RTOSDEMO
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148 #################################################################
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150 RTOSDemo_program: $(RTOSDEMO_OUTPUT)
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152 $(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \
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153 $(LIBRARIES) __xps/rtosdemo_compiler.opt
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154 @mkdir -p $(RTOSDEMO_OUTPUT_DIR)
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155 $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \
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156 $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \
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157 $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS)
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158 $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT)
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161 RTOSDemo_programclean:
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162 rm -f $(RTOSDEMO_OUTPUT)
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164 #################################################################
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165 # BOOTLOOP ELF FILES
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166 #################################################################
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170 $(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP)
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171 @mkdir -p $(BOOTLOOP_DIR)
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172 cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP)
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174 #################################################################
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175 # HARDWARE IMPLEMENTATION FLOW
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176 #################################################################
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180 $(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
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181 $(CORE_STATE_DEVELOPMENT_FILES)
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182 @echo "****************************************************"
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183 @echo "Creating system netlist for hardware specification.."
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184 @echo "****************************************************"
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185 platgen $(PLATGEN_OPTIONS) $(MHSFILE)
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187 $(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
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188 @echo "Running synthesis..."
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189 bash -c "cd synthesis; ./synthesis.sh"
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191 __xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)
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192 @echo "*********************************************"
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193 @echo "Running Xilinx Implementation tools.."
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194 @echo "*********************************************"
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195 @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
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196 xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/manage_fastruntime_opt.pl $(MANAGE_FASTRT_OPTIONS)
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197 xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc
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198 touch __xps/$(SYSTEM)_routed
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200 $(SYSTEM_BIT): __xps/$(SYSTEM)_routed
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201 xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par
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202 @echo "*********************************************"
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203 @echo "Running Bitgen.."
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204 @echo "*********************************************"
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205 @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
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206 cd implementation; bitgen -w -f bitgen.ut $(SYSTEM)
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208 $(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt
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209 # @cp -f implementation/$(SYSTEM)_bd.bmm .
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210 @echo "*********************************************"
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211 @echo "Initializing BRAM contents of the bitstream"
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212 @echo "*********************************************"
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213 bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \
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214 -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
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215 @rm -f $(SYSTEM)_bd.bmm
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217 $(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT)
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218 @echo "*********************************************"
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219 @echo "Creating system ace file"
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220 @echo "*********************************************"
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221 xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE)
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223 #################################################################
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225 #################################################################
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228 ################## BEHAVIORAL SIMULATION ##################
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230 $(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
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231 $(BRAMINIT_ELF_FILES)
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232 @echo "*********************************************"
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233 @echo "Creating behavioral simulation models..."
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234 @echo "*********************************************"
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235 simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
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237 ################## STRUCTURAL SIMULATION ##################
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239 $(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
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240 $(BRAMINIT_ELF_FILES)
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241 @echo "*********************************************"
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242 @echo "Creating structural simulation models..."
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243 @echo "*********************************************"
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244 simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
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247 ################## TIMING SIMULATION ##################
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249 $(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \
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250 $(BRAMINIT_ELF_FILES)
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251 @echo "*********************************************"
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252 @echo "Creating timing simulation models..."
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253 @echo "*********************************************"
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254 simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
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256 #################################################################
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257 # VIRTUAL PLATFORM FLOW
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258 #################################################################
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261 $(VPEXEC): $(MHSFILE) __xps/vpgen.opt
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262 @echo "****************************************************"
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263 @echo "Creating virtual platform for hardware specification.."
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264 @echo "****************************************************"
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265 vpgen $(VPGEN_OPTIONS) $(MHSFILE)
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