2 # ##############################################################################
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3 # Created by Base System Builder Wizard for Xilinx EDK 10.1 Build EDK_K.15
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4 # Sun Mar 30 11:39:33 2008
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5 # Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
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10 # Processor: ppc405_0
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11 # Processor clock frequency: 100.00 MHz
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12 # Bus clock frequency: 100.00 MHz
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13 # Total Off Chip Memory : 1 MB
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15 # ##############################################################################
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16 PARAMETER VERSION = 2.1.0
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19 PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I
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20 PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O
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21 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
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22 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
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23 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [9:29]
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24 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3]
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25 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O
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26 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31]
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27 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0]
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28 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0]
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29 PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O
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30 PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O
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31 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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32 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
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35 BEGIN ppc405_virtex4
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36 PARAMETER INSTANCE = ppc405_0
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37 PARAMETER HW_VER = 2.01.a
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38 PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
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39 PARAMETER C_IDCR_BASEADDR = 0b0100000000
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40 PARAMETER C_IDCR_HIGHADDR = 0b0111111111
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41 BUS_INTERFACE JTAGPPC = jtagppc_0_0
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42 BUS_INTERFACE IPLB0 = plb
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43 BUS_INTERFACE DPLB0 = plb
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44 BUS_INTERFACE RESETPPC = ppc_reset_bus
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45 PORT CPMC405CLOCK = sys_clk_s
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46 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
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50 PARAMETER INSTANCE = jtagppc_0
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51 PARAMETER HW_VER = 2.01.a
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52 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
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56 PARAMETER INSTANCE = plb
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57 PARAMETER C_DCR_INTFCE = 0
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58 PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
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59 PARAMETER HW_VER = 1.02.a
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60 PORT PLB_Clk = sys_clk_s
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61 PORT SYS_Rst = sys_bus_reset
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65 PARAMETER INSTANCE = RS232_Uart
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66 PARAMETER HW_VER = 1.00.a
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67 PARAMETER C_BAUDRATE = 9600
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68 PARAMETER C_DATA_BITS = 8
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69 PARAMETER C_ODD_PARITY = 0
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70 PARAMETER C_USE_PARITY = 0
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71 PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000
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72 PARAMETER C_BASEADDR = 0x84000000
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73 PARAMETER C_HIGHADDR = 0x8400ffff
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74 BUS_INTERFACE SPLB = plb
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75 PORT RX = fpga_0_RS232_Uart_RX
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76 PORT TX = fpga_0_RS232_Uart_TX
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77 PORT Interrupt = RS232_Uart_Interrupt
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81 PARAMETER INSTANCE = LEDs_4Bit
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82 PARAMETER HW_VER = 1.00.a
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83 PARAMETER C_GPIO_WIDTH = 4
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84 PARAMETER C_IS_DUAL = 0
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85 PARAMETER C_IS_BIDIR = 1
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86 PARAMETER C_ALL_INPUTS = 0
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87 PARAMETER C_BASEADDR = 0x81420000
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88 PARAMETER C_HIGHADDR = 0x8142ffff
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89 BUS_INTERFACE SPLB = plb
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90 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
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94 PARAMETER INSTANCE = LEDs_Positions
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95 PARAMETER HW_VER = 1.00.a
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96 PARAMETER C_GPIO_WIDTH = 5
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97 PARAMETER C_IS_DUAL = 0
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98 PARAMETER C_IS_BIDIR = 1
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99 PARAMETER C_ALL_INPUTS = 0
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100 PARAMETER C_BASEADDR = 0x81400000
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101 PARAMETER C_HIGHADDR = 0x8140ffff
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102 BUS_INTERFACE SPLB = plb
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103 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
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107 PARAMETER INSTANCE = SRAM
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108 PARAMETER HW_VER = 1.01.a
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109 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000
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110 PARAMETER C_NUM_BANKS_MEM = 1
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111 PARAMETER C_MAX_MEM_WIDTH = 32
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112 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
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113 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
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114 PARAMETER C_MEM0_WIDTH = 32
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115 PARAMETER C_SYNCH_MEM_0 = 1
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116 PARAMETER C_TCEDV_PS_MEM_0 = 0
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117 PARAMETER C_TWC_PS_MEM_0 = 0
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118 PARAMETER C_TAVDV_PS_MEM_0 = 0
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119 PARAMETER C_TWP_PS_MEM_0 = 0
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120 PARAMETER C_THZCE_PS_MEM_0 = 0
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121 PARAMETER C_TLZWE_PS_MEM_0 = 0
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122 PARAMETER C_MEM0_BASEADDR = 0xfff00000
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123 PARAMETER C_MEM0_HIGHADDR = 0xffffffff
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124 BUS_INTERFACE SPLB = plb
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125 PORT Mem_A = fpga_0_SRAM_Mem_A_split
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126 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN
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127 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN
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128 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ
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129 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN
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130 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN
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131 PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN
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134 BEGIN util_bus_split
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135 PARAMETER INSTANCE = SRAM_util_bus_split_1
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136 PARAMETER HW_VER = 1.00.a
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137 PARAMETER C_SIZE_IN = 32
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138 PARAMETER C_LEFT_POS = 9
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139 PARAMETER C_SPLIT = 30
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140 PORT Sig = fpga_0_SRAM_Mem_A_split
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141 PORT Out1 = fpga_0_SRAM_Mem_A
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144 BEGIN clock_generator
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145 PARAMETER INSTANCE = clock_generator_0
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146 PARAMETER HW_VER = 2.01.a
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147 PARAMETER C_EXT_RESET_HIGH = 1
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148 PARAMETER C_CLKIN_FREQ = 100000000
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149 PARAMETER C_CLKOUT0_FREQ = 100000000
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150 PARAMETER C_CLKOUT0_BUF = TRUE
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151 PARAMETER C_CLKOUT0_PHASE = 0
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152 PARAMETER C_CLKOUT0_GROUP = NONE
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153 PORT CLKOUT0 = sys_clk_s
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154 PORT CLKIN = dcm_clk_s
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155 PORT LOCKED = Dcm_all_locked
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159 BEGIN proc_sys_reset
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160 PARAMETER INSTANCE = proc_sys_reset_0
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161 PARAMETER HW_VER = 2.00.a
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162 PARAMETER C_EXT_RESET_HIGH = 0
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163 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
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164 PORT Slowest_sync_clk = sys_clk_s
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165 PORT Dcm_locked = Dcm_all_locked
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166 PORT Ext_Reset_In = sys_rst_s
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167 PORT Bus_Struct_Reset = sys_bus_reset
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168 PORT Peripheral_Reset = sys_periph_reset
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172 PARAMETER INSTANCE = xps_intc_0
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173 PARAMETER HW_VER = 1.00.a
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174 PARAMETER C_BASEADDR = 0x81800000
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175 PARAMETER C_HIGHADDR = 0x8180ffff
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176 BUS_INTERFACE SPLB = plb
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177 PORT Irq = EICC405EXTINPUTIRQ
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178 PORT Intr = RS232_Uart_Interrupt
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