2 # ##############################################################################
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4 # Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
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6 # Tue Mar 04 08:41:46 2008
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8 # Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
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14 # Processor: PPC 405
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15 # Processor clock frequency: 100.000000 MHz
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16 # Bus clock frequency: 100.000000 MHz
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17 # Debug interface: FPGA JTAG
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19 # Instruction Cache: 16 KB
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20 # On Chip Memory : 4 KB
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21 # Total Off Chip Memory : 1 MB
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22 # - SRAM_256Kx32 = 1 MB
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24 # ##############################################################################
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27 PARAMETER VERSION = 2.1.0
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30 PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I
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31 PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O
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32 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
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33 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
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34 PORT fpga_0_SRAM_256Kx32_Mem_A_pin = fpga_0_SRAM_256Kx32_Mem_A, DIR = O, VEC = [9:29]
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35 PORT fpga_0_SRAM_256Kx32_Mem_BEN_pin = fpga_0_SRAM_256Kx32_Mem_BEN, DIR = O, VEC = [0:3]
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36 PORT fpga_0_SRAM_256Kx32_Mem_WEN_pin = fpga_0_SRAM_256Kx32_Mem_WEN, DIR = O
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37 PORT fpga_0_SRAM_256Kx32_Mem_DQ_pin = fpga_0_SRAM_256Kx32_Mem_DQ, DIR = IO, VEC = [0:31]
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38 PORT fpga_0_SRAM_256Kx32_Mem_OEN_pin = fpga_0_SRAM_256Kx32_Mem_OEN, DIR = O, VEC = [0:0]
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39 PORT fpga_0_SRAM_256Kx32_Mem_CEN_pin = fpga_0_SRAM_256Kx32_Mem_CEN, DIR = O, VEC = [0:0]
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40 PORT fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin = fpga_0_SRAM_256Kx32_Mem_ADV_LDN, DIR = O
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41 PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O
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42 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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43 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
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46 BEGIN ppc405_virtex4
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47 PARAMETER INSTANCE = ppc405_0
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48 PARAMETER HW_VER = 1.01.a
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49 BUS_INTERFACE JTAGPPC = jtagppc_0_0
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50 BUS_INTERFACE IPLB = plb
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51 BUS_INTERFACE DPLB = plb
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52 PORT PLBCLK = sys_clk_s
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53 PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
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54 PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
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55 PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
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56 PORT RSTC405RESETCHIP = RSTC405RESETCHIP
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57 PORT RSTC405RESETCORE = RSTC405RESETCORE
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58 PORT RSTC405RESETSYS = RSTC405RESETSYS
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59 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
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60 PORT CPMC405CLOCK = sys_clk_s
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64 PARAMETER INSTANCE = jtagppc_0
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65 PARAMETER HW_VER = 2.00.a
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66 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
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69 BEGIN proc_sys_reset
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70 PARAMETER INSTANCE = reset_block
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71 PARAMETER HW_VER = 1.00.a
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72 PARAMETER C_EXT_RESET_HIGH = 0
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73 PORT Ext_Reset_In = sys_rst_s
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74 PORT Slowest_sync_clk = sys_clk_s
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75 PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
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76 PORT Core_Reset_Req = C405RSTCORERESETREQ
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77 PORT System_Reset_Req = C405RSTSYSRESETREQ
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78 PORT Rstc405resetchip = RSTC405RESETCHIP
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79 PORT Rstc405resetcore = RSTC405RESETCORE
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80 PORT Rstc405resetsys = RSTC405RESETSYS
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81 PORT Bus_Struct_Reset = sys_bus_reset
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82 PORT Dcm_locked = dcm_0_lock
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86 PARAMETER INSTANCE = plb
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87 PARAMETER HW_VER = 1.02.a
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88 PARAMETER C_DCR_INTFCE = 0
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89 PARAMETER C_EXT_RESET_HIGH = 1
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90 PORT SYS_Rst = sys_bus_reset
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91 PORT PLB_Clk = sys_clk_s
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95 PARAMETER INSTANCE = opb
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96 PARAMETER HW_VER = 1.10.c
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97 PARAMETER C_EXT_RESET_HIGH = 1
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98 PORT SYS_Rst = sys_bus_reset
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99 PORT OPB_Clk = sys_clk_s
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102 BEGIN plb2opb_bridge
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103 PARAMETER INSTANCE = plb2opb
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104 PARAMETER HW_VER = 1.01.a
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105 PARAMETER C_DCR_INTFCE = 0
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106 PARAMETER C_NUM_ADDR_RNG = 1
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107 PARAMETER C_RNG0_BASEADDR = 0x40000000
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108 PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
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109 BUS_INTERFACE SPLB = plb
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110 BUS_INTERFACE MOPB = opb
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114 PARAMETER INSTANCE = RS232_Uart
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115 PARAMETER HW_VER = 1.00.b
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116 PARAMETER C_BAUDRATE = 115200
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117 PARAMETER C_DATA_BITS = 8
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118 PARAMETER C_ODD_PARITY = 0
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119 PARAMETER C_USE_PARITY = 0
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120 PARAMETER C_CLK_FREQ = 100000000
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121 PARAMETER C_BASEADDR = 0x40600000
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122 PARAMETER C_HIGHADDR = 0x4060ffff
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123 BUS_INTERFACE SOPB = opb
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124 PORT Interrupt = RS232_Uart_Interrupt
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125 PORT RX = fpga_0_RS232_Uart_RX
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126 PORT TX = fpga_0_RS232_Uart_TX
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130 PARAMETER INSTANCE = LEDs_4Bit
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131 PARAMETER HW_VER = 3.01.b
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132 PARAMETER C_GPIO_WIDTH = 4
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133 PARAMETER C_IS_DUAL = 0
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134 PARAMETER C_IS_BIDIR = 1
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135 PARAMETER C_ALL_INPUTS = 0
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136 PARAMETER C_BASEADDR = 0x40000000
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137 PARAMETER C_HIGHADDR = 0x4000ffff
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138 BUS_INTERFACE SOPB = opb
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139 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
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143 PARAMETER INSTANCE = LEDs_Positions
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144 PARAMETER HW_VER = 3.01.b
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145 PARAMETER C_GPIO_WIDTH = 5
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146 PARAMETER C_IS_DUAL = 0
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147 PARAMETER C_IS_BIDIR = 1
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148 PARAMETER C_ALL_INPUTS = 0
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149 PARAMETER C_BASEADDR = 0x40020000
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150 PARAMETER C_HIGHADDR = 0x4002ffff
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151 BUS_INTERFACE SOPB = opb
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152 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
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156 PARAMETER INSTANCE = SRAM_256Kx32
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157 PARAMETER HW_VER = 2.00.a
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158 PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1
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159 PARAMETER C_PLB_CLK_PERIOD_PS = 10000
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160 PARAMETER C_NUM_BANKS_MEM = 1
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161 PARAMETER C_MAX_MEM_WIDTH = 32
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162 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
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163 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
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164 PARAMETER C_MEM0_WIDTH = 32
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165 PARAMETER C_SYNCH_MEM_0 = 1
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166 PARAMETER C_TCEDV_PS_MEM_0 = 0
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167 PARAMETER C_TWC_PS_MEM_0 = 0
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168 PARAMETER C_TAVDV_PS_MEM_0 = 0
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169 PARAMETER C_TWP_PS_MEM_0 = 0
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170 PARAMETER C_THZCE_PS_MEM_0 = 0
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171 PARAMETER C_TLZWE_PS_MEM_0 = 0
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172 PARAMETER C_MEM0_BASEADDR = 0x00000000
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173 PARAMETER C_MEM0_HIGHADDR = 0x000fffff
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174 BUS_INTERFACE SPLB = plb
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175 PORT Mem_A = fpga_0_SRAM_256Kx32_Mem_A_split
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176 PORT Mem_BEN = fpga_0_SRAM_256Kx32_Mem_BEN
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177 PORT Mem_WEN = fpga_0_SRAM_256Kx32_Mem_WEN
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178 PORT Mem_DQ = fpga_0_SRAM_256Kx32_Mem_DQ
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179 PORT Mem_OEN = fpga_0_SRAM_256Kx32_Mem_OEN
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180 PORT Mem_CEN = fpga_0_SRAM_256Kx32_Mem_CEN
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181 PORT Mem_ADV_LDN = fpga_0_SRAM_256Kx32_Mem_ADV_LDN
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184 BEGIN plb_bram_if_cntlr
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185 PARAMETER INSTANCE = plb_bram_if_cntlr_1
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186 PARAMETER HW_VER = 1.00.b
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187 PARAMETER c_include_burst_cacheln_support = 0
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188 PARAMETER c_plb_clk_period_ps = 10000
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189 PARAMETER c_baseaddr = 0xfffff000
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190 PARAMETER c_highaddr = 0xffffffff
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191 BUS_INTERFACE SPLB = plb
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192 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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196 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
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197 PARAMETER HW_VER = 1.00.a
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198 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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202 PARAMETER INSTANCE = opb_intc_0
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203 PARAMETER HW_VER = 1.00.c
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204 PARAMETER C_BASEADDR = 0x41200000
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205 PARAMETER C_HIGHADDR = 0x4120ffff
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206 BUS_INTERFACE SOPB = opb
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207 PORT Irq = EICC405EXTINPUTIRQ
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208 PORT Intr = RS232_Uart_Interrupt
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211 BEGIN util_bus_split
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212 PARAMETER INSTANCE = SRAM_256Kx32_util_bus_split_0
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213 PARAMETER HW_VER = 1.00.a
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214 PARAMETER C_SIZE_IN = 32
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215 PARAMETER C_LEFT_POS = 9
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216 PARAMETER C_SPLIT = 30
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217 PORT Sig = fpga_0_SRAM_256Kx32_Mem_A_split
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218 PORT Out1 = fpga_0_SRAM_256Kx32_Mem_A
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222 PARAMETER INSTANCE = dcm_0
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223 PARAMETER HW_VER = 1.00.a
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224 PARAMETER C_CLK0_BUF = TRUE
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225 PARAMETER C_CLKIN_PERIOD = 10.000000
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226 PARAMETER C_CLK_FEEDBACK = 1X
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227 PARAMETER C_DLL_FREQUENCY_MODE = LOW
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228 PARAMETER C_EXT_RESET_HIGH = 1
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229 PORT CLKIN = dcm_clk_s
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230 PORT CLK0 = sys_clk_s
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231 PORT CLKFB = sys_clk_s
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233 PORT LOCKED = dcm_0_lock
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