git.sur5r.net Git - freertos/blob - Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system.log

   1 No logfile was found.\r
   2 \r
   3 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
   4 \r
   5 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
   6 \r
   7 Generating Block Diagram to Buffer
   8 \r
   9 Generated Block Diagram SVG
  10 \r
  11 The project file (XMP) has changed on disk.
  12 \r
  13 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
  14 \r
  15 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
  16 \r
  17 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
  18 \r
  19 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
  20 \r
  21 At Local date and time: Tue Jun 30 18:36:00 2009
  22  make -f system.make netlistclean started...
  23 \r
  24 rm -f implementation/system.ngc\r
  25 rm -f platgen.log\r
  26 rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
  27 rm -f implementation/system.bmm\r
  28 \r
  29 \r
  30 Done!
  31 \r
  32 At Local date and time: Tue Jun 30 18:36:05 2009
  33  make -f system.make bitsclean started...
  34 \r
  35 rm -f implementation/system.bit\r
  36 rm -f implementation/system.ncd\r
  37 rm -f implementation/system_bd.bmm \r
  38 rm -f implementation/system_map.ncd \r
  39 rm -f __xps/system_routed\r
  40 \r
  41 \r
  42 Done!
  43 \r
  44 At Local date and time: Tue Jun 30 18:36:10 2009
  45  make -f system.make hwclean started...
  46 \r
  47 rm -f implementation/system.ngc\r
  48 rm -f platgen.log\r
  49 rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
  50 rm -f implementation/system.bmm\r
  51 rm -f implementation/system.bit\r
  52 rm -f implementation/system.ncd\r
  53 rm -f implementation/system_bd.bmm \r
  54 rm -f implementation/system_map.ncd \r
  55 rm -f __xps/system_routed\r
  56 rm -rf implementation synthesis xst hdl\r
  57 rm -rf xst.srp system.srp\r
  58 rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
  59 \r
  60 \r
  61 Done!
  62 \r
  63 At Local date and time: Tue Jun 30 18:36:16 2009
  64  make -f system.make libsclean started...
  65 \r
  66 rm -rf ppc440_0/\r
  67 rm -f libgen.log\r
  68 rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
  69 \r
  70 \r
  71 Done!
  72 \r
  73 At Local date and time: Tue Jun 30 18:36:20 2009
  74  make -f system.make programclean started...
  75 \r
  76 rm -f RTOSDemo/executable.elf \r
  77 \r
  78 \r
  79 Done!
  80 \r
  81 At Local date and time: Tue Jun 30 18:36:25 2009
  82  make -f system.make swclean started...
  83 \r
  84 rm -rf ppc440_0/\r
  85 rm -f libgen.log\r
  86 rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
  87 rm -f RTOSDemo/executable.elf \r
  88 \r
  89 \r
  90 Done!
  91 \r
  92 Writing filter settings....
  93 \r
  94 Done writing filter settings to:
  95         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
  96 \r
  97 Done writing Tab View settings to:
  98         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
  99 \r
 100 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 101 \r
 102 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 103 \r
 104 Generating Block Diagram to Buffer
 105 \r
 106 Generated Block Diagram SVG
 107 \r
 108 At Local date and time: Tue Jun 30 22:00:27 2009
 109  make -f system.make bits started...
 110 \r
 111 ****************************************************\r
 112 Creating system netlist for hardware specification..\r
 113 ****************************************************\r
 114 platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs\r
 115 \r\r
 116 Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47\r\r
 117  (nt)\r\r
 118 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 119 \r\r
 120 \r\r
 121 Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg\r\r
 122 __xps/ise/xmsgprops.lst system.mhs \r\r
 123 \r\r
 124 Parse\r\r
 125 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/system.mhs\r\r
 126 ...\r\r
 127 \r\r
 128 Read MPD definitions ...\r\r
 129 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 130    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 131    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
 132 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 133    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 134    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
 135 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 136    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 137    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
 138 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 139    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 140    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
 141 \r\r
 142 Overriding IP level properties ...\r\r
 143 \r\r
 144 Performing IP level DRCs on properties...\r\r
 145 \r\r
 146 Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
 147 Address Map for Processor ppc440_0\r\r
 148   (0b0000000000-0b0011111111) ppc440_0  \r\r
 149   (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC\r\r
 150   (0x81000000-0x8100ffff) Ethernet_MAC  plb_v46_0\r\r
 151   (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0\r\r
 152   (0x81420000-0x8142ffff) LEDs_Positions        plb_v46_0\r\r
 153   (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0\r\r
 154   (0x81460000-0x8146ffff) DIP_Switches_8Bit     plb_v46_0\r\r
 155   (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0\r\r
 156   (0x81800000-0x8180ffff) xps_intc_0    plb_v46_0\r\r
 157   (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0\r\r
 158   (0x84000000-0x8400ffff) RS232_Uart_1  plb_v46_0\r\r
 159   (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0\r\r
 160   (0xc0000000-0xdfffffff) PCIe_Bridge   plb_v46_0\r\r
 161   (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0\r\r
 162   (0xf8000000-0xf80fffff) SRAM  plb_v46_0\r\r
 163   (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0\r\r
 164 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
 165    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
 166    01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
 167    C_SPLB0_P2P value to 0\r\r
 168 \r\r
 169 Computing clock values...\r\r
 170 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
 171    'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
 172    performed for IPs connected to that clock port, unless they are connected\r\r
 173    through the clock generator IP. \r\r
 174 \r\r
 175 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
 176    'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
 177    performed for IPs connected to that clock port, unless they are connected\r\r
 178    through the clock generator IP. \r\r
 179 \r\r
 180 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 181    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 182    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
 183    C_PLBV46_NUM_MASTERS value to 1\r\r
 184 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 185    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 186    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
 187    C_PLBV46_NUM_SLAVES value to 12\r\r
 188 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 189    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 190    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
 191    C_PLBV46_MID_WIDTH value to 1\r\r
 192 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 193    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 194    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
 195    value to 128\r\r
 196 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
 197    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
 198    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
 199    PARAMETER C_SPLB_DWIDTH value to 128\r\r
 200 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
 201    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
 202    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
 203    PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
 204 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
 205    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
 206    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
 207    PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
 208 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 209    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
 210    \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
 211    value to 0x2000\r\r
 212 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 213    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
 214    \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
 215    C_PORT_DWIDTH value to 64\r\r
 216 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 217    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
 218    \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
 219    value to 8\r\r
 220 INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
 221    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
 222    _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
 223    C_SPLB_DWIDTH value to 128\r\r
 224 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
 225    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 226    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 227    value to 128\r\r
 228 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
 229    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 230    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 231    value to 128\r\r
 232 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
 233    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 234    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 235    value to 128\r\r
 236 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
 237    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 238    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 239    value to 128\r\r
 240 INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
 241    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
 242    ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 243    value to 128\r\r
 244 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
 245    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
 246    a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
 247    C_SPLB_DWIDTH value to 128\r\r
 248 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
 249    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
 250    a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
 251    C_SPLB_SMALLEST_MASTER value to 128\r\r
 252 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 253    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 254    b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
 255    C_MPLB_DWIDTH value to 128\r\r
 256 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 257    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 258    b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
 259    C_MPLB_SMALLEST_SLAVE value to 128\r\r
 260 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 261    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 262    b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
 263    C_SPLB_MID_WIDTH value to 1\r\r
 264 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 265    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 266    b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
 267    C_SPLB_NUM_MASTERS value to 1\r\r
 268 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 269    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 270    b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
 271    C_SPLB_SMALLEST_MASTER value to 128\r\r
 272 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 273    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 274    b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
 275    C_SPLB_DWIDTH value to 128\r\r
 276 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 277    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 278    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
 279    C_PLBV46_NUM_MASTERS value to 1\r\r
 280 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 281    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 282    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
 283    C_PLBV46_NUM_SLAVES value to 1\r\r
 284 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 285    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 286    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
 287    C_PLBV46_MID_WIDTH value to 1\r\r
 288 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 289    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 290    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
 291    value to 128\r\r
 292 INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 293    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
 294    2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
 295    PARAMETER C_SPLB_DWIDTH value to 128\r\r
 296 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
 297    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
 298    \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
 299    C_SPLB_DWIDTH value to 128\r\r
 300 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
 301    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
 302    \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
 303    C_SPLB_MID_WIDTH value to 1\r\r
 304 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
 305    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
 306    \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
 307    C_SPLB_NUM_MASTERS value to 1\r\r
 308 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 309    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 310    ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 311    value to 128\r\r
 312 \r\r
 313 Checking platform address map ...\r\r
 314 \r\r
 315 Checking platform configuration ...\r\r
 316 INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 317    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 318    hs line 298 - This design requires design constraints to guarantee\r\r
 319    performance.\r\r
 320    Please refer to the xps_ethernetlite_v2_00_a data sheet for details.  \r\r
 321    The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs\r\r
 322    Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet\r\r
 323    operation.\r\r
 324 IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 325 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 326 line 109 - 1 master(s) : 12 slave(s)\r\r
 327 IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 328 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 329 line 290 - 1 master(s) : 1 slave(s)\r\r
 330 IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -\r\r
 331 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 332 line 394 - 1 master(s) : 1 slave(s)\r\r
 333 \r\r
 334 Checking port drivers...\r\r
 335 WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
 336    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 337    hs line 461 - floating connection!\r\r
 338 \r\r
 339 Performing Clock DRCs...\r\r
 340 \r\r
 341 Performing Reset DRCs...\r\r
 342 \r\r
 343 Overriding system level properties...\r\r
 344 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
 345    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
 346    01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER\r\r
 347    C_PPC440MC_ADDR_BASE value to 0x00000000\r\r
 348 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
 349    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
 350    01_a\data\ppc440_virtex5_v2_1_0.mpd line 125 - tcl is overriding PARAMETER\r\r
 351    C_PPC440MC_ADDR_HIGH value to 0x0fffffff\r\r
 352 INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -\r\r
 353    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0\r\r
 354    1_c\data\jtagppc_cntlr_v2_1_0.mpd line 70 - tcl is overriding PARAMETER\r\r
 355    C_NUM_PPC_USED value to 1\r\r
 356 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 357    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 358    ata\xps_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR\r\r
 359    value to 0b00000000000000000000000000000001\r\r
 360 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 361    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 362    ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE\r\r
 363    value to 0b00000000000000000000000000000001\r\r
 364 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 365    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 366    ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL\r\r
 367    value to 0b00000000000000000000000000000000\r\r
 368 \r\r
 369 Running system level update procedures...\r\r
 370 \r\r
 371 Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
 372 \r\r
 373 Running system level DRCs...\r\r
 374 \r\r
 375 Performing System level DRCs on properties...\r\r
 376 \r\r
 377 Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
 378 \r\r
 379 Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...\r\r
 380 INFO: The PCIe_Bridge core has constraints automatically generated by XPS in\r\r
 381 implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.\r\r\r
 382 It can be overridden by constraints placed in the system.ucf file.\r\r\r
 383 \r\r
 384 \r\r\r
 385 \r\r
 386 INFO: The Ethernet_MAC core has constraints automatically generated by XPS in\r\r
 387 implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.\r\r\r
 388 It can be overridden by constraints placed in the system.ucf file.\r\r\r
 389 \r\r
 390 \r\r\r
 391 \r\r
 392 INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in\r\r
 393 implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.\r\r\r
 394 It can be overridden by constraints placed in the system.ucf file.\r\r\r
 395 \r\r
 396 \r\r\r
 397 \r\r
 398 \r\r
 399 Modify defaults ...\r\r
 400 \r\r
 401 Creating stub ...\r\r
 402 \r\r
 403 Processing licensed instances ...\r\r
 404 Completion time: 0.00 seconds\r\r
 405 \r\r
 406 Creating hardware output directories ...\r\r
 407 \r\r
 408 Managing hardware (BBD-specified) netlist files ...\r\r
 409 IPNAME:plbv46_pcie INSTANCE:pcie_bridge -\r\r
 410 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 411 line 253 - Copying (BBD-specified) netlist files.\r\r
 412 IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -\r\r
 413 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 414 line 298 - Copying (BBD-specified) netlist files.\r\r
 415 IPNAME:apu_fpu_virtex5 INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
 416 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 417 line 401 - Copying (BBD-specified) netlist files.\r\r
 418 \r\r
 419 Managing cache ...\r\r
 420 \r\r
 421 Elaborating instances ...\r\r
 422 IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 423 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 424 line 131 - elaborating IP\r\r
 425 \r\r
 426 Writing HDL for elaborated instances ...\r\r
 427 \r\r
 428 Inserting wrapper level ...\r\r
 429 Completion time: 0.00 seconds\r\r
 430 \r\r
 431 Constructing platform-level connectivity ...\r\r
 432 Completion time: 1.00 seconds\r\r
 433 \r\r
 434 Writing (top-level) BMM ...\r\r
 435 \r\r
 436 Writing (top-level and wrappers) HDL ...\r\r
 437 \r\r
 438 Generating synthesis project file ...\r\r
 439 \r\r
 440 Running XST synthesis ...\r\r
 441 \r\r
 442 INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option\r\r
 443    IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST\r\r
 444    synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. \r\r
 445 INSTANCE:ppc440_0 -\r\r
 446 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 447 line 78 - Running XST synthesis\r\r
 448 INSTANCE:plb_v46_0 -\r\r
 449 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 450 line 109 - Running XST synthesis\r\r
 451 INSTANCE:xps_bram_if_cntlr_1 -\r\r
 452 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 453 line 118 - Running XST synthesis\r\r
 454 INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 455 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 456 line 131 - Running XST synthesis\r\r
 457 INSTANCE:rs232_uart_1 -\r\r
 458 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 459 line 138 - Running XST synthesis\r\r
 460 INSTANCE:leds_8bit -\r\r
 461 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 462 line 154 - Running XST synthesis\r\r
 463 INSTANCE:leds_positions -\r\r
 464 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 465 line 168 - Running XST synthesis\r\r
 466 INSTANCE:push_buttons_5bit -\r\r
 467 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 468 line 182 - Running XST synthesis\r\r
 469 INSTANCE:dip_switches_8bit -\r\r
 470 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 471 line 196 - Running XST synthesis\r\r
 472 INSTANCE:iic_eeprom -\r\r
 473 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 474 line 210 - Running XST synthesis\r\r
 475 INSTANCE:sram -\r\r
 476 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 477 line 223 - Running XST synthesis\r\r
 478 INSTANCE:pcie_bridge -\r\r
 479 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 480 line 253 - Running XST synthesis\r\r
 481 INSTANCE:ppc440_0_splb0 -\r\r
 482 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 483 line 290 - Running XST synthesis\r\r
 484 INSTANCE:ethernet_mac -\r\r
 485 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 486 line 298 - Running XST synthesis\r\r
 487 INSTANCE:ddr2_sdram -\r\r
 488 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 489 line 317 - Running XST synthesis\r\r
 490 INSTANCE:sysace_compactflash -\r\r
 491 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 492 line 377 - Running XST synthesis\r\r
 493 INSTANCE:ppc440_0_fcb_v20 -\r\r
 494 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 495 line 394 - Running XST synthesis\r\r
 496 INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
 497 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 498 line 401 - Running XST synthesis\r\r
 499 INSTANCE:clock_generator_0 -\r\r
 500 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 501 line 407 - Running XST synthesis\r\r
 502 INSTANCE:jtagppc_cntlr_inst -\r\r
 503 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 504 line 446 - Running XST synthesis\r\r
 505 INSTANCE:proc_sys_reset_0 -\r\r
 506 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 507 line 452 - Running XST synthesis\r\r
 508 INSTANCE:xps_intc_0 -\r\r
 509 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 510 line 464 - Running XST synthesis\r\r
 511 \r\r
 512 Running NGCBUILD ...\r\r
 513 IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -\r\r
 514 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 515 line 78 - Running NGCBUILD\r\r
 516 PMSPEC -- Overriding Xilinx file\r\r
 517 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 518 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 519 \r\r
 520 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 521 xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..\r\r
 522 ppc440_0_wrapper.ngc ../ppc440_0_wrapper.ngc\r\r
 523 \r\r
 524 Reading NGO file\r\r
 525 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 526 tion/ppc440_0_wrapper/ppc440_0_wrapper.ngc" ...\r\r
 527 \r\r
 528 Applying constraints in "ppc440_0_wrapper.ucf" to the design...\r\r
 529 \r\r
 530 Partition Implementation Status\r\r
 531 -------------------------------\r\r
 532 \r\r
 533   No Partitions were found in this design.\r\r
 534 \r\r
 535 -------------------------------\r\r
 536 \r\r
 537 NGCBUILD Design Results Summary:\r\r
 538   Number of errors:     0\r\r
 539   Number of warnings:   0\r\r
 540 \r\r
 541 Writing NGC file "../ppc440_0_wrapper.ngc" ...\r\r
 542 Total REAL time to NGCBUILD completion:  6 sec\r\r
 543 Total CPU time to NGCBUILD completion:   6 sec\r\r
 544 \r\r
 545 Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...\r\r
 546 \r\r
 547 NGCBUILD done.\r\r
 548 IPNAME:rs232_uart_1_wrapper INSTANCE:rs232_uart_1 -\r\r
 549 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 550 line 138 - Running NGCBUILD\r\r
 551 PMSPEC -- Overriding Xilinx file\r\r
 552 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 553 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 554 \r\r
 555 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 556 xc5vfx70tff1136-1 -intstyle silent -sd .. rs232_uart_1_wrapper.ngc\r\r
 557 ../rs232_uart_1_wrapper.ngc\r\r
 558 \r\r
 559 Reading NGO file\r\r
 560 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 561 tion/rs232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...\r\r
 562 \r\r
 563 Partition Implementation Status\r\r
 564 -------------------------------\r\r
 565 \r\r
 566   No Partitions were found in this design.\r\r
 567 \r\r
 568 -------------------------------\r\r
 569 \r\r
 570 NGCBUILD Design Results Summary:\r\r
 571   Number of errors:     0\r\r
 572   Number of warnings:   0\r\r
 573 \r\r
 574 Writing NGC file "../rs232_uart_1_wrapper.ngc" ...\r\r
 575 Total REAL time to NGCBUILD completion:  2 sec\r\r
 576 Total CPU time to NGCBUILD completion:   2 sec\r\r
 577 \r\r
 578 Writing NGCBUILD log file "../rs232_uart_1_wrapper.blc"...\r\r
 579 \r\r
 580 NGCBUILD done.\r\r
 581 IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -\r\r
 582 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 583 line 253 - Running NGCBUILD\r\r
 584 PMSPEC -- Overriding Xilinx file\r\r
 585 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 586 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 587 \r\r
 588 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 589 xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..\r\r
 590 pcie_bridge_wrapper.ngc ../pcie_bridge_wrapper.ngc\r\r
 591 \r\r
 592 Reading NGO file\r\r
 593 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 594 tion/pcie_bridge_wrapper/pcie_bridge_wrapper.ngc" ...\r\r
 595 Executing edif2ngd -noa\r\r
 596 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 597 tion\pcie_bridge_wrapper_fifo_generator_v4_3.edn"\r\r
 598 "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"\r\r
 599 Release 11.2 - edif2ngd L.46 (nt)\r\r
 600 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 601 INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
 602 INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 603 PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
 604 with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
 605 Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
 606 Loading design module\r\r
 607 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 608 tion\pcie_bridge_wrapper\pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
 609 Loading design module\r\r
 610 "../pcie_bridge_wrapper_fifo_generator_v4_3_fifo_generator_v4_3_xst_1.ngc"...\r\r
 611 Loading design module\r\r
 612 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 613 tion\pcie_bridge_wrapper/dpram_70_512.ngc"...\r\r
 614 Loading design module\r\r
 615 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 616 tion\pcie_bridge_wrapper/fifo_71x512.ngc"...\r\r
 617 \r\r
 618 Applying constraints in "pcie_bridge_wrapper.ucf" to the design...\r\r
 619 \r\r
 620 Partition Implementation Status\r\r
 621 -------------------------------\r\r
 622 \r\r
 623   No Partitions were found in this design.\r\r
 624 \r\r
 625 -------------------------------\r\r
 626 \r\r
 627 NGCBUILD Design Results Summary:\r\r
 628   Number of errors:     0\r\r
 629   Number of warnings:   0\r\r
 630 \r\r
 631 Writing NGC file "../pcie_bridge_wrapper.ngc" ...\r\r
 632 Total REAL time to NGCBUILD completion:  13 sec\r\r
 633 Total CPU time to NGCBUILD completion:   9 sec\r\r
 634 \r\r
 635 Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...\r\r
 636 \r\r
 637 NGCBUILD done.\r\r
 638 IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -\r\r
 639 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 640 line 298 - Running NGCBUILD\r\r
 641 PMSPEC -- Overriding Xilinx file\r\r
 642 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 643 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 644 \r\r
 645 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 646 xc5vfx70tff1136-1 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..\r\r
 647 ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc\r\r
 648 \r\r
 649 Reading NGO file\r\r
 650 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 651 tion/ethernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...\r\r
 652 Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"\r\r
 653 "ethernetlite_v1_01_b_dmem_v2.ngo"\r\r
 654 Release 11.2 - edif2ngd L.46 (nt)\r\r
 655 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 656 INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
 657 INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 658 PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
 659 with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
 660 Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
 661 Loading design module\r\r
 662 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 663 tion\ethernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
 664 \r\r
 665 Applying constraints in "ethernet_mac_wrapper.ucf" to the design...\r\r
 666 \r\r
 667 Partition Implementation Status\r\r
 668 -------------------------------\r\r
 669 \r\r
 670   No Partitions were found in this design.\r\r
 671 \r\r
 672 -------------------------------\r\r
 673 \r\r
 674 NGCBUILD Design Results Summary:\r\r
 675   Number of errors:     0\r\r
 676   Number of warnings:   0\r\r
 677 \r\r
 678 Writing NGC file "../ethernet_mac_wrapper.ngc" ...\r\r
 679 Total REAL time to NGCBUILD completion:  9 sec\r\r
 680 Total CPU time to NGCBUILD completion:   6 sec\r\r
 681 \r\r
 682 Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...\r\r
 683 \r\r
 684 NGCBUILD done.\r\r
 685 IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -\r\r
 686 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 687 line 317 - Running NGCBUILD\r\r
 688 PMSPEC -- Overriding Xilinx file\r\r
 689 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 690 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 691 \r\r
 692 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 693 xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..\r\r
 694 ddr2_sdram_wrapper.ngc ../ddr2_sdram_wrapper.ngc\r\r
 695 \r\r
 696 Reading NGO file\r\r
 697 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 698 tion/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...\r\r
 699 \r\r
 700 Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...\r\r
 701 \r\r
 702 Partition Implementation Status\r\r
 703 -------------------------------\r\r
 704 \r\r
 705   No Partitions were found in this design.\r\r
 706 \r\r
 707 -------------------------------\r\r
 708 \r\r
 709 NGCBUILD Design Results Summary:\r\r
 710   Number of errors:     0\r\r
 711   Number of warnings:   0\r\r
 712 \r\r
 713 Writing NGC file "../ddr2_sdram_wrapper.ngc" ...\r\r
 714 Total REAL time to NGCBUILD completion:  7 sec\r\r
 715 Total CPU time to NGCBUILD completion:   7 sec\r\r
 716 \r\r
 717 Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...\r\r
 718 \r\r
 719 NGCBUILD done.\r\r
 720 IPNAME:ppc440_0_apu_fpu_virtex5_wrapper INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
 721 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 722 line 401 - Running NGCBUILD\r\r
 723 PMSPEC -- Overriding Xilinx file\r\r
 724 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 725 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 726 \r\r
 727 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 728 xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_apu_fpu_virtex5_wrapper.ucf -sd\r\r
 729 .. ppc440_0_apu_fpu_virtex5_wrapper.ngc ../ppc440_0_apu_fpu_virtex5_wrapper.ngc\r\r
 730 \r\r
 731 Reading NGO file\r\r
 732 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 733 tion/ppc440_0_apu_fpu_virtex5_wrapper/ppc440_0_apu_fpu_virtex5_wrapper.ngc" ...\r\r
 734 Loading design module\r\r
 735 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 736 tion\ppc440_0_apu_fpu_virtex5_wrapper/apu_fpu_dp_lo.ngc"...\r\r
 737 \r\r
 738 Applying constraints in "ppc440_0_apu_fpu_virtex5_wrapper.ucf" to the design...\r\r
 739 \r\r
 740 Partition Implementation Status\r\r
 741 -------------------------------\r\r
 742 \r\r
 743   No Partitions were found in this design.\r\r
 744 \r\r
 745 -------------------------------\r\r
 746 \r\r
 747 NGCBUILD Design Results Summary:\r\r
 748   Number of errors:     0\r\r
 749   Number of warnings:   0\r\r
 750 \r\r
 751 Writing NGC file "../ppc440_0_apu_fpu_virtex5_wrapper.ngc" ...\r\r
 752 Total REAL time to NGCBUILD completion:  7 sec\r\r
 753 Total CPU time to NGCBUILD completion:   7 sec\r\r
 754 \r\r
 755 Writing NGCBUILD log file "../ppc440_0_apu_fpu_virtex5_wrapper.blc"...\r\r
 756 \r\r
 757 NGCBUILD done.\r\r
 758 IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -\r\r
 759 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 760 line 464 - Running NGCBUILD\r\r
 761 PMSPEC -- Overriding Xilinx file\r\r
 762 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 763 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 764 \r\r
 765 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 766 xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc\r\r
 767 ../xps_intc_0_wrapper.ngc\r\r
 768 \r\r
 769 Reading NGO file\r\r
 770 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 771 tion/xps_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...\r\r
 772 \r\r
 773 Partition Implementation Status\r\r
 774 -------------------------------\r\r
 775 \r\r
 776   No Partitions were found in this design.\r\r
 777 \r\r
 778 -------------------------------\r\r
 779 \r\r
 780 NGCBUILD Design Results Summary:\r\r
 781   Number of errors:     0\r\r
 782   Number of warnings:   0\r\r
 783 \r\r
 784 Writing NGC file "../xps_intc_0_wrapper.ngc" ...\r\r
 785 Total REAL time to NGCBUILD completion:  2 sec\r\r
 786 Total CPU time to NGCBUILD completion:   2 sec\r\r
 787 \r\r
 788 Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...\r\r
 789 \r\r
 790 NGCBUILD done.\r\r
 791 \r\r
 792 Rebuilding cache ...\r\r
 793 \r\r
 794 Total run time: 1120.00 seconds\r\r
 795 Running synthesis...\r
 796 bash -c "cd synthesis; ./synthesis.sh"\r
 797 xst -ifn system_xst.scr -intstyle silent\r
 798 Running XST synthesis ...\r
 799 XST completed\r
 800 Release 11.2 - ngcbuild L.46 (nt)\r\r
 801 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 802 Overriding Xilinx file <ngcflow.csf> with local file\r\r
 803 <c:/devtools/Xilinx/11.1/ISE/data/ngcflow.csf>\r\r
 804 \r\r
 805 Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe\r\r
 806 ./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise\r\r
 807 ../__xps/ise/system.ise\r\r
 808 \r\r
 809 Reading NGO file\r\r
 810 "c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/synthesis/\r\r
 811 system.ngc" ...\r\r
 812 Loading design module "../implementation/ppc440_0_wrapper.ngc"...\r\r
 813 Loading design module "../implementation/plb_v46_0_wrapper.ngc"...\r\r
 814 Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...\r\r
 815 Loading design module\r\r
 816 "../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...\r\r
 817 Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...\r\r
 818 Loading design module "../implementation/leds_8bit_wrapper.ngc"...\r\r
 819 Loading design module "../implementation/leds_positions_wrapper.ngc"...\r\r
 820 Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...\r\r
 821 Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...\r\r
 822 Loading design module "../implementation/iic_eeprom_wrapper.ngc"...\r\r
 823 Loading design module "../implementation/sram_wrapper.ngc"...\r\r
 824 Loading design module "../implementation/pcie_bridge_wrapper.ngc"...\r\r
 825 Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...\r\r
 826 Loading design module "../implementation/ethernet_mac_wrapper.ngc"...\r\r
 827 Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...\r\r
 828 Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...\r\r
 829 Loading design module "../implementation/ppc440_0_fcb_v20_wrapper.ngc"...\r\r
 830 Loading design module\r\r
 831 "../implementation/ppc440_0_apu_fpu_virtex5_wrapper.ngc"...\r\r
 832 Loading design module "../implementation/clock_generator_0_wrapper.ngc"...\r\r
 833 Loading design module "../implementation/jtagppc_cntlr_inst_wrapper.ngc"...\r\r
 834 Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...\r\r
 835 Loading design module "../implementation/xps_intc_0_wrapper.ngc"...\r\r
 836 \r\r
 837 Partition Implementation Status\r\r
 838 -------------------------------\r\r
 839 \r\r
 840   No Partitions were found in this design.\r\r
 841 \r\r
 842 -------------------------------\r\r
 843 \r\r
 844 NGCBUILD Design Results Summary:\r\r
 845   Number of errors:     0\r\r
 846   Number of warnings:   0\r\r
 847 \r\r
 848 Writing NGC file "../implementation/system.ngc" ...\r\r
 849 Total REAL time to NGCBUILD completion:  12 sec\r\r
 850 Total CPU time to NGCBUILD completion:   11 sec\r\r
 851 \r\r
 852 Writing NGCBUILD log file "../implementation/system.blc"...\r\r
 853 \r\r
 854 NGCBUILD done.\r\r
 855 *********************************************\r
 856 Running Xilinx Implementation tools..\r
 857 *********************************************\r
 858 xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc\r
 859 Release 11.2 - Xflow L.46 (nt)\r\r
 860 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 861 xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise\r\r
 862 ../__xps/ise/system.ise system.ngc  \r\r
 863 PMSPEC -- Overriding Xilinx file\r\r
 864 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 865 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 866 .... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into\r\r
 867 working directory\r\r
 868 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
 869 ion \r\r
 870 \r\r
 871 Using Flow File:\r\r
 872 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
 873 ion/fpga.flw \r\r
 874 Using Option File(s): \r\r
 875  C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 876 tion/xflow.opt \r\r
 877 \r\r
 878 Creating Script File ... \r\r
 879 \r\r
 880 #----------------------------------------------#\r\r
 881 # Starting program ngdbuild\r\r
 882 # ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm\r\r
 883 system.bmm\r\r
 884 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 885 tion/system.ngc" -uc system.ucf system.ngd \r\r
 886 #----------------------------------------------#\r\r
 887 Release 11.2 - ngdbuild L.46 (nt)\r\r
 888 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 889 PMSPEC -- Overriding Xilinx file\r\r
 890 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 891 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 892 \r\r
 893 Command Line: ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt\r\r
 894 timestamp -bm system.bmm\r\r
 895 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
 896 ion/system.ngc -uc system.ucf system.ngd\r\r
 897 \r\r
 898 Reading NGO file\r\r
 899 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 900 tion/system.ngc" ...\r\r
 901 Gathering constraint information from source properties...\r\r
 902 Done.\r\r
 903 \r\r
 904 Applying constraints in "system.ucf" to the design...\r\r
 905 WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance\r\r
 906    'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_\r\r
 907    ADV.DCM_ADV_INST' of type DCM_ADV has been changed from 'VIRTEX4' to\r\r
 908    'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive. \r\r
 909    In order for functional simulation to be correct, the value of SIM_DEVICE\r\r
 910    should be changed in this same manner in the source netlist or constraint\r\r
 911    file.\r\r
 912 Resolving constraint associations...\r\r
 913 Checking Constraint Associations...\r\r
 914 WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_MC_RD_DATA_SEL" = FROM\r\r
 915    "TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i"\r\r
 916    * 4;> [system.ucf(264)]: This constraint will be ignored because the relative\r\r
 917    clock constraint named 'TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i' was not\r\r
 918    found.\r\r
 919 \r\r
 920 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 921    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 922    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 923    The following new TNM groups and period specifications were generated at the\r\r
 924    PLL_ADV output(s): \r\r
 925    CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ =\r\r
 926    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *\r\r
 927    1.25 PHASE 2 ns HIGH 50%>\r\r
 928 \r\r
 929 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 930    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 931    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 932    The following new TNM groups and period specifications were generated at the\r\r
 933    PLL_ADV output(s): \r\r
 934    CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ =\r\r
 935    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin *\r\r
 936    1.25 HIGH 50%>\r\r
 937 \r\r
 938 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 939    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 940    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 941    The following new TNM groups and period specifications were generated at the\r\r
 942    PLL_ADV output(s): \r\r
 943    CLKOUT2: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ =\r\r
 944    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *\r\r
 945    1.25 HIGH 50%>\r\r
 946 \r\r
 947 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 948    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 949    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 950    The following new TNM groups and period specifications were generated at the\r\r
 951    PLL_ADV output(s): \r\r
 952    CLKOUT3: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ =\r\r
 953    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin *\r\r
 954    2 HIGH 50%>\r\r
 955 \r\r
 956 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 957    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 958    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 959    The following new TNM groups and period specifications were generated at the\r\r
 960    PLL_ADV output(s): \r\r
 961    CLKOUT4: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ =\r\r
 962    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *\r\r
 963    0.625 HIGH 50%>\r\r
 964 \r\r
 965 Done...\r\r
 966 Checking Partitions ...\r\r
 967 \r\r
 968 Processing BMM file ...\r\r
 969 \r\r
 970 WARNING:NgdBuild:1212 - User specified non-default attribute value\r\r
 971    (8.0000000000000000) was detected for the CLKIN_PERIOD attribute on DCM\r\r
 972    "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".\r\r
 973     This does not match the PERIOD constraint value (5 ns.).  The uncertainty\r\r
 974    calculation will use the non-default attribute value.  This could result in\r\r
 975    incorrect uncertainty calculated for DCM output clocks.\r\r
 976 Checking expanded design ...\r\r
 977 WARNING:NgdBuild:443 - SFF primitive\r\r
 978    'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_\r\r
 979    ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I'\r\r
 980    has unconnected output pin\r\r
 981 WARNING:NgdBuild:443 - SFF primitive\r\r
 982    'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has\r\r
 983    unconnected output pin\r\r
 984 WARNING:NgdBuild:443 - SFF primitive\r\r
 985    'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].\r\r
 986    ALIGN_PIPE' has unconnected output pin\r\r
 987 WARNING:NgdBuild:443 - SFF primitive\r\r
 988    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
 989    ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'\r\r
 990    has unconnected output pin\r\r
 991 WARNING:NgdBuild:443 - SFF primitive\r\r
 992    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
 993    ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'\r\r
 994    has unconnected output pin\r\r
 995 WARNING:NgdBuild:443 - SFF primitive\r\r
 996    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
 997    ENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FD\r\r
 998    RE_I' has unconnected output pin\r\r
 999 WARNING:NgdBuild:443 - SFF primitive\r\r
1000    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1001    ENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDR\r\r
1002    E_I' has unconnected output pin\r\r
1003 WARNING:NgdBuild:443 - SFF primitive\r\r
1004    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1005    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3\r\r
1006    ' has unconnected output pin\r\r
1007 WARNING:NgdBuild:443 - SFF primitive\r\r
1008    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1009    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3\r\r
1010    ' has unconnected output pin\r\r
1011 WARNING:NgdBuild:443 - SFF primitive\r\r
1012    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1013    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3\r\r
1014    ' has unconnected output pin\r\r
1015 WARNING:NgdBuild:443 - SFF primitive\r\r
1016    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1017    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3\r\r
1018    ' has unconnected output pin\r\r
1019 WARNING:NgdBuild:443 - SFF primitive\r\r
1020    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1021    ENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG'\r\r
1022    has unconnected output pin\r\r
1023 WARNING:NgdBuild:443 - SFF primitive\r\r
1024    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1025    ENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG\r\r
1026    ' has unconnected output pin\r\r
1027 WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
1028    "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad\r\r
1029    v_i" of type "PLL_ADV".  This attribute will be ignored.\r\r
1030 WARNING:NgdBuild:443 - SFF primitive\r\r
1031    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1032    URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
1033    unconnected output pin\r\r
1034 WARNING:NgdBuild:443 - SFF primitive\r\r
1035    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1036    URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
1037    unconnected output pin\r\r
1038 WARNING:NgdBuild:443 - SFF primitive\r\r
1039    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1040    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1041    _4to7[7].I_FDRSE_BE4to7' has unconnected output pin\r\r
1042 WARNING:NgdBuild:443 - SFF primitive\r\r
1043    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1044    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1045    _4to7[6].I_FDRSE_BE4to7' has unconnected output pin\r\r
1046 WARNING:NgdBuild:443 - SFF primitive\r\r
1047    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1048    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1049    _4to7[5].I_FDRSE_BE4to7' has unconnected output pin\r\r
1050 WARNING:NgdBuild:443 - SFF primitive\r\r
1051    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1052    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1053    _4to7[4].I_FDRSE_BE4to7' has unconnected output pin\r\r
1054 WARNING:NgdBuild:443 - SFF primitive\r\r
1055    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1056    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B\r\r
1057    E0to3' has unconnected output pin\r\r
1058 WARNING:NgdBuild:443 - SFF primitive\r\r
1059    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1060    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B\r\r
1061    E0to3' has unconnected output pin\r\r
1062 WARNING:NgdBuild:443 - SFF primitive\r\r
1063    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1064    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B\r\r
1065    E0to3' has unconnected output pin\r\r
1066 WARNING:NgdBuild:443 - SFF primitive\r\r
1067    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1068    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B\r\r
1069    E0to3' has unconnected output pin\r\r
1070 WARNING:NgdBuild:443 - SFF primitive\r\r
1071    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
1072    _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin\r\r
1073 WARNING:NgdBuild:443 - SFF primitive\r\r
1074    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
1075    _H_ADDR_REG[7].I_ADDR_S_H_REG' has unconnected output pin\r\r
1076 WARNING:NgdBuild:443 - SFF primitive\r\r
1077    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1078    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected\r\r
1079    output pin\r\r
1080 WARNING:NgdBuild:443 - SFF primitive\r\r
1081    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1082    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected\r\r
1083    output pin\r\r
1084 WARNING:NgdBuild:443 - SFF primitive\r\r
1085    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1086    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected\r\r
1087    output pin\r\r
1088 WARNING:NgdBuild:443 - SFF primitive\r\r
1089    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1090    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected\r\r
1091    output pin\r\r
1092 WARNING:NgdBuild:443 - SFF primitive\r\r
1093    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1094    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected\r\r
1095    output pin\r\r
1096 WARNING:NgdBuild:443 - SFF primitive\r\r
1097    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1098    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected\r\r
1099    output pin\r\r
1100 WARNING:NgdBuild:443 - SFF primitive\r\r
1101    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1102    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected\r\r
1103    output pin\r\r
1104 WARNING:NgdBuild:443 - SFF primitive\r\r
1105    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1106    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected\r\r
1107    output pin\r\r
1108 WARNING:NgdBuild:443 - SFF primitive\r\r
1109    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1110    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected\r\r
1111    output pin\r\r
1112 WARNING:NgdBuild:443 - SFF primitive\r\r
1113    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1114    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected\r\r
1115    output pin\r\r
1116 WARNING:NgdBuild:443 - SFF primitive\r\r
1117    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1118    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected\r\r
1119    output pin\r\r
1120 WARNING:NgdBuild:443 - SFF primitive\r\r
1121    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1122    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected\r\r
1123    output pin\r\r
1124 WARNING:NgdBuild:443 - SFF primitive\r\r
1125    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1126    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected\r\r
1127    output pin\r\r
1128 WARNING:NgdBuild:443 - SFF primitive\r\r
1129    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1130    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected\r\r
1131    output pin\r\r
1132 WARNING:NgdBuild:443 - SFF primitive\r\r
1133    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1134    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected\r\r
1135    output pin\r\r
1136 WARNING:NgdBuild:443 - SFF primitive\r\r
1137    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1138    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected\r\r
1139    output pin\r\r
1140 WARNING:NgdBuild:443 - SFF primitive\r\r
1141    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1142    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected\r\r
1143    output pin\r\r
1144 WARNING:NgdBuild:443 - SFF primitive\r\r
1145    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1146    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected\r\r
1147    output pin\r\r
1148 WARNING:NgdBuild:443 - SFF primitive\r\r
1149    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1150    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected\r\r
1151    output pin\r\r
1152 WARNING:NgdBuild:443 - SFF primitive\r\r
1153    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1154    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected\r\r
1155    output pin\r\r
1156 WARNING:NgdBuild:443 - SFF primitive\r\r
1157    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1158    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected\r\r
1159    output pin\r\r
1160 WARNING:NgdBuild:443 - SFF primitive\r\r
1161    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1162    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected\r\r
1163    output pin\r\r
1164 WARNING:NgdBuild:443 - SFF primitive\r\r
1165    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1166    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG' has unconnected\r\r
1167    output pin\r\r
1168 WARNING:NgdBuild:443 - SFF primitive\r\r
1169    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1170    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected\r\r
1171    output pin\r\r
1172 WARNING:NgdBuild:443 - SFF primitive\r\r
1173    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1174    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected\r\r
1175    output pin\r\r
1176 WARNING:NgdBuild:443 - SFF primitive\r\r
1177    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1178    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected\r\r
1179    output pin\r\r
1180 WARNING:NgdBuild:443 - SFF primitive\r\r
1181    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1182    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG' has unconnected\r\r
1183    output pin\r\r
1184 WARNING:NgdBuild:443 - SFF primitive\r\r
1185    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1186    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected\r\r
1187    output pin\r\r
1188 WARNING:NgdBuild:443 - SFF primitive\r\r
1189    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1190    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG' has unconnected\r\r
1191    output pin\r\r
1192 WARNING:NgdBuild:443 - SFF primitive\r\r
1193    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1194    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected\r\r
1195    output pin\r\r
1196 WARNING:NgdBuild:443 - SFF primitive\r\r
1197    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1198    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected\r\r
1199    output pin\r\r
1200 WARNING:NgdBuild:443 - SFF primitive\r\r
1201    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1202    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has\r\r
1203    unconnected output pin\r\r
1204 WARNING:NgdBuild:443 - SFF primitive\r\r
1205    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1206    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has\r\r
1207    unconnected output pin\r\r
1208 WARNING:NgdBuild:443 - SFF primitive\r\r
1209    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1210    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected\r\r
1211    output pin\r\r
1212 WARNING:NgdBuild:443 - SFF primitive\r\r
1213    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1214    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has\r\r
1215    unconnected output pin\r\r
1216 WARNING:NgdBuild:443 - SFF primitive\r\r
1217    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1218    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has\r\r
1219    unconnected output pin\r\r
1220 WARNING:NgdBuild:443 - SFF primitive\r\r
1221    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1222    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected\r\r
1223    output pin\r\r
1224 WARNING:NgdBuild:443 - SFF primitive\r\r
1225    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1226    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG' has\r\r
1227    unconnected output pin\r\r
1228 WARNING:NgdBuild:443 - SFF primitive\r\r
1229    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1230    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has\r\r
1231    unconnected output pin\r\r
1232 WARNING:NgdBuild:443 - SFF primitive\r\r
1233    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1234    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected\r\r
1235    output pin\r\r
1236 WARNING:NgdBuild:443 - SFF primitive\r\r
1237    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1238    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has\r\r
1239    unconnected output pin\r\r
1240 WARNING:NgdBuild:443 - SFF primitive\r\r
1241    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1242    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has\r\r
1243    unconnected output pin\r\r
1244 WARNING:NgdBuild:443 - SFF primitive\r\r
1245    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1246    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected\r\r
1247    output pin\r\r
1248 WARNING:NgdBuild:443 - SFF primitive\r\r
1249    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1250    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has\r\r
1251    unconnected output pin\r\r
1252 WARNING:NgdBuild:443 - SFF primitive\r\r
1253    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1254    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has\r\r
1255    unconnected output pin\r\r
1256 WARNING:NgdBuild:443 - SFF primitive\r\r
1257    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1258    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected\r\r
1259    output pin\r\r
1260 WARNING:NgdBuild:443 - SFF primitive\r\r
1261    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1262    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has\r\r
1263    unconnected output pin\r\r
1264 WARNING:NgdBuild:443 - SFF primitive\r\r
1265    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1266    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has\r\r
1267    unconnected output pin\r\r
1268 WARNING:NgdBuild:443 - SFF primitive\r\r
1269    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1270    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected\r\r
1271    output pin\r\r
1272 WARNING:NgdBuild:443 - SFF primitive\r\r
1273    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1274    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has\r\r
1275    unconnected output pin\r\r
1276 WARNING:NgdBuild:443 - SFF primitive\r\r
1277    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1278    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has\r\r
1279    unconnected output pin\r\r
1280 WARNING:NgdBuild:443 - SFF primitive\r\r
1281    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1282    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected\r\r
1283    output pin\r\r
1284 WARNING:NgdBuild:443 - SFF primitive\r\r
1285    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1286    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has\r\r
1287    unconnected output pin\r\r
1288 WARNING:NgdBuild:443 - SFF primitive\r\r
1289    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1290    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has\r\r
1291    unconnected output pin\r\r
1292 WARNING:NgdBuild:443 - SFF primitive\r\r
1293    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1294    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected\r\r
1295    output pin\r\r
1296 WARNING:NgdBuild:443 - SFF primitive\r\r
1297    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1298    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has\r\r
1299    unconnected output pin\r\r
1300 WARNING:NgdBuild:443 - SFF primitive\r\r
1301    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1302    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has\r\r
1303    unconnected output pin\r\r
1304 WARNING:NgdBuild:443 - SFF primitive\r\r
1305    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1306    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected\r\r
1307    output pin\r\r
1308 WARNING:NgdBuild:443 - SFF primitive\r\r
1309    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1310    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has\r\r
1311    unconnected output pin\r\r
1312 WARNING:NgdBuild:443 - SFF primitive\r\r
1313    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1314    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has\r\r
1315    unconnected output pin\r\r
1316 WARNING:NgdBuild:443 - SFF primitive\r\r
1317    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1318    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected\r\r
1319    output pin\r\r
1320 WARNING:NgdBuild:443 - SFF primitive\r\r
1321    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1322    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has\r\r
1323    unconnected output pin\r\r
1324 WARNING:NgdBuild:443 - SFF primitive\r\r
1325    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1326    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has\r\r
1327    unconnected output pin\r\r
1328 WARNING:NgdBuild:443 - SFF primitive\r\r
1329    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1330    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected\r\r
1331    output pin\r\r
1332 WARNING:NgdBuild:443 - SFF primitive\r\r
1333    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1334    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has\r\r
1335    unconnected output pin\r\r
1336 WARNING:NgdBuild:443 - SFF primitive\r\r
1337    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1338    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has\r\r
1339    unconnected output pin\r\r
1340 WARNING:NgdBuild:443 - SFF primitive\r\r
1341    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1342    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected\r\r
1343    output pin\r\r
1344 WARNING:NgdBuild:443 - SFF primitive\r\r
1345    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1346    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG' has\r\r
1347    unconnected output pin\r\r
1348 WARNING:NgdBuild:443 - SFF primitive\r\r
1349    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1350    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has\r\r
1351    unconnected output pin\r\r
1352 WARNING:NgdBuild:443 - SFF primitive\r\r
1353    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1354    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG' has unconnected\r\r
1355    output pin\r\r
1356 WARNING:NgdBuild:443 - SFF primitive\r\r
1357    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1358    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has\r\r
1359    unconnected output pin\r\r
1360 WARNING:NgdBuild:443 - SFF primitive\r\r
1361    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1362    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has\r\r
1363    unconnected output pin\r\r
1364 WARNING:NgdBuild:443 - SFF primitive\r\r
1365    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1366    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected\r\r
1367    output pin\r\r
1368 WARNING:NgdBuild:443 - SFF primitive\r\r
1369    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1370    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has\r\r
1371    unconnected output pin\r\r
1372 WARNING:NgdBuild:443 - SFF primitive\r\r
1373    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1374    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has\r\r
1375    unconnected output pin\r\r
1376 WARNING:NgdBuild:443 - SFF primitive\r\r
1377    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1378    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected\r\r
1379    output pin\r\r
1380 WARNING:NgdBuild:443 - SFF primitive\r\r
1381    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1382    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has\r\r
1383    unconnected output pin\r\r
1384 WARNING:NgdBuild:443 - SFF primitive\r\r
1385    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1386    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has\r\r
1387    unconnected output pin\r\r
1388 WARNING:NgdBuild:443 - SFF primitive\r\r
1389    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1390    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected\r\r
1391    output pin\r\r
1392 WARNING:NgdBuild:443 - SFF primitive\r\r
1393    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1394    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has\r\r
1395    unconnected output pin\r\r
1396 WARNING:NgdBuild:443 - SFF primitive\r\r
1397    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1398    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has\r\r
1399    unconnected output pin\r\r
1400 WARNING:NgdBuild:443 - SFF primitive\r\r
1401    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1402    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected\r\r
1403    output pin\r\r
1404 WARNING:NgdBuild:443 - SFF primitive\r\r
1405    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1406    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has\r\r
1407    unconnected output pin\r\r
1408 WARNING:NgdBuild:443 - SFF primitive\r\r
1409    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1410    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has\r\r
1411    unconnected output pin\r\r
1412 WARNING:NgdBuild:443 - SFF primitive\r\r
1413    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1414    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected\r\r
1415    output pin\r\r
1416 WARNING:NgdBuild:443 - SFF primitive\r\r
1417    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1418    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has\r\r
1419    unconnected output pin\r\r
1420 WARNING:NgdBuild:443 - SFF primitive\r\r
1421    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1422    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has\r\r
1423    unconnected output pin\r\r
1424 WARNING:NgdBuild:443 - SFF primitive\r\r
1425    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1426    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected\r\r
1427    output pin\r\r
1428 WARNING:NgdBuild:443 - SFF primitive\r\r
1429    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1430    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG' has\r\r
1431    unconnected output pin\r\r
1432 WARNING:NgdBuild:443 - SFF primitive\r\r
1433    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1434    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has\r\r
1435    unconnected output pin\r\r
1436 WARNING:NgdBuild:443 - SFF primitive\r\r
1437    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1438    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected\r\r
1439    output pin\r\r
1440 WARNING:NgdBuild:443 - SFF primitive\r\r
1441    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1442    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has\r\r
1443    unconnected output pin\r\r
1444 WARNING:NgdBuild:443 - SFF primitive\r\r
1445    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1446    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has\r\r
1447    unconnected output pin\r\r
1448 WARNING:NgdBuild:443 - SFF primitive\r\r
1449    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1450    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected\r\r
1451    output pin\r\r
1452 WARNING:NgdBuild:443 - SFF primitive\r\r
1453    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1454    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has\r\r
1455    unconnected output pin\r\r
1456 WARNING:NgdBuild:443 - SFF primitive\r\r
1457    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1458    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has\r\r
1459    unconnected output pin\r\r
1460 WARNING:NgdBuild:443 - SFF primitive\r\r
1461    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1462    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected\r\r
1463    output pin\r\r
1464 WARNING:NgdBuild:443 - SFF primitive\r\r
1465    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1466    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected\r\r
1467    output pin\r\r
1468 WARNING:NgdBuild:443 - SFF primitive\r\r
1469    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1470    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected\r\r
1471    output pin\r\r
1472 WARNING:NgdBuild:443 - SFF primitive\r\r
1473    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1474    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected\r\r
1475    output pin\r\r
1476 WARNING:NgdBuild:443 - SFF primitive\r\r
1477    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1478    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected\r\r
1479    output pin\r\r
1480 WARNING:NgdBuild:443 - SFF primitive\r\r
1481    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1482    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected\r\r
1483    output pin\r\r
1484 WARNING:NgdBuild:443 - SFF primitive\r\r
1485    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1486    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected\r\r
1487    output pin\r\r
1488 WARNING:NgdBuild:443 - SFF primitive\r\r
1489    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1490    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected\r\r
1491    output pin\r\r
1492 WARNING:NgdBuild:443 - SFF primitive\r\r
1493    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1494    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected\r\r
1495    output pin\r\r
1496 WARNING:NgdBuild:443 - SFF primitive\r\r
1497    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1498    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected\r\r
1499    output pin\r\r
1500 WARNING:NgdBuild:443 - SFF primitive\r\r
1501    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1502    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected\r\r
1503    output pin\r\r
1504 WARNING:NgdBuild:443 - SFF primitive\r\r
1505    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1506    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected\r\r
1507    output pin\r\r
1508 WARNING:NgdBuild:443 - SFF primitive\r\r
1509    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1510    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG' has unconnected\r\r
1511    output pin\r\r
1512 WARNING:NgdBuild:443 - SFF primitive\r\r
1513    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1514    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG' has\r\r
1515    unconnected output pin\r\r
1516 WARNING:NgdBuild:443 - SFF primitive\r\r
1517    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1518    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG' has\r\r
1519    unconnected output pin\r\r
1520 WARNING:NgdBuild:443 - SFF primitive\r\r
1521    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1522    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected\r\r
1523    output pin\r\r
1524 WARNING:NgdBuild:443 - SFF primitive\r\r
1525    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1526    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG' has\r\r
1527    unconnected output pin\r\r
1528 WARNING:NgdBuild:443 - SFF primitive\r\r
1529    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1530    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has\r\r
1531    unconnected output pin\r\r
1532 WARNING:NgdBuild:443 - SFF primitive\r\r
1533    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1534    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG' has unconnected\r\r
1535    output pin\r\r
1536 WARNING:NgdBuild:443 - SFF primitive\r\r
1537    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1538    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG' has\r\r
1539    unconnected output pin\r\r
1540 WARNING:NgdBuild:443 - SFF primitive\r\r
1541    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1542    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has\r\r
1543    unconnected output pin\r\r
1544 WARNING:NgdBuild:443 - SFF primitive\r\r
1545    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1546    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected\r\r
1547    output pin\r\r
1548 WARNING:NgdBuild:443 - SFF primitive\r\r
1549    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1550    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has\r\r
1551    unconnected output pin\r\r
1552 WARNING:NgdBuild:443 - SFF primitive\r\r
1553    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1554    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG' has\r\r
1555    unconnected output pin\r\r
1556 WARNING:NgdBuild:443 - SFF primitive\r\r
1557    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1558    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected\r\r
1559    output pin\r\r
1560 WARNING:NgdBuild:443 - SFF primitive\r\r
1561    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1562    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG' has\r\r
1563    unconnected output pin\r\r
1564 WARNING:NgdBuild:443 - SFF primitive\r\r
1565    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1566    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has\r\r
1567    unconnected output pin\r\r
1568 WARNING:NgdBuild:443 - SFF primitive\r\r
1569    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1570    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG' has unconnected\r\r
1571    output pin\r\r
1572 WARNING:NgdBuild:443 - SFF primitive\r\r
1573    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1574    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has\r\r
1575    unconnected output pin\r\r
1576 WARNING:NgdBuild:443 - SFF primitive\r\r
1577    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1578    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has\r\r
1579    unconnected output pin\r\r
1580 WARNING:NgdBuild:443 - SFF primitive\r\r
1581    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1582    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected\r\r
1583    output pin\r\r
1584 WARNING:NgdBuild:443 - SFF primitive\r\r
1585    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1586    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has\r\r
1587    unconnected output pin\r\r
1588 WARNING:NgdBuild:443 - SFF primitive\r\r
1589    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1590    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has\r\r
1591    unconnected output pin\r\r
1592 WARNING:NgdBuild:443 - SFF primitive\r\r
1593    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1594    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected\r\r
1595    output pin\r\r
1596 WARNING:NgdBuild:443 - SFF primitive\r\r
1597    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1598    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has\r\r
1599    unconnected output pin\r\r
1600 WARNING:NgdBuild:443 - SFF primitive\r\r
1601    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1602    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has\r\r
1603    unconnected output pin\r\r
1604 WARNING:NgdBuild:443 - SFF primitive\r\r
1605    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1606    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected\r\r
1607    output pin\r\r
1608 WARNING:NgdBuild:443 - SFF primitive\r\r
1609    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1610    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has\r\r
1611    unconnected output pin\r\r
1612 WARNING:NgdBuild:443 - SFF primitive\r\r
1613    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1614    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has\r\r
1615    unconnected output pin\r\r
1616 WARNING:NgdBuild:443 - SFF primitive\r\r
1617    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1618    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected\r\r
1619    output pin\r\r
1620 WARNING:NgdBuild:443 - SFF primitive\r\r
1621    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1622    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG' has\r\r
1623    unconnected output pin\r\r
1624 WARNING:NgdBuild:443 - SFF primitive\r\r
1625    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1626    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG' has\r\r
1627    unconnected output pin\r\r
1628 WARNING:NgdBuild:443 - SFF primitive\r\r
1629    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1630    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG' has unconnected\r\r
1631    output pin\r\r
1632 WARNING:NgdBuild:443 - SFF primitive\r\r
1633    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1634    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG' has\r\r
1635    unconnected output pin\r\r
1636 WARNING:NgdBuild:443 - SFF primitive\r\r
1637    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1638    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG' has\r\r
1639    unconnected output pin\r\r
1640 WARNING:NgdBuild:443 - SFF primitive\r\r
1641    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1642    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG' has unconnected\r\r
1643    output pin\r\r
1644 WARNING:NgdBuild:443 - SFF primitive\r\r
1645    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1646    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG' has\r\r
1647    unconnected output pin\r\r
1648 WARNING:NgdBuild:443 - SFF primitive\r\r
1649    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1650    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG' has\r\r
1651    unconnected output pin\r\r
1652 WARNING:NgdBuild:443 - SFF primitive\r\r
1653    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1654    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG' has unconnected\r\r
1655    output pin\r\r
1656 WARNING:NgdBuild:443 - SFF primitive\r\r
1657    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1658    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG' has unconnected\r\r
1659    output pin\r\r
1660 WARNING:NgdBuild:443 - SFF primitive\r\r
1661    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1662    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG' has unconnected\r\r
1663    output pin\r\r
1664 WARNING:NgdBuild:443 - SFF primitive\r\r
1665    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1666    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG' has unconnected\r\r
1667    output pin\r\r
1668 WARNING:NgdBuild:443 - SFF primitive\r\r
1669    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1670    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG' has unconnected\r\r
1671    output pin\r\r
1672 WARNING:NgdBuild:443 - SFF primitive\r\r
1673    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1674    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG' has unconnected\r\r
1675    output pin\r\r
1676 WARNING:NgdBuild:443 - SFF primitive\r\r
1677    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1678    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG' has\r\r
1679    unconnected output pin\r\r
1680 WARNING:NgdBuild:443 - SFF primitive\r\r
1681    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1682    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG' has\r\r
1683    unconnected output pin\r\r
1684 WARNING:NgdBuild:443 - SFF primitive\r\r
1685    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1686    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG' has unconnected\r\r
1687    output pin\r\r
1688 WARNING:NgdBuild:443 - SFF primitive\r\r
1689    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1690    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG' has\r\r
1691    unconnected output pin\r\r
1692 WARNING:NgdBuild:443 - SFF primitive\r\r
1693    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1694    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG' has\r\r
1695    unconnected output pin\r\r
1696 WARNING:NgdBuild:443 - SFF primitive\r\r
1697    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1698    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG' has unconnected\r\r
1699    output pin\r\r
1700 WARNING:NgdBuild:443 - SFF primitive\r\r
1701    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1702    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG' has\r\r
1703    unconnected output pin\r\r
1704 WARNING:NgdBuild:443 - SFF primitive\r\r
1705    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1706    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG' has\r\r
1707    unconnected output pin\r\r
1708 WARNING:NgdBuild:443 - SFF primitive\r\r
1709    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1710    E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG' has unconnected\r\r
1711    output pin\r\r
1712 WARNING:NgdBuild:443 - SFF primitive\r\r
1713    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1714    E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG' has\r\r
1715    unconnected output pin\r\r
1716 WARNING:NgdBuild:443 - SFF primitive\r\r
1717    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1718    E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG' has\r\r
1719    unconnected output pin\r\r
1720 WARNING:NgdBuild:443 - SFF primitive\r\r
1721    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1722    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG' has\r\r
1723    unconnected output pin\r\r
1724 WARNING:NgdBuild:443 - SFF primitive\r\r
1725    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1726    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has\r\r
1727    unconnected output pin\r\r
1728 WARNING:NgdBuild:443 - SFF primitive\r\r
1729    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1730    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG' has\r\r
1731    unconnected output pin\r\r
1732 WARNING:NgdBuild:443 - SFF primitive\r\r
1733    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1734    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG' has\r\r
1735    unconnected output pin\r\r
1736 WARNING:NgdBuild:443 - SFF primitive\r\r
1737    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1738    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG' has\r\r
1739    unconnected output pin\r\r
1740 WARNING:NgdBuild:443 - SFF primitive\r\r
1741    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1742    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG' has\r\r
1743    unconnected output pin\r\r
1744 WARNING:NgdBuild:443 - SFF primitive\r\r
1745    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1746    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG' has\r\r
1747    unconnected output pin\r\r
1748 WARNING:NgdBuild:443 - SFF primitive\r\r
1749    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1750    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG' has\r\r
1751    unconnected output pin\r\r
1752 WARNING:NgdBuild:443 - SFF primitive\r\r
1753    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1754    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG' has\r\r
1755    unconnected output pin\r\r
1756 WARNING:NgdBuild:443 - SFF primitive\r\r
1757    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1758    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG' has\r\r
1759    unconnected output pin\r\r
1760 WARNING:NgdBuild:443 - SFF primitive\r\r
1761    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1762    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG' has\r\r
1763    unconnected output pin\r\r
1764 WARNING:NgdBuild:443 - SFF primitive\r\r
1765    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1766    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG' has\r\r
1767    unconnected output pin\r\r
1768 WARNING:NgdBuild:443 - SFF primitive\r\r
1769    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1770    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG' has\r\r
1771    unconnected output pin\r\r
1772 WARNING:NgdBuild:443 - SFF primitive\r\r
1773    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1774    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG' has\r\r
1775    unconnected output pin\r\r
1776 WARNING:NgdBuild:443 - SFF primitive\r\r
1777    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1778    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG' has\r\r
1779    unconnected output pin\r\r
1780 WARNING:NgdBuild:443 - SFF primitive\r\r
1781    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1782    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG' has\r\r
1783    unconnected output pin\r\r
1784 WARNING:NgdBuild:443 - SFF primitive\r\r
1785    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1786    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG' has\r\r
1787    unconnected output pin\r\r
1788 WARNING:NgdBuild:443 - SFF primitive\r\r
1789    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1790    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG' has\r\r
1791    unconnected output pin\r\r
1792 WARNING:NgdBuild:443 - SFF primitive\r\r
1793    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1794    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG' has\r\r
1795    unconnected output pin\r\r
1796 WARNING:NgdBuild:443 - SFF primitive\r\r
1797    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1798    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG' has\r\r
1799    unconnected output pin\r\r
1800 WARNING:NgdBuild:443 - SFF primitive\r\r
1801    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1802    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG' has\r\r
1803    unconnected output pin\r\r
1804 WARNING:NgdBuild:443 - SFF primitive\r\r
1805    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1806    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG' has\r\r
1807    unconnected output pin\r\r
1808 WARNING:NgdBuild:443 - SFF primitive\r\r
1809    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1810    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG' has\r\r
1811    unconnected output pin\r\r
1812 WARNING:NgdBuild:443 - SFF primitive\r\r
1813    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1814    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG' has\r\r
1815    unconnected output pin\r\r
1816 WARNING:NgdBuild:443 - SFF primitive\r\r
1817    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1818    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG' has\r\r
1819    unconnected output pin\r\r
1820 WARNING:NgdBuild:443 - SFF primitive\r\r
1821    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1822    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG' has\r\r
1823    unconnected output pin\r\r
1824 WARNING:NgdBuild:443 - SFF primitive\r\r
1825    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1826    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG' has\r\r
1827    unconnected output pin\r\r
1828 WARNING:NgdBuild:443 - SFF primitive\r\r
1829    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1830    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG' has\r\r
1831    unconnected output pin\r\r
1832 WARNING:NgdBuild:443 - SFF primitive\r\r
1833    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1834    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG' has\r\r
1835    unconnected output pin\r\r
1836 WARNING:NgdBuild:443 - SFF primitive\r\r
1837    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1838    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG' has\r\r
1839    unconnected output pin\r\r
1840 WARNING:NgdBuild:443 - SFF primitive\r\r
1841    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1842    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG' has\r\r
1843    unconnected output pin\r\r
1844 WARNING:NgdBuild:443 - SFF primitive\r\r
1845    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1846    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG' has\r\r
1847    unconnected output pin\r\r
1848 WARNING:NgdBuild:443 - SFF primitive\r\r
1849    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1850    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG' has\r\r
1851    unconnected output pin\r\r
1852 WARNING:NgdBuild:443 - SFF primitive\r\r
1853    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1854    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG' has\r\r
1855    unconnected output pin\r\r
1856 WARNING:NgdBuild:443 - SFF primitive\r\r
1857    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1858    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG' has\r\r
1859    unconnected output pin\r\r
1860 WARNING:NgdBuild:443 - SFF primitive\r\r
1861    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1862    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG' has\r\r
1863    unconnected output pin\r\r
1864 WARNING:NgdBuild:443 - SFF primitive\r\r
1865    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1866    E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG' has unconnected output pin\r\r
1867 WARNING:NgdBuild:443 - SFF primitive\r\r
1868    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1869    E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin\r\r
1870 WARNING:NgdBuild:443 - SFF primitive\r\r
1871    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1872    E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG' has unconnected\r\r
1873    output pin\r\r
1874 WARNING:NgdBuild:443 - SFF primitive\r\r
1875    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1876    E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG' has\r\r
1877    unconnected output pin\r\r
1878 WARNING:NgdBuild:443 - SFF primitive\r\r
1879    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1880    E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG' has\r\r
1881    unconnected output pin\r\r
1882 WARNING:NgdBuild:443 - SFF primitive\r\r
1883    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1884    E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG' has unconnected\r\r
1885    output pin\r\r
1886 WARNING:NgdBuild:443 - SFF primitive\r\r
1887    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1888    E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG' has\r\r
1889    unconnected output pin\r\r
1890 WARNING:NgdBuild:443 - SFF primitive\r\r
1891    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1892    E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG' has\r\r
1893    unconnected output pin\r\r
1894 WARNING:NgdBuild:443 - SFF primitive\r\r
1895    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
1896    SIZE2_REG0' has unconnected output pin\r\r
1897 WARNING:NgdBuild:443 - SFF primitive\r\r
1898    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
1899    SIZE2_REG1' has unconnected output pin\r\r
1900 WARNING:NgdBuild:443 - SFF primitive\r\r
1901    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
1902    SIZE2_REG2' has unconnected output pin\r\r
1903 WARNING:NgdBuild:443 - SFF primitive\r\r
1904    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG' has\r\r
1905    unconnected output pin\r\r
1906 WARNING:NgdBuild:443 - SFF primitive\r\r
1907    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected\r\r
1908    output pin\r\r
1909 WARNING:NgdBuild:440 - FF primitive\r\r
1910    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'\r\r
1911    has unconnected output pin\r\r
1912 WARNING:NgdBuild:440 - FF primitive\r\r
1913    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'\r\r
1914    has unconnected output pin\r\r
1915 WARNING:NgdBuild:440 - FF primitive\r\r
1916    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'\r\r
1917    has unconnected output pin\r\r
1918 WARNING:NgdBuild:440 - FF primitive\r\r
1919    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'\r\r
1920    has unconnected output pin\r\r
1921 WARNING:NgdBuild:440 - FF primitive\r\r
1922    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'\r\r
1923    has unconnected output pin\r\r
1924 WARNING:NgdBuild:440 - FF primitive\r\r
1925    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'\r\r
1926    has unconnected output pin\r\r
1927 WARNING:NgdBuild:440 - FF primitive\r\r
1928    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'\r\r
1929    has unconnected output pin\r\r
1930 WARNING:NgdBuild:440 - FF primitive\r\r
1931    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'\r\r
1932    has unconnected output pin\r\r
1933 WARNING:NgdBuild:440 - FF primitive\r\r
1934    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'\r\r
1935    has unconnected output pin\r\r
1936 WARNING:NgdBuild:440 - FF primitive\r\r
1937    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'\r\r
1938    has unconnected output pin\r\r
1939 WARNING:NgdBuild:440 - FF primitive\r\r
1940    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'\r\r
1941    has unconnected output pin\r\r
1942 WARNING:NgdBuild:440 - FF primitive\r\r
1943    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'\r\r
1944    has unconnected output pin\r\r
1945 WARNING:NgdBuild:440 - FF primitive\r\r
1946    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'\r\r
1947    has unconnected output pin\r\r
1948 WARNING:NgdBuild:440 - FF primitive\r\r
1949    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'\r\r
1950    has unconnected output pin\r\r
1951 WARNING:NgdBuild:440 - FF primitive\r\r
1952    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'\r\r
1953    has unconnected output pin\r\r
1954 WARNING:NgdBuild:440 - FF primitive\r\r
1955    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'\r\r
1956    has unconnected output pin\r\r
1957 WARNING:NgdBuild:440 - FF primitive\r\r
1958    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1959    /gen_rden[1].u_calib_rden_r' has unconnected output pin\r\r
1960 WARNING:NgdBuild:440 - FF primitive\r\r
1961    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1962    /gen_rden[2].u_calib_rden_r' has unconnected output pin\r\r
1963 WARNING:NgdBuild:440 - FF primitive\r\r
1964    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1965    /gen_rden[3].u_calib_rden_r' has unconnected output pin\r\r
1966 WARNING:NgdBuild:440 - FF primitive\r\r
1967    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1968    /gen_rden[4].u_calib_rden_r' has unconnected output pin\r\r
1969 WARNING:NgdBuild:440 - FF primitive\r\r
1970    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1971    /gen_rden[5].u_calib_rden_r' has unconnected output pin\r\r
1972 WARNING:NgdBuild:440 - FF primitive\r\r
1973    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1974    /gen_rden[6].u_calib_rden_r' has unconnected output pin\r\r
1975 WARNING:NgdBuild:440 - FF primitive\r\r
1976    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1977    /gen_rden[7].u_calib_rden_r' has unconnected output pin\r\r
1978 WARNING:NgdBuild:440 - FF primitive\r\r
1979    'ppc440_0_apu_fpu_virtex5/ppc440_0_apu_fpu_virtex5/gen_apu_fpu_dp_lo.netlist/\r\r
1980    fpu_is_full.sqrt_sqrt_flt_pt_op_sqrt_op.spd.op_round_logic.rnd2_carrys_q_del.\r\r
1981    no_rlocs.fast_del.carry_fd' has unconnected output pin\r\r
1982 WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
1983    "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"\r\r
1984    of type "PLL_ADV".  This attribute will be ignored.\r\r
1985 WARNING:NgdBuild:452 - logical net 'N194' has no driver\r\r
1986 WARNING:NgdBuild:452 - logical net 'N195' has no driver\r\r
1987 WARNING:NgdBuild:452 - logical net 'N196' has no driver\r\r
1988 WARNING:NgdBuild:452 - logical net 'N197' has no driver\r\r
1989 WARNING:NgdBuild:452 - logical net 'N198' has no driver\r\r
1990 WARNING:NgdBuild:452 - logical net 'N199' has no driver\r\r
1991 WARNING:NgdBuild:452 - logical net 'N200' has no driver\r\r
1992 WARNING:NgdBuild:452 - logical net 'N201' has no driver\r\r
1993 WARNING:NgdBuild:452 - logical net 'N202' has no driver\r\r
1994 WARNING:NgdBuild:452 - logical net 'N203' has no driver\r\r
1995 WARNING:NgdBuild:452 - logical net 'N204' has no driver\r\r
1996 WARNING:NgdBuild:452 - logical net 'N205' has no driver\r\r
1997 WARNING:NgdBuild:452 - logical net 'N206' has no driver\r\r
1998 WARNING:NgdBuild:452 - logical net 'N207' has no driver\r\r
1999 WARNING:NgdBuild:452 - logical net 'N208' has no driver\r\r
2000 WARNING:NgdBuild:452 - logical net 'N209' has no driver\r\r
2001 WARNING:NgdBuild:452 - logical net 'N210' has no driver\r\r
2002 WARNING:NgdBuild:452 - logical net 'N211' has no driver\r\r
2003 WARNING:NgdBuild:452 - logical net 'N212' has no driver\r\r
2004 WARNING:NgdBuild:452 - logical net 'N213' has no driver\r\r
2005 WARNING:NgdBuild:452 - logical net 'N214' has no driver\r\r
2006 WARNING:NgdBuild:452 - logical net 'N215' has no driver\r\r
2007 WARNING:NgdBuild:452 - logical net 'N216' has no driver\r\r
2008 WARNING:NgdBuild:452 - logical net 'N217' has no driver\r\r
2009 WARNING:NgdBuild:452 - logical net 'N218' has no driver\r\r
2010 WARNING:NgdBuild:452 - logical net 'N219' has no driver\r\r
2011 WARNING:NgdBuild:452 - logical net 'N220' has no driver\r\r
2012 WARNING:NgdBuild:452 - logical net 'N221' has no driver\r\r
2013 WARNING:NgdBuild:452 - logical net 'N222' has no driver\r\r
2014 WARNING:NgdBuild:452 - logical net 'N223' has no driver\r\r
2015 WARNING:NgdBuild:452 - logical net 'N224' has no driver\r\r
2016 WARNING:NgdBuild:452 - logical net 'N225' has no driver\r\r
2017 WARNING:NgdBuild:452 - logical net 'N226' has no driver\r\r
2018 WARNING:NgdBuild:452 - logical net 'N227' has no driver\r\r
2019 WARNING:NgdBuild:452 - logical net 'N228' has no driver\r\r
2020 WARNING:NgdBuild:452 - logical net 'N229' has no driver\r\r
2021 WARNING:NgdBuild:452 - logical net 'N230' has no driver\r\r
2022 WARNING:NgdBuild:452 - logical net 'N231' has no driver\r\r
2023 WARNING:NgdBuild:452 - logical net 'N232' has no driver\r\r
2024 WARNING:NgdBuild:452 - logical net 'N233' has no driver\r\r
2025 WARNING:NgdBuild:452 - logical net 'N234' has no driver\r\r
2026 WARNING:NgdBuild:452 - logical net 'N235' has no driver\r\r
2027 WARNING:NgdBuild:452 - logical net 'N236' has no driver\r\r
2028 WARNING:NgdBuild:452 - logical net 'N237' has no driver\r\r
2029 WARNING:NgdBuild:452 - logical net 'N238' has no driver\r\r
2030 WARNING:NgdBuild:452 - logical net 'N239' has no driver\r\r
2031 WARNING:NgdBuild:452 - logical net 'N240' has no driver\r\r
2032 WARNING:NgdBuild:452 - logical net 'N241' has no driver\r\r
2033 WARNING:NgdBuild:452 - logical net 'N242' has no driver\r\r
2034 WARNING:NgdBuild:452 - logical net 'N243' has no driver\r\r
2035 WARNING:NgdBuild:452 - logical net 'N244' has no driver\r\r
2036 WARNING:NgdBuild:452 - logical net 'N245' has no driver\r\r
2037 WARNING:NgdBuild:452 - logical net 'N246' has no driver\r\r
2038 WARNING:NgdBuild:452 - logical net 'N247' has no driver\r\r
2039 WARNING:NgdBuild:452 - logical net 'N248' has no driver\r\r
2040 WARNING:NgdBuild:452 - logical net 'N249' has no driver\r\r
2041 WARNING:NgdBuild:452 - logical net 'N250' has no driver\r\r
2042 WARNING:NgdBuild:452 - logical net 'N251' has no driver\r\r
2043 WARNING:NgdBuild:452 - logical net 'N252' has no driver\r\r
2044 WARNING:NgdBuild:452 - logical net 'N253' has no driver\r\r
2045 WARNING:NgdBuild:452 - logical net 'N254' has no driver\r\r
2046 WARNING:NgdBuild:452 - logical net 'N255' has no driver\r\r
2047 WARNING:NgdBuild:452 - logical net 'N256' has no driver\r\r
2048 WARNING:NgdBuild:452 - logical net 'N257' has no driver\r\r
2049 WARNING:NgdBuild:452 - logical net 'N266' has no driver\r\r
2050 WARNING:NgdBuild:452 - logical net 'N267' has no driver\r\r
2051 WARNING:NgdBuild:452 - logical net 'N268' has no driver\r\r
2052 WARNING:NgdBuild:452 - logical net 'N269' has no driver\r\r
2053 WARNING:NgdBuild:452 - logical net 'N270' has no driver\r\r
2054 WARNING:NgdBuild:452 - logical net 'N271' has no driver\r\r
2055 WARNING:NgdBuild:452 - logical net 'N272' has no driver\r\r
2056 WARNING:NgdBuild:452 - logical net 'N273' has no driver\r\r
2057 WARNING:NgdBuild:452 - logical net 'N306' has no driver\r\r
2058 WARNING:NgdBuild:452 - logical net 'N307' has no driver\r\r
2059 WARNING:NgdBuild:452 - logical net 'N308' has no driver\r\r
2060 WARNING:NgdBuild:452 - logical net 'N309' has no driver\r\r
2061 WARNING:NgdBuild:452 - logical net 'N310' has no driver\r\r
2062 WARNING:NgdBuild:452 - logical net 'N311' has no driver\r\r
2063 WARNING:NgdBuild:452 - logical net 'N312' has no driver\r\r
2064 WARNING:NgdBuild:452 - logical net 'N313' has no driver\r\r
2065 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'\r\r
2066    has no driver\r\r
2067 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'\r\r
2068    has no driver\r\r
2069 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'\r\r
2070    has no driver\r\r
2071 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'\r\r
2072    has no driver\r\r
2073 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'\r\r
2074    has no driver\r\r
2075 \r\r
2076 Partition Implementation Status\r\r
2077 -------------------------------\r\r
2078 \r\r
2079   No Partitions were found in this design.\r\r
2080 \r\r
2081 -------------------------------\r\r
2082 \r\r
2083 NGDBUILD Design Results Summary:\r\r
2084   Number of errors:     0\r\r
2085   Number of warnings: 349\r\r
2086 \r\r
2087 Writing NGD file "system.ngd" ...\r\r
2088 Total REAL time to NGDBUILD completion: 2 min  20 sec\r\r
2089 Total CPU time to NGDBUILD completion:  1 min  50 sec\r\r
2090 \r\r
2091 Writing NGDBUILD log file "system.bld"...\r\r
2092 \r\r
2093 NGDBUILD done.\r\r
2094 \r\r
2095 \r\r
2096 \r\r
2097 #----------------------------------------------#\r\r
2098 # Starting program map\r\r
2099 # map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing\r\r
2100 system.ngd system.pcf \r\r
2101 #----------------------------------------------#\r\r
2102 Release 11.2 - Map L.46 (nt)\r\r
2103 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
2104 PMSPEC -- Overriding Xilinx file\r\r
2105 <C:/devtools/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda> with local file\r\r
2106 <c:/devtools/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>\r\r
2107 Using target part "5vfx70tff1136-1".\r\r
2108 WARNING:LIT:243 - Logical network N194 has no load.\r\r
2109 WARNING:LIT:395 - The above warning message is repeated 1028 more times for the\r\r
2110    following (max. 5 shown):\r\r
2111    N195,\r\r
2112    N196,\r\r
2113    N197,\r\r
2114    N198,\r\r
2115    N199\r\r
2116    To see the details of these warning messages, please use the -detail switch.\r\r
2117 Mapping design into LUTs...\r\r
2118 WARNING:MapLib:701 - Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin\r\r
2119    connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has\r\r
2120    been removed.\r\r
2121 WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top\r\r
2122    level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.\r\r
2123 WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been\r\r
2124    optimized out of the design.\r\r
2125 Writing file system_map.ngm...\r\r
2126 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2127    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
2128    of frag REGCLKAU connected to power/ground net\r\r
2129    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig\r\r
2130 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2131    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
2132    of frag REGCLKAL connected to power/ground net\r\r
2133    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig\r\r
2134 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2135    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
2136    of frag REGCLKAU connected to power/ground net\r\r
2137    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig\r\r
2138 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2139    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
2140    of frag REGCLKAL connected to power/ground net\r\r
2141    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig\r\r
2142 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2143    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2144    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
2145    of frag REGCLKAU connected to power/ground net\r\r
2146    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2147    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig\r\r
2148 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2149    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2150    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
2151    of frag REGCLKAL connected to power/ground net\r\r
2152    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2153    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig\r\r
2154 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2155    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2156    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
2157    of frag REGCLKAU connected to power/ground net\r\r
2158    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2159    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig\r\r
2160 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2161    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2162    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
2163    of frag REGCLKAL connected to power/ground net\r\r
2164    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2165    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig\r\r
2166 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2167    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2168    x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
2169    of frag RDRCLKU connected to power/ground net\r\r
2170    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2171    x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig\r\r
2172 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2173    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2174    x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
2175    of frag RDRCLKL connected to power/ground net\r\r
2176    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2177    x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig\r\r
2178 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2179    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2180    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2181    noeccerr.SDP\r\r
2182    of frag RDRCLKU connected to power/ground net\r\r
2183    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2184    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2185    noeccerr.SDP_RDRCLKU_tiesig\r\r
2186 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2187    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2188    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2189    noeccerr.SDP\r\r
2190    of frag RDRCLKL connected to power/ground net\r\r
2191    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2192    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2193    noeccerr.SDP_RDRCLKL_tiesig\r\r
2194 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2195    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2196    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2197    ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2198    of frag RDRCLKU connected to power/ground net\r\r
2199    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2200    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2201    ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
2202 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2203    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2204    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2205    ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2206    of frag RDRCLKL connected to power/ground net\r\r
2207    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2208    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2209    ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
2210 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2211    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2212    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2213    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2214    of frag RDRCLKU connected to power/ground net\r\r
2215    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2216    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2217    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
2218 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2219    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2220    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2221    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2222    of frag RDRCLKL connected to power/ground net\r\r
2223    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2224    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2225    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
2226 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2227    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2228    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2229    36.noeccerr.SDP\r\r
2230    of frag RDRCLKU connected to power/ground net\r\r
2231    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2232    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2233    36.noeccerr.SDP_RDRCLKU_tiesig\r\r
2234 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2235    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2236    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2237    36.noeccerr.SDP\r\r
2238    of frag RDRCLKL connected to power/ground net\r\r
2239    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2240    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2241    36.noeccerr.SDP_RDRCLKL_tiesig\r\r
2242 Running directed packing...\r\r
2243 Running delay-based LUT packing...\r\r
2244 Updating timing models...\r\r
2245 WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
2246    TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during\r\r
2247    timing analysis.\r\r
2248 INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report\r\r
2249    (.mrp).\r\r
2250 Running timing-driven placement...\r\r
2251 Total REAL time at the beginning of Placer: 2 mins 24 secs \r\r
2252 Total CPU  time at the beginning of Placer: 2 mins 19 secs \r\r
2253 \r\r
2254 Phase 1.1  Initial Placement Analysis\r\r
2255 Phase 1.1  Initial Placement Analysis (Checksum:3a0b7697) REAL time: 2 mins 44 secs \r\r
2256 \r\r
2257 Phase 2.7  Design Feasibility Check\r\r
2258 WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
2259    Components associated with this bus are as follows: \r\r
2260          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7>   IOSTANDARD = LVCMOS25\r\r
2261          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25\r\r
2262          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5>   IOSTANDARD = LVCMOS25\r\r
2263          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18\r\r
2264          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3>   IOSTANDARD = LVCMOS25\r\r
2265          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18\r\r
2266          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1>   IOSTANDARD = LVCMOS18\r\r
2267          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18\r\r
2268 \r\r
2269 \r\r
2270 WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
2271    Components associated with this bus are as follows: \r\r
2272          Comp: fpga_0_SRAM_Mem_DQ_pin<31>   IOSTANDARD = LVDCI_33\r\r
2273          Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33\r\r
2274          Comp: fpga_0_SRAM_Mem_DQ_pin<29>   IOSTANDARD = LVDCI_33\r\r
2275          Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33\r\r
2276          Comp: fpga_0_SRAM_Mem_DQ_pin<27>   IOSTANDARD = LVDCI_33\r\r
2277          Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33\r\r
2278          Comp: fpga_0_SRAM_Mem_DQ_pin<25>   IOSTANDARD = LVDCI_33\r\r
2279          Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33\r\r
2280          Comp: fpga_0_SRAM_Mem_DQ_pin<23>   IOSTANDARD = LVDCI_33\r\r
2281          Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33\r\r
2282          Comp: fpga_0_SRAM_Mem_DQ_pin<21>   IOSTANDARD = LVDCI_33\r\r
2283          Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33\r\r
2284          Comp: fpga_0_SRAM_Mem_DQ_pin<19>   IOSTANDARD = LVDCI_33\r\r
2285          Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33\r\r
2286          Comp: fpga_0_SRAM_Mem_DQ_pin<17>   IOSTANDARD = LVDCI_33\r\r
2287          Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33\r\r
2288          Comp: fpga_0_SRAM_Mem_DQ_pin<15>   IOSTANDARD = LVCMOS33\r\r
2289          Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33\r\r
2290          Comp: fpga_0_SRAM_Mem_DQ_pin<13>   IOSTANDARD = LVCMOS33\r\r
2291          Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33\r\r
2292          Comp: fpga_0_SRAM_Mem_DQ_pin<11>   IOSTANDARD = LVCMOS33\r\r
2293          Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33\r\r
2294          Comp: fpga_0_SRAM_Mem_DQ_pin<9>   IOSTANDARD = LVCMOS33\r\r
2295          Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33\r\r
2296          Comp: fpga_0_SRAM_Mem_DQ_pin<7>   IOSTANDARD = LVCMOS33\r\r
2297          Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33\r\r
2298          Comp: fpga_0_SRAM_Mem_DQ_pin<5>   IOSTANDARD = LVCMOS33\r\r
2299          Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33\r\r
2300          Comp: fpga_0_SRAM_Mem_DQ_pin<3>   IOSTANDARD = LVCMOS33\r\r
2301          Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33\r\r
2302          Comp: fpga_0_SRAM_Mem_DQ_pin<1>   IOSTANDARD = LVCMOS33\r\r
2303          Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33\r\r
2304 \r\r
2305 \r\r
2306 Phase 2.7  Design Feasibility Check (Checksum:3a0b7697) REAL time: 2 mins 45 secs \r\r
2307 \r\r
2308 Phase 3.31  Local Placement Optimization\r\r
2309 Phase 3.31  Local Placement Optimization (Checksum:c9fd22c3) REAL time: 2 mins 45 secs \r\r
2310 \r\r
2311 Phase 4.37  Local Placement Optimization\r\r
2312 Phase 4.37  Local Placement Optimization (Checksum:c9fd22c3) REAL time: 2 mins 45 secs \r\r
2313 \r\r
2314 Phase 5.33  Local Placement Optimization\r\r
2315 Phase 5.33  Local Placement Optimization (Checksum:c9fd22c3) REAL time: 10 mins 47 secs \r\r
2316 \r\r
2317 Phase 6.32  Local Placement Optimization\r\r
2318 Phase 6.32  Local Placement Optimization (Checksum:c9fd22c3) REAL time: 10 mins 52 secs \r\r
2319 \r\r
2320 Phase 7.2  Initial Clock and IO Placement\r\r
2321 \r\r
2322 \r\r
2323 \r\r
2324 There are 16 clock regions on the target FPGA device:\r\r
2325 |------------------------------------------|------------------------------------------|\r\r
2326 | CLOCKREGION_X0Y7:                        | CLOCKREGION_X1Y7:                        |\r\r
2327 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2328 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2329 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2330 |   4 center BUFIOs available, 0 in use    |                                          |\r\r
2331 |                                          |                                          |\r\r
2332 |------------------------------------------|------------------------------------------|\r\r
2333 | CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |\r\r
2334 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2335 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2336 |   4 edge BUFIOs available, 3 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2337 |   0 center BUFIOs available, 0 in use    |                                          |\r\r
2338 |                                          |                                          |\r\r
2339 |------------------------------------------|------------------------------------------|\r\r
2340 | CLOCKREGION_X0Y5:                        | CLOCKREGION_X1Y5:                        |\r\r
2341 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2342 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2343 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2344 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2345 |                                          |                                          |\r\r
2346 |------------------------------------------|------------------------------------------|\r\r
2347 | CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |\r\r
2348 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2349 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2350 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2351 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2352 |                                          |                                          |\r\r
2353 |------------------------------------------|------------------------------------------|\r\r
2354 | CLOCKREGION_X0Y3:                        | CLOCKREGION_X1Y3:                        |\r\r
2355 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2356 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2357 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2358 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2359 |                                          |                                          |\r\r
2360 |------------------------------------------|------------------------------------------|\r\r
2361 | CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |\r\r
2362 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2363 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2364 |   4 edge BUFIOs available, 3 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2365 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2366 |                                          |                                          |\r\r
2367 |------------------------------------------|------------------------------------------|\r\r
2368 | CLOCKREGION_X0Y1:                        | CLOCKREGION_X1Y1:                        |\r\r
2369 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2370 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use\r
2371       |\r\r
2372 |   4 edge BUFIOs available, 2 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2373 |   0 center BUFIOs available, 0 in use    |                                          |\r\r
2374 |                                          |                                          |\r\r
2375 |------------------------------------------|------------------------------------------|\r\r
2376 | CLOCKREGION_X0Y0:                        | CLOCKREGION_X1Y0:                        |\r\r
2377 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2378 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2379 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2380 |   4 center BUFIOs available, 0 in use    |                                          |\r\r
2381 |                                          |                                          |\r\r
2382 |------------------------------------------|------------------------------------------|\r\r
2383 \r\r
2384 \r\r
2385 Clock-Region: <CLOCKREGION_X0Y1>\r\r
2386   key resource utilizations (used/available): edge-bufios - 2/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
2387 |-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
2388 |       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
2389 |       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
2390 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2391 |       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region\r\r
2392 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2393 |       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
2394 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2395 |       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
2396 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2397 | clock |    region   |                                                                                      -----------------------------------------------\r\r
2398 |  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
2399 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2400 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>"\r\r
2401 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2402 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>"\r\r
2403 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2404 \r\r
2405 \r\r
2406 Clock-Region: <CLOCKREGION_X0Y2>\r\r
2407   key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4\r\r
2408 |-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
2409 |       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
2410 |       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
2411 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2412 |       | Upper Region|   8  |  0  |  0 |   60   |   60   |  1280 |   640 |  1920 |   0  |   0  |  1  |   0  | <- Available resources in the upper region\r\r
2413 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2414 |       |CurrentRegion|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
2415 |-------|-------------|------|-----|----|--------|-------\r
2416 -|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2417 |       | Lower Region|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
2418 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2419 | clock |    region   |                                                                                      -----------------------------------------------\r\r
2420 |  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
2421 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2422 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"\r\r
2423 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2424 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"\r\r
2425 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2426 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"\r\r
2427 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2428 \r\r
2429 \r\r
2430 Clock-Region: <CLOCKREGION_X0Y6>\r\r
2431   key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
2432 |-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
2433 |       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
2434 |       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
2435 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2436 |       | Upper Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region\r\r
2437 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2438 |       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
2439 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2440 |       | Lower Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
2441 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2442 | clock |    region   |                                                                                      -----------------------------------------------\r\r
2443 |  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
2444 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2445 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 | \r
2446     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"\r\r
2447 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2448 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"\r\r
2449 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2450 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"\r\r
2451 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2452 \r\r
2453 \r\r
2454 \r\r
2455 \r\r
2456 ######################################################################################\r\r
2457 # REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:\r\r
2458 #\r\r
2459 # Number of Regional Clocking Regions in the device: 16  (4 clock spines in each)\r\r
2460 # Number of Regional Clock Networks used in this design: 8 (each network can be\r\r
2461 # composed of up to 3 clock spines and cover up to 3 regional clock regions)\r\r
2462 # \r\r
2463 ######################################################################################\r\r
2464 \r\r
2465 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"\r\r
2466 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2467 "BUFIO_X0Y27" ;\r\r
2468 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =\r\r
2469 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
2470 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =\r\r
2471 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
2472 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =\r\r
2473 CLOCKREGION_X0Y6;\r\r
2474 \r\r
2475 \r\r
2476 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"\r\r
2477 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2478 "BUFIO_X0Y9" ;\r\r
2479 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =\r\r
2480 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
2481 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =\r\r
2482 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
2483 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =\r\r
2484 CLOCKREGION_X0Y2;\r\r
2485 \r\r
2486 \r\r
2487 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"\r\r
2488 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2489 "BUFIO_X0Y11" ;\r\r
2490 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =\r\r
2491 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
2492 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =\r\r
2493 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
2494 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =\r\r
2495 CLOCKREGION_X0Y2;\r\r
2496 \r\r
2497 \r\r
2498 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"\r\r
2499 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2500 "BUFIO_X0Y4" ;\r\r
2501 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =\r\r
2502 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
2503 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =\r\r
2504 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
2505 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =\r\r
2506 CLOCKREGION_X0Y1;\r\r
2507 \r\r
2508 \r\r
2509 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"\r\r
2510 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2511 "BUFIO_X0Y25" ;\r\r
2512 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =\r\r
2513 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
2514 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =\r\r
2515 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
2516 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =\r\r
2517 CLOCKREGION_X0Y6;\r\r
2518 \r\r
2519 \r\r
2520 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"\r\r
2521 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2522 "BUFIO_X0Y7" ;\r\r
2523 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =\r\r
2524 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
2525 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =\r\r
2526 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
2527 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =\r\r
2528 CLOCKREGION_X0Y1;\r\r
2529 \r\r
2530 \r\r
2531 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"\r\r
2532 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2533 "BUFIO_X0Y26" ;\r\r
2534 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =\r\r
2535 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
2536 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =\r\r
2537 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
2538 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =\r\r
2539 CLOCKREGION_X0Y6;\r\r
2540 \r\r
2541 \r\r
2542 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"\r\r
2543 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2544 "BUFIO_X0Y10" ;\r\r
2545 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =\r\r
2546 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
2547 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =\r\r
2548 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
2549 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =\r\r
2550 CLOCKREGION_X0Y2;\r\r
2551 \r\r
2552 \r\r
2553 Phase 7.2  Initial Clock and IO Placement (Checksum:b5943100) REAL time: 11 mins 10 secs \r\r
2554 \r\r
2555 Phase 8.36  Local Placement Optimization\r\r
2556 Phase 8.36  Local Placement Optimization (Checksum:b5943100) REAL time: 11 mins 10 secs \r\r
2557 \r\r
2558 .........\r
2559 ..............\r
2560 .......\r\r
2561 ....\r
2562 ......\r
2563 ......\r
2564 ......\r
2565 ......\r
2566 ......\r
2567 .......\r
2568 .......\r
2569 ......\r
2570 ........\r
2571 ......\r
2572 ........\r
2573 .......\r
2574 ........\r
2575 ........\r
2576 ......\r\r
2577 Phase 9.30  Global Clock Region Assignment\r\r
2578 \r\r
2579 \r\r
2580 ######################################################################################\r\r
2581 # GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:\r\r
2582 #\r\r
2583 # Number of Global Clock Regions : 16\r\r
2584 # Number of Global Clock Networks: 15\r\r
2585 #\r\r
2586 # Clock Region Assignment: SUCCESSFUL\r\r
2587 \r\r
2588 # Location of Clock Components\r\r
2589 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;\r\r
2590 INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;\r\r
2591 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;\r\r
2592 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;\r\r
2593 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;\r\r
2594 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;\r\r
2595 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;\r\r
2596 INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;\r\r
2597 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;\r\r
2598 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;\r\r
2599 INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;\r\r
2600 INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;\r\r
2601 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;\r\r
2602 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;\r\r
2603 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;\r\r
2604 INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;\r\r
2605 INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;\r\r
2606 INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;\r\r
2607 INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;\r\r
2608 INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;\r\r
2609 INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;\r\r
2610 INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;\r\r
2611 INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;\r\r
2612 INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;\r\r
2613 INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;\r\r
2614 INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;\r\r
2615 INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;\r\r
2616 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;\r\r
2617 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;\r\r
2618 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;\r\r
2619 INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;\r\r
2620 \r\r
2621 # clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1\r\r
2622 NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;\r\r
2623 TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;\r\r
2624 AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2625 \r\r
2626 # fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30\r\r
2627 NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
2628 TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
2629 AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2630 \r\r
2631 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29\r\r
2632 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
2633 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
2634 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
2635 \r\r
2636 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27\r\r
2637 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
2638 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
2639 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2640 \r\r
2641 # clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2\r\r
2642 NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;\r\r
2643 TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;\r\r
2644 AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2645 \r\r
2646 # clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3\r\r
2647 NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
2648 TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
2649 AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y3 ;\r\r
2650 \r\r
2651 # PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28\r\r
2652 NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;\r\r
2653 TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;\r\r
2654 AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2655 \r\r
2656 # fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8\r\r
2657 NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
2658 TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
2659 AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE =   CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
2660 \r\r
2661 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26\r\r
2662 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
2663 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
2664 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
2665 \r\r
2666 # clk_200_0000MHz driven by BUFGCTRL_X0Y4\r\r
2667 NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;\r\r
2668 TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;\r\r
2669 AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2670 \r\r
2671 # fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7\r\r
2672 NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
2673 TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
2674 AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE =   CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
2675 \r\r
2676 # fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31\r\r
2677 NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
2678 TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
2679 AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
2680 \r\r
2681 # clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5\r\r
2682 NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
2683 TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
2684 AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2685 \r\r
2686 # clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6\r\r
2687 NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;\r\r
2688 TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;\r\r
2689 AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2690 \r\r
2691 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0\r\r
2692 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
2693 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
2694 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
2695 \r\r
2696 # NOTE: \r\r
2697 # This report is provided to help reproduce successful clock-region \r\r
2698 # assignments. The report provides range constraints for all global \r\r
2699 # clock networks, in a format that is directly usable in ucf files. \r\r
2700 #\r\r
2701 #END of Global Clock Net Distribution UCF Constraints\r\r
2702 ######################################################################################\r\r
2703 \r\r
2704 \r\r
2705 ######################################################################################\r\r
2706 GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:\r\r
2707 \r\r
2708 Number of Global Clock Regions : 16\r\r
2709 Number of Global Clock Networks: 15\r\r
2710 \r\r
2711 Clock Region Assignment: SUCCESSFUL\r\r
2712 \r\r
2713 Clock-Region: <CLOCKREGION_X0Y0> \r\r
2714  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
2715 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2716    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2717    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2718 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2719      12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2720 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2721         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2722 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2723       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     38 |    676 |PCIe_Bridge/Bridge_Clk\r\r
2724       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    329 |clk_125_0000MHzPLL0_ADJUST\r\r
2725 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2726       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     40 |   1005 | Total \r\r
2727 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2728 \r\r
2729 \r\r
2730 Clock-Region: <CLOCKREGION_X1Y0> \r\r
2731  key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
2732 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2733    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2734    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2735 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2736       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2737 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2738         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2739 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2740       4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     55 |   1130 |PCIe_Bridge/Bridge_Clk\r\r
2741       4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     24 |     52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
2742       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     29 |clk_125_0000MHzPLL0_ADJUST\r\r
2743 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2744       8 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |      0 |      0 |     79 |   1211 | Total \r\r
2745 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2746 \r\r
2747 \r\r
2748 Clock-Region: <CLOCKREGION_X0Y1> \r\r
2749  key resource utilizations (used/available): global-clocks - 6/10 ;\r\r
2750 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2751    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2752    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2753 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2754      12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2755 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2756         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2757 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2758       2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     18 |    164 |PCIe_Bridge/Bridge_Clk\r\r
2759       0 |      0 |      0 |      0 |      0 |     18 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |clk_125_0000MHz90PLL0_ADJUST\r\r
2760       2 |      1 |      0 |      0 |      0 |     17 |      0 |      0 |      0 |      0 |      0 |      0 |     33 |    942 |clk_125_0000MHzPLL0_ADJUST\r\r
2761       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
2762       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_62_5000MHzPLL0_ADJUST\r\r
2763       0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>\r\r
2764 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2765       4 |      1 |      1 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     51 |   1110 | Total \r\r
2766 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2767 \r\r
2768 \r\r
2769 Clock-Region: <CLOCKREGION_X1Y1> \r\r
2770  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2771 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2772    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2773    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2774 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2775       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2776 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2777         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2778 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2779       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    104 |    750 |PCIe_Bridge/Bridge_Clk\r\r
2780       1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     15 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
2781       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    312 |clk_125_0000MHzPLL0_ADJUST\r\r
2782       0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
2783 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2784       1 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    104 |   1077 | Total \r\r
2785 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2786 \r\r
2787 \r\r
2788 Clock-Region: <CLOCKREGION_X0Y2> \r\r
2789  key resource utilizations (used/available): global-clocks - 5/10 ;\r\r
2790 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2791    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2792    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2793 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2794      12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2795 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2796         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2797 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2798       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      6 |      4 |PCIe_Bridge/Bridge_Clk\r\r
2799       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |clk_125_0000MHz90PLL0_ADJUST\r\r
2800       3 |      0 |      0 |      0 |      9 |     15 |      0 |      0 |      0 |      0 |      0 |      0 |     41 |   1074 |clk_125_0000MHzPLL0_ADJUST\r\r
2801       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
2802       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    109 |clk_62_5000MHzPLL0_ADJUST\r\r
2803 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2804       3 |      0 |      0 |      0 |      9 |     42 |      0 |      0 |      0 |      0 |      1 |      0 |     47 |   1207 | Total \r\r
2805 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2806 \r\r
2807 \r\r
2808 Clock-Region: <CLOCKREGION_X1Y2> \r\r
2809  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2810 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2811    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2812    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2813 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2814       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2815 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2816         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2817 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2818       1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    150 |    685 |PCIe_Bridge/Bridge_Clk\r\r
2819       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     59 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
2820       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk\r\r
2821       0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |    407 |clk_125_0000MHzPLL0_ADJUST\r\r
2822 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2823       1 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    178 |   1153 | Total \r\r
2824 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2825 \r\r
2826 \r\r
2827 Clock-Region: <CLOCKREGION_X0Y3> \r\r
2828  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2829 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2830    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2831    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2832 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2833       4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)\r\r
2834 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2835         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2836 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2837       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     79 |clk_125_0000MHz90PLL0_ADJUST\r\r
2838       0 |      0 |      0 |      0 |      8 |     17 |      0 |      0 |      1 |      0 |      0 |      0 |     20 |    286 |clk_125_0000MHzPLL0_ADJUST\r\r
2839       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz\r\r
2840       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     79 |clk_62_5000MHzPLL0_ADJUST\r\r
2841 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2842       0 |      0 |      0 |      0 |      8 |     17 |      0 |      0 |      1 |      0 |      0 |      0 |     20 |    447 | Total \r\r
2843 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2844 \r\r
2845 \r\r
2846 Clock-Region: <CLOCKREGION_X1Y3> \r\r
2847  key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
2848 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2849    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2850    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2851 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2852       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2853 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2854         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2855 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2856       2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    126 |PCIe_Bridge/Bridge_Clk\r\r
2857       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     27 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
2858       6 |      0 |      0 |      0 |      0 |      0 |     13 |      0 |      0 |      0 |      0 |      0 |    116 |    933 |clk_125_0000MHzPLL0_ADJUST\r\r
2859 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2860       8 |      0 |      0 |      0 |      0 |      0 |     13 |      0 |      0 |      0 |      0 |      0 |    116 |   1086 | Total \r\r
2861 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2862 \r\r
2863 \r\r
2864 Clock-Region: <CLOCKREGION_X0Y4> \r\r
2865  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2866 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2867    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2868    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2869 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2870       4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)\r\r
2871 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2872         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2873 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2874       2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     33 |clk_125_0000MHz90PLL0_ADJUST\r\r
2875       4 |      0 |      0 |      0 |      1 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     51 |    262 |clk_125_0000MHzPLL0_ADJUST\r\r
2876       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |clk_62_5000MHzPLL0_ADJUST\r\r
2877       0 |      0 |      0 |      0 |      6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
2878 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2879       6 |      0 |      0 |      0 |      7 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     51 |    329 | Total \r\r
2880 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2881 \r\r
2882 \r\r
2883 Clock-Region: <CLOCKREGION_X1Y4> \r\r
2884  key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
2885 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2886    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2887    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2888 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2889      10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2890 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2891         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2892 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2893       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |PCIe_Bridge/Bridge_Clk\r\r
2894       3 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     76 |   1046 |clk_125_0000MHzPLL0_ADJUST\r\r
2895       0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     23 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
2896 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2897       3 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |     76 |   1089 | Total \r\r
2898 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2899 \r\r
2900 \r\r
2901 Clock-Region: <CLOCKREGION_X0Y5> \r\r
2902  key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
2903 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2904    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2905    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2906 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2907      12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2908 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2909         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2910 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2911       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     49 |clk_125_0000MHz90PLL0_ADJUST\r\r
2912       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     72 |    601 |clk_125_0000MHzPLL0_ADJUST\r\r
2913       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     99 |clk_62_5000MHzPLL0_ADJUST\r\r
2914 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2915       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     72 |    749 | Total \r\r
2916 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2917 \r\r
2918 \r\r
2919 Clock-Region: <CLOCKREGION_X1Y5> \r\r
2920  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2921 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2922    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2923    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2924 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2925      10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2926 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2927         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2928 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2929       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |PCIe_Bridge/Bridge_Clk\r\r
2930       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    126 |    746 |clk_125_0000MHzPLL0_ADJUST\r\r
2931       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
2932       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     14 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
2933 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2934       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    126 |    789 | Total \r\r
2935 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2936 \r\r
2937 \r\r
2938 Clock-Region: <CLOCKREGION_X0Y6> \r\r
2939  key resource utilizations (used/available): global-clocks - 7/10 ;\r\r
2940 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2941    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2942    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2943 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2944      12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2945 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2946         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2947 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2948       0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg\r\r
2949       0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin\r\r
2950       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |clk_125_0000MHz90PLL0_ADJUST\r\r
2951       0 |      0 |      0 |      0 |      0 |      8 |      0 |      0 |      0 |      0 |      0 |      0 |     91 |    751 |clk_125_0000MHzPLL0_ADJUST\r\r
2952       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
2953       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    249 |clk_62_5000MHzPLL0_ADJUST\r\r
2954       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     15 |      8 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
2955 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2956       0 |      0 |      2 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |    106 |   1010 | Total \r\r
2957 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2958 \r\r
2959 \r\r
2960 Clock-Region: <CLOCKREGION_X1Y6> \r\r
2961  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
2962 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2963    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2964    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2965 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2966       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2967 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2968         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2969 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2970       0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     97 |    796 |clk_125_0000MHzPLL0_ADJUST\r\r
2971       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
2972 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2973       0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     97 |    800 | Total \r\r
2974 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2975 \r\r
2976 \r\r
2977 Clock-Region: <CLOCKREGION_X0Y7> \r\r
2978  key resource utilizations (used/available): global-clocks - 3/10 ;\r\r
2979 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2980    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2981    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2982 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2983      12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2984 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2985         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2986 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2987       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    106 |    471 |clk_125_0000MHzPLL0_ADJUST\r\r
2988       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     10 |    310 |clk_62_5000MHzPLL0_ADJUST\r\r
2989       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
2990 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2991       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    116 |    782 | Total \r\r
2992 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2993 \r\r
2994 \r\r
2995 Clock-Region: <CLOCKREGION_X1Y7> \r\r
2996  key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
2997 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2998    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2999    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
3000 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3001       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
3002 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3003         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
3004 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3005       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    146 |    674 |clk_125_0000MHzPLL0_ADJUST\r\r
3006 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3007       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    146 |    674 | Total \r\r
3008 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3009 \r\r
3010 NOTE:\r\r
3011 The above detailed report is the initial placement of the logic after the clock region assignment. The final placement\r\r
3012 may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks\r\r
3013 maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.\r\r
3014 \r\r
3015 \r\r
3016 # END of Global Clock Net Loads Distribution Report:\r\r
3017 ######################################################################################\r\r
3018 \r\r
3019 \r\r
3020 Phase 9.30  Global Clock Region Assignment (Checksum:b5943100) REAL time: 12 mins 45 secs \r\r
3021 \r\r
3022 Phase 10.3  Local Placement Optimization\r\r
3023 Phase 10.3  Local Placement Optimization (Checksum:b5943100) REAL time: 12 mins 46 secs \r\r
3024 \r\r
3025 Phase 11.5  Local Placement Optimization\r\r
3026 Phase 11.5  Local Placement Optimization (Checksum:b5943100) REAL time: 12 mins 47 secs \r\r
3027 \r\r
3028 Phase 12.8  Global Placement\r\r
3029 ..\r
3030 ...........\r
3031 ...........\r
3032 .........\r\r
3033 ......\r
3034 ....\r
3035 .....\r
3036 .....\r
3037 .....\r
3038 .....\r
3039 .....\r
3040 .....\r
3041 ....\r
3042 .....\r
3043 .....\r
3044 .....\r
3045 ....\r
3046 ......\r
3047 .....\r
3048 ......\r
3049 .......\r
3050 ......\r
3051 .......\r
3052 .......\r
3053 .......\r
3054 ........\r
3055 ...\r\r
3056 .\r
3057 .....\r
3058 .....\r
3059 .....\r
3060 .....\r
3061 ......\r
3062 ......\r
3063 ......\r
3064 ......\r
3065 ......\r
3066 .....\r\r
3067 .....\r
3068 ....\r
3069 .....\r
3070 ....\r
3071 ....\r
3072 ....\r
3073 ....\r
3074 ...\r
3075 ...\r
3076 ....\r
3077 ...\r
3078 ...\r
3079 ..\r
3080 .\r
3081 ...\r
3082 ...\r
3083 ...\r
3084 ..\r
3085 ...\r
3086 .\r
3087 .\r
3088 ...\r
3089 ..\r
3090 ...\r
3091 ..\r
3092 ...\r
3093 ...\r
3094 ...\r
3095 ....\r
3096 ...\r
3097 ....\r
3098 ...\r
3099 .\r
3100 ...\r
3101 ...\r
3102 ...\r
3103 ..\r
3104 ....\r
3105 ..\r
3106 ...\r
3107 ..\r
3108 ...\r
3109 ....\r\r
3110 .\r
3111 .\r
3112 .\r
3113 ..\r
3114 ...\r
3115 .\r
3116 ..\r
3117 ..\r
3118 ...\r
3119 ...\r
3120 ...\r
3121 .\r
3122 ...\r
3123 ...\r
3124 ..\r
3125 ...\r
3126 ...\r
3127 ...\r
3128 ...\r
3129 .\r\r
3130 .\r
3131 .\r
3132 ..\r
3133 ...\r
3134 ..\r
3135 .\r
3136 ....\r
3137 ....\r
3138 ....\r
3139 .\r
3140 ..\r
3141 .....\r\r
3142 .\r
3143 ...\r
3144 ....\r
3145 ...\r
3146 .......\r
3147 .....\r\r
3148 .\r
3149 ....\r
3150 ....\r
3151 ....\r
3152 .....\r
3153 ......\r
3154 .....\r
3155 ....\r
3156 ....\r
3157 ....\r
3158 ....\r\r
3159 Phase 12.8  Global Placement (Checksum:64c223c7) REAL time: 20 mins 44 secs \r\r
3160 \r\r
3161 Phase 13.29  Local Placement Optimization\r\r
3162 Phase 13.29  Local Placement Optimization (Checksum:64c223c7) REAL time: 20 mins 44 secs \r\r
3163 \r\r
3164 Phase 14.5  Local Placement Optimization\r\r
3165 Phase 14.5  Local Placement Optimization (Checksum:64c223c7) REAL time: 20 mins 49 secs \r\r
3166 \r\r
3167 Phase 15.18  Placement Optimization\r\r
3168 Phase 15.18  Placement Optimization (Checksum:d0a37aa3) REAL time: 23 mins 25 secs \r\r
3169 \r\r
3170 Phase 16.5  Local Placement Optimization\r\r
3171 Phase 16.5  Local Placement Optimization (Checksum:d0a37aa3) REAL time: 23 mins 28 secs \r\r
3172 \r\r
3173 Phase 17.34  Placement Validation\r\r
3174 Phase 17.34  Placement Validation (Checksum:d0a37aa3) REAL time: 23 mins 30 secs \r\r
3175 \r\r
3176 Total REAL time to Placer completion: 23 mins 34 secs \r\r
3177 Total CPU  time to Placer completion: 22 mins 30 secs \r\r
3178 Running post-placement packing...\r\r
3179 Writing output files...\r\r
3180 \r\r
3181 Design Summary:\r\r
3182 Number of errors:      0\r\r
3183 Number of warnings:   52\r\r
3184 Slice Logic Utilization:\r\r
3185   Number of Slice Registers:                14,755 out of  44,800   32%\r\r
3186     Number used as Flip Flops:              14,754\r\r
3187     Number used as Latches:                      1\r\r
3188   Number of Slice LUTs:                     16,419 out of  44,800   36%\r\r
3189     Number used as logic:                   15,565 out of  44,800   34%\r\r
3190       Number using O6 output only:          14,103\r\r
3191       Number using O5 output only:             371\r\r
3192       Number using O5 and O6:                1,091\r\r
3193     Number used as Memory:                     724 out of  13,120    5%\r\r
3194       Number used as Dual Port RAM:            228\r\r
3195         Number using O6 output only:            12\r\r
3196         Number using O5 output only:            32\r\r
3197         Number using O5 and O6:                184\r\r
3198       Number used as Single Port RAM:            4\r\r
3199         Number using O6 output only:             4\r\r
3200       Number used as Shift Register:           492\r\r
3201         Number using O6 output only:           492\r\r
3202     Number used as exclusive route-thru:       130\r\r
3203   Number of route-thrus:                       581\r\r
3204     Number using O6 output only:               490\r\r
3205     Number using O5 output only:                81\r\r
3206     Number using O5 and O6:                     10\r\r
3207 \r\r
3208 Slice Logic Distribution:\r\r
3209   Number of occupied Slices:                 7,735 out of  11,200   69%\r\r
3210   Number of LUT Flip Flop pairs used:       21,404\r\r
3211     Number with an unused Flip Flop:         6,649 out of  21,404   31%\r\r
3212     Number with an unused LUT:               4,985 out of  21,404   23%\r\r
3213     Number of fully used LUT-FF pairs:       9,770 out of  21,404   45%\r\r
3214     Number of unique control sets:           1,397\r\r
3215     Number of slice register sites lost\r\r
3216       to control set restrictions:           3,281 out of  44,800    7%\r\r
3217 \r\r
3218   A LUT Flip Flop pair for this architecture represents one LUT paired with\r\r
3219   one Flip Flop within a slice.  A control set is a unique combination of\r\r
3220   clock, reset, set, and enable signals for a registered element.\r\r
3221   The Slice Logic Distribution report is not meaningful if the design is\r\r
3222   over-mapped for a non-slice resource or if Placement fails.\r\r
3223   OVERMAPPING of BRAM resources should be ignored if the design is\r\r
3224   over-mapped for a non-BRAM resource or if placement fails.\r\r
3225 \r\r
3226 IO Utilization:\r\r
3227   Number of bonded IOBs:                       255 out of     640   39%\r\r
3228     Number of LOCed IOBs:                      255 out of     255  100%\r\r
3229     IOB Flip Flops:                            494\r\r
3230     Number of bonded IPADs:                      4 out of      50    8%\r\r
3231     Number of bonded OPADs:                      2 out of      32    6%\r\r
3232 \r\r
3233 Specific Feature Utilization:\r\r
3234   Number of BlockRAM/FIFO:                      22 out of     148   14%\r\r
3235     Number using BlockRAM only:                 20\r\r
3236     Number using FIFO only:                      2\r\r
3237     Total primitives used:\r\r
3238       Number of 36k BlockRAM used:              16\r\r
3239       Number of 18k BlockRAM used:               6\r\r
3240       Number of 36k FIFO used:                   2\r\r
3241     Total Memory used (KB):                    756 out of   5,328   14%\r\r
3242   Number of BUFG/BUFGCTRLs:                     15 out of      32   46%\r\r
3243     Number used as BUFGs:                       15\r\r
3244   Number of IDELAYCTRLs:                         3 out of      22   13%\r\r
3245   Number of BUFDSs:                              1 out of       8   12%\r\r
3246   Number of BUFIOs:                              8 out of      80   10%\r\r
3247   Number of DCM_ADVs:                            1 out of      12    8%\r\r
3248   Number of DSP48Es:                            13 out of     128   10%\r\r
3249   Number of GTX_DUALs:                           1 out of       8   12%\r\r
3250   Number of PCIEs:                               1 out of       3   33%\r\r
3251     Number of LOCed PCIEs:                       1 out of       1  100%\r\r
3252   Number of PLL_ADVs:                            2 out of       6   33%\r\r
3253   Number of PPC440s:                             1 out of       1  100%\r\r
3254 \r\r
3255   Number of RPM macros:           64\r\r
3256 Average Fanout of Non-Clock Nets:                3.80\r\r
3257 \r\r
3258 Peak Memory Usage:  888 MB\r\r
3259 Total REAL time to MAP completion:  24 mins 23 secs \r\r
3260 Total CPU time to MAP completion:   23 mins 18 secs \r\r
3261 \r\r
3262 Mapping completed.\r\r
3263 See MAP report file "system_map.mrp" for details.\r\r
3264 \r\r
3265 \r\r
3266 \r\r
3267 #----------------------------------------------#\r\r
3268 # Starting program par\r\r
3269 # par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd\r\r
3270 system.pcf \r\r
3271 #----------------------------------------------#\r\r
3272 Release 11.2 - par L.46 (nt)\r\r
3273 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3274 PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/parBmgr.acd> with local file\r\r
3275 <c:/devtools/Xilinx/11.1/ISE/data/parBmgr.acd>\r\r
3276 \r\r
3277 \r\r
3278 Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
3279 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3280    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3281 \r\r
3282 Constraints file: system.pcf.\r\r
3283    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3284 WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(90242)]\r\r
3285    overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(90241)].\r\r
3286 \r\r
3287 \r\r
3288 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)\r\r
3289 Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)\r\r
3290 \r\r
3291 WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP       \r\r
3292    "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.\r\r
3293 INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please\r\r
3294    consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.\r\r
3295 \r\r
3296 Device speed data version:  "PRODUCTION 1.65 2009-06-01".\r\r
3297 \r\r
3298 \r\r
3299 \r\r
3300 Device Utilization Summary:\r\r
3301 \r\r
3302    Number of BUFDSs                          1 out of 8      12%\r\r
3303    Number of BUFGs                          15 out of 32     46%\r\r
3304    Number of BUFIOs                          8 out of 80     10%\r\r
3305    Number of DCM_ADVs                        1 out of 12      8%\r\r
3306    Number of DSP48Es                        13 out of 128    10%\r\r
3307    Number of FIFO36_72_EXPs                  2 out of 148     1%\r\r
3308       Number of LOCed FIFO36_72_EXPs         2 out of 2     100%\r\r
3309 \r\r
3310    Number of GTX_DUALs                       1 out of 8      12%\r\r
3311    Number of IDELAYCTRLs                     3 out of 22     13%\r\r
3312       Number of LOCed IDELAYCTRLs            3 out of 3     100%\r\r
3313 \r\r
3314    Number of ILOGICs                       131 out of 800    16%\r\r
3315       Number of LOCed ILOGICs                8 out of 131     6%\r\r
3316 \r\r
3317    Number of External IOBs                 255 out of 640    39%\r\r
3318       Number of LOCed IOBs                 255 out of 255   100%\r\r
3319 \r\r
3320    Number of IODELAYs                       80 out of 800    10%\r\r
3321       Number of LOCed IODELAYs               8 out of 80     10%\r\r
3322 \r\r
3323    Number of External IPADs                  4 out of 690     1%\r\r
3324       Number of LOCed IPADs                  4 out of 4     100%\r\r
3325 \r\r
3326    Number of JTAGPPCs                        1 out of 1     100%\r\r
3327    Number of OLOGICs                       236 out of 800    29%\r\r
3328    Number of External OPADs                  2 out of 32      6%\r\r
3329       Number of LOCed OPADs                  2 out of 2     100%\r\r
3330 \r\r
3331    Number of PCIEs                           1 out of 3      33%\r\r
3332       Number of LOCed PCIEs                  1 out of 1     100%\r\r
3333 \r\r
3334    Number of PLL_ADVs                        2 out of 6      33%\r\r
3335    Number of PPC440s                         1 out of 1     100%\r\r
3336    Number of RAMB18X2SDPs                    4 out of 148     2%\r\r
3337    Number of RAMB36SDP_EXPs                  6 out of 148     4%\r\r
3338       Number of LOCed RAMB36SDP_EXPs         1 out of 6      16%\r\r
3339 \r\r
3340    Number of RAMB36_EXPs                    10 out of 148     6%\r\r
3341       Number of LOCed RAMB36_EXPs            6 out of 10     60%\r\r
3342 \r\r
3343    Number of Slice Registers             14755 out of 44800  32%\r\r
3344       Number used as Flip Flops          14754\r\r
3345       Number used as Latches                 1\r\r
3346       Number used as LatchThrus              0\r\r
3347 \r\r
3348    Number of Slice LUTS                  16419 out of 44800  36%\r\r
3349    Number of Slice LUT-Flip Flop pairs   21404 out of 44800  47%\r\r
3350 \r\r
3351 \r\r
3352 Overall effort level (-ol):   High \r\r
3353 Router effort level (-rl):    High \r\r
3354 \r\r
3355 Starting initial Timing Analysis.  REAL time: 1 mins 25 secs \r\r
3356 Finished initial Timing Analysis.  REAL time: 1 mins 27 secs \r\r
3357 \r\r
3358 WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load.  PAR will not attempt to route this\r\r
3359    signal.\r\r
3360 WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load.  PAR will not attempt to route this\r\r
3361    signal.\r\r
3362 WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load.  PAR will not attempt to route this\r\r
3363    signal.\r\r
3364 WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load.  PAR will not attempt to route this\r\r
3365    signal.\r\r
3366 WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load.  PAR will not attempt to route this\r\r
3367    signal.\r\r
3368 Starting Router\r\r
3369 \r\r
3370 INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note\r\r
3371    that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,\r\r
3372    verify that the same connectivity is available in the target device for this implementation. \r\r
3373 \r\r
3374 Phase  1  : 106522 unrouted;      REAL time: 1 mins 45 secs \r\r
3375 \r\r
3376 Phase  2  : 93293 unrouted;      REAL time: 2 mins \r\r
3377 \r\r
3378 Phase  3  : 39046 unrouted;      REAL time: 4 mins 11 secs \r\r
3379 \r\r
3380 Phase  4  : 39025 unrouted; (Setup:0, Hold:89741, Component Switching Limit:0)     REAL time: 4 mins 40 secs \r\r
3381 \r\r
3382 Updating file: system.ncd with current fully routed design.\r\r
3383 \r\r
3384 Phase  5  : 0 unrouted; (Setup:0, Hold:90756, Component Switching Limit:0)     REAL time: 6 mins 33 secs \r\r
3385 \r\r
3386 Phase  6  : 0 unrouted; (Setup:0, Hold:90756, Component Switching Limit:0)     REAL time: 6 mins 33 secs \r\r
3387 \r\r
3388 Phase  7  : 0 unrouted; (Setup:0, Hold:90756, Component Switching Limit:0)     REAL time: 6 mins 33 secs \r\r
3389 \r\r
3390 Phase  8  : 0 unrouted; (Setup:0, Hold:90756, Component Switching Limit:0)     REAL time: 6 mins 33 secs \r\r
3391 \r\r
3392 Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 8 mins 30 secs \r\r
3393 \r\r
3394 Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 9 mins 7 secs \r\r
3395 Total REAL time to Router completion: 9 mins 7 secs \r\r
3396 Total CPU time to Router completion: 8 mins 54 secs \r\r
3397 \r\r
3398 Partition Implementation Status\r\r
3399 -------------------------------\r\r
3400 \r\r
3401   No Partitions were found in this design.\r\r
3402 \r\r
3403 -------------------------------\r\r
3404 \r\r
3405 Generating "PAR" statistics.\r\r
3406 \r\r
3407 **************************\r\r
3408 Generating Clock Report\r\r
3409 **************************\r\r
3410 \r\r
3411 +---------------------+--------------+------+------+------------+-------------+\r\r
3412 |        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|\r\r
3413 +---------------------+--------------+------+------+------------+-------------+\r\r
3414 |clk_125_0000MHzPLL0_ |              |      |      |            |             |\r\r
3415 |              ADJUST | BUFGCTRL_X0Y2| No   | 4263 |  0.532     |  2.076      |\r\r
3416 +---------------------+--------------+------+------+------------+-------------+\r\r
3417 |PCIe_Bridge/Bridge_C |              |      |      |            |             |\r\r
3418 |                  lk |BUFGCTRL_X0Y28| No   | 1472 |  0.444     |  2.085      |\r\r
3419 +---------------------+--------------+------+------+------------+-------------+\r\r
3420 |clk_62_5000MHzPLL0_A |              |      |      |            |             |\r\r
3421 |               DJUST | BUFGCTRL_X0Y6| No   |  490 |  0.318     |  2.057      |\r\r
3422 +---------------------+--------------+------+------+------------+-------------+\r\r
3423 |clk_125_0000MHz90PLL |              |      |      |            |             |\r\r
3424 |            0_ADJUST | BUFGCTRL_X0Y5| No   |  162 |  0.254     |  2.028      |\r\r
3425 +---------------------+--------------+------+------+------------+-------------+\r\r
3426 |fpga_0_SysACE_Compac |              |      |      |            |             |\r\r
3427 |tFlash_SysACE_CLK_pi |              |      |      |            |             |\r\r
3428 |             n_BUFGP | BUFGCTRL_X0Y8| No   |   55 |  0.150     |  1.770      |\r\r
3429 +---------------------+--------------+------+------+------------+-------------+\r\r
3430 |PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
3431 |dge/comp_block_plus/ |              |      |      |            |             |\r\r
3432 |comp_endpoint/core_c |              |      |      |            |             |\r\r
3433 |                  lk |BUFGCTRL_X0Y27| No   |   94 |  0.260     |  2.085      |\r\r
3434 +---------------------+--------------+------+------+------------+-------------+\r\r
3435 |fpga_0_Ethernet_MAC_ |              |      |      |            |             |\r\r
3436 |PHY_rx_clk_pin_BUFGP |              |      |      |            |             |\r\r
3437 |                     |BUFGCTRL_X0Y30| No   |   12 |  0.093     |  1.934      |\r\r
3438 +---------------------+--------------+------+------+------------+-------------+\r\r
3439 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3440 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3441 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3442 | y_io/delayed_dqs<0> |        IO Clk| No   |   18 |  0.095     |  0.419      |\r\r
3443 +---------------------+--------------+------+------+------------+-------------+\r\r
3444 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3445 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3446 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3447 | y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |\r\r
3448 +---------------------+--------------+------+------+------------+-------------+\r\r
3449 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3450 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3451 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3452 | y_io/delayed_dqs<2> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3453 +---------------------+--------------+------+------+------------+-------------+\r\r
3454 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3455 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3456 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3457 | y_io/delayed_dqs<3> |        IO Clk| No   |   18 |  0.107     |  0.404      |\r\r
3458 +---------------------+--------------+------+------+------------+-------------+\r\r
3459 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3460 |M/u_ddr2_top/u_mem_i |              |      |\r
3461       |            |             |\r\r
3462 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3463 | y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3464 +---------------------+--------------+------+------+------------+-------------+\r\r
3465 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3466 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3467 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3468 | y_io/delayed_dqs<4> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3469 +---------------------+--------------+------+------+------------+-------------+\r\r
3470 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3471 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3472 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3473 | y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |\r\r
3474 +---------------------+--------------+------+------+------------+-------------+\r\r
3475 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3476 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3477 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3478 | y_io/delayed_dqs<7> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3479 +---------------------+--------------+------+------+------------+-------------+\r\r
3480 |fpga_0_Ethernet_MAC_ |              |      |      |            |             |\r\r
3481 |PHY_tx_clk_pin_BUFGP |              |      |      |            |             |\r\r
3482 |                     |BUFGCTRL_X0Y31| No   |    6 |  0.004     |  1.941      |\r\r
3483 +---------------------+--------------+------+------+------------+-------------+\r\r
3484 | clk_125_0000MHzPLL0 | BUFGCTRL_X0Y1| No   |    2 |  0.000     |  1.739      |\r\r
3485 +---------------------+--------------+------+------+------------+-------------+\r\r
3486 |PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
3487 |dge/comp_block_plus/ |              |      |      |            |             |\r\r
3488 |comp_endpoint/pcie_b |              |      |      |            |             |\r\r
3489 |        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.096     |  1.916      |\r\r
3490 +---------------------+--------------+------+------+------------+-------------+\r\r
3491 |     clk_200_0000MHz | BUFGCTRL_X0Y4| No   |    4 |  0.128     |  1.879      |\r\r
3492 +---------------------+--------------+------+------+------------+-------------+\r\r
3493 |RS232_Uart_1_Interru |              |      |      |            |             |\r\r
3494 |                  pt |         Local|      |    1 |  0.000     |  1.071      |\r\r
3495 +---------------------+--------------+------+------+------------+-------------+\r\r
3496 |Ethernet_MAC/Etherne |              |      |      |            |             |\r\r
3497 |  t_MAC/phy_tx_clk_i |         Local|      |    9 |  2.410     |  3.454      |\r\r
3498 +---------------------+--------------+------+------+------------+-------------+\r\r
3499 |ppc440_0_jtagppc_bus |              |      |      |            |             |\r\r
3500 |         _JTGC405TCK |         Local|      |    1 |  0.000     |  1.678      |\r\r
3501 +---------------------+--------------+------+------+------------+-------------+\r\r
3502 |PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
3503 |dge/comp_block_plus/ |              |      |      |            |             |\r\r
3504 |comp_endpoint/pcie_b |              |      |      |            |             |\r\r
3505 |lk/SIO/.pcie_gt_wrap |              |      |      |            |             |\r\r
3506 |  per_i/icdrreset<0> |         Local|      |    1 |  0.000     |  0.590      |\r\r
3507 +---------------------+--------------+------+------+------------+-------------+\r\r
3508 \r\r
3509 * Net Skew is the difference between the minimum and maximum routing\r\r
3510 only delays for the net. Note this is different from Clock Skew which\r\r
3511 is reported in TRCE timing report. Clock Skew is the difference between\r\r
3512 the minimum and maximum path delays which includes logic delays.\r\r
3513 \r\r
3514 Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)\r\r
3515 \r\r
3516 Number of Timing Constraints that were not applied: 5\r\r
3517 \r\r
3518 Asterisk (*) preceding a constraint indicates it was not met.\r\r
3519    This may be due to a setup or hold violation.\r\r
3520 \r\r
3521 ----------------------------------------------------------------------------------------------------------\r\r
3522   Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   \r\r
3523                                             |             |    Slack   | Achievable | Errors |    Score   \r\r
3524 ----------------------------------------------------------------------------------------------------------\r\r
3525   NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP       |     0.030ns|     7.970ns|       0|           0\r\r
3526   s HIGH 50%                                | HOLD        |     0.030ns|            |       0|           0\r\r
3527                                             | MINPERIOD   |     0.000ns|     8.000ns|       0|           0\r\r
3528 ------------------------------------------------------------------------------------------------------\r\r
3529   NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP       |     0.075ns|     3.925ns|       0|           0\r\r
3530   lus/comp_endpoint/core_clk" PERIOD =      | HOLD        |     0.366ns|            |       0|           0\r\r
3531       4 ns HIGH 50%                         | MINPERIOD   |     0.000ns|     4.000ns|       0|           0\r\r
3532 ------------------------------------------------------------------------------------------------------\r\r
3533   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.012ns|     0.838ns|       0|           0\r\r
3534   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3535   dqs[2].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3536   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3537 ------------------------------------------------------------------------------------------------------\r\r
3538   TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_ | SETUP       |     0.021ns|     1.879ns|       0|           0\r\r
3539   CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.026ns|            |       0|           0\r\r
3540      1.9 ns                                 |             |            |            |        |            \r\r
3541 ------------------------------------------------------------------------------------------------------\r\r
3542   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     0.026ns|     7.974ns|       0|           0\r\r
3543   L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.079ns|            |       0|           0\r\r
3544   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3545   LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
3546   HIGH 50%                                  |             |            |            |        |            \r\r
3547 ------------------------------------------------------------------------------------------------------\r\r
3548   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
3549   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3550   dqs[0].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3551   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3552 ------------------------------------------------------------------------------------------------------\r\r
3553   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
3554   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3555   dqs[1].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3556   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3557 ------------------------------------------------------------------------------------------------------\r\r
3558   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
3559   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3560   dqs[5].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3561   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3562 ------------------------------------------------------------------------------------------------------\r\r
3563   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3564   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3565   dqs[3].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3566   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3567 ------------------------------------------------------------------------------------------------------\r\r
3568   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3569   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3570   dqs[4].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3571   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3572 ------------------------------------------------------------------------------------------------------\r\r
3573   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3574   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3575   dqs[6].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3576   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3577 ------------------------------------------------------------------------------------------------------\r\r
3578   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3579   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3580   dqs[7].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3581   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3582 ------------------------------------------------------------------------------------------------------\r\r
3583   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.068ns|     0.532ns|       0|           0\r\r
3584   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3585   qs<0>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3586 ------------------------------------------------------------------------------------------------------\r\r
3587   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3588   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3589   qs<1>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3590 ------------------------------------------------------------------------------------------------------\r\r
3591   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3592   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3593   qs<2>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3594 ------------------------------------------------------------------------------------------------------\r\r
3595   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3596   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3597   qs<3>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3598 ------------------------------------------------------------------------------------------------------\r\r
3599   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3600   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3601   qs<4>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3602 ------------------------------------------------------------------------------------------------------\r\r
3603   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3604   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3605   qs<5>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3606 ------------------------------------------------------------------------------------------------------\r\r
3607   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3608   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3609   qs<6>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3610 ------------------------------------------------------------------------------------------------------\r\r
3611   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3612   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3613   qs<7>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3614 ------------------------------------------------------------------------------------------------------\r\r
3615   TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP       |     0.449ns|     7.551ns|       0|           0\r\r
3616   _Clk" TO TIMEGRP "Bridge_Clk" 8 ns        | HOLD        |     0.456ns|            |       0|           0\r\r
3617     DATAPATHONLY                            |             |            |            |        |            \r\r
3618 ------------------------------------------------------------------------------------------------------\r\r
3619   TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP       |     0.639ns|     7.361ns|       0|           0\r\r
3620   ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns        | HOLD        |     0.465ns|            |       0|           0\r\r
3621     DATAPATHONLY                            |             |            |            |        |            \r\r
3622 ------------------------------------------------------------------------------------------------------\r\r
3623   TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns  | MINPERIOD   |     1.010ns|     3.990ns|       0|           0\r\r
3624   HIGH 50%                                  |             |            |            |        |            \r\r
3625 ------------------------------------------------------------------------------------------------------\r\r
3626   TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY    |     1.640ns|     4.360ns|       0|           0\r\r
3627   RP "PADS" TO TIMEGRP         "RXCLK_GRP_E | HOLD        |     1.060ns|            |       0|           0\r\r
3628   thernet_MAC" 6 ns                         |             |            |            |        |            \r\r
3629 ------------------------------------------------------------------------------------------------------\r\r
3630   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     2.000ns|     4.973ns|       0|           0\r\r
3631   L0_CLK_OUT_0_ = PERIOD TIMEGRP         "c | HOLD        |     0.476ns|            |       0|           0\r\r
3632   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3633   LK_OUT_0_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
3634   PHASE 2 ns HIGH 50%                       |             |            |            |        |            \r\r
3635 ------------------------------------------------------------------------------------------------------\r\r
3636   TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.000ns|     4.000ns|       0|           0\r\r
3637   pin" 100 MHz HIGH 50%                     |             |            |            |        |            \r\r
3638 ------------------------------------------------------------------------------------------------------\r\r
3639   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     3.644ns|     1.356ns|       0|           0\r\r
3640   L0_CLK_OUT_3_ = PERIOD TIMEGRP         "c | HOLD        |     0.476ns|            |       0|           0\r\r
3641   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3642   LK_OUT_3_" TS_sys_clk_pin *         2 HIG |             |            |            |        |            \r\r
3643   H 50%                                     |             |            |            |        |            \r\r
3644 ------------------------------------------------------------------------------------------------------\r\r
3645   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     4.149ns|     8.008ns|       0|           0\r\r
3646   L0_CLK_OUT_4_ = PERIOD TIMEGRP         "c | HOLD        |     0.172ns|            |       0|           0\r\r
3647   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3648   LK_OUT_4_" TS_sys_clk_pin *         0.625 |             |            |            |        |            \r\r
3649    HIGH 50%                                 |             |            |            |        |            \r\r
3650 ------------------------------------------------------------------------------------------------------\r\r
3651   NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW     |     4.422ns|     0.578ns|       0|           0\r\r
3652   UFGP" MAXSKEW = 5 ns                      |             |            |            |        |            \r\r
3653 ------------------------------------------------------------------------------------------------------\r\r
3654   NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW     |     4.778ns|     0.222ns|       0|           0\r\r
3655   UFGP" MAXSKEW = 5 ns                      |             |            |            |        |            \r\r
3656 ------------------------------------------------------------------------------------------------------\r\r
3657   TS_clock_generator_0_clock_generator_0_PL | MINPERIOD   |     4.900ns|     3.100ns|       0|           0\r\r
3658   L0_CLK_OUT_1_ = PERIOD TIMEGRP         "c |             |            |            |        |            \r\r
3659   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3660   LK_OUT_1_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
3661   HIGH 50%                                  |             |            |            |        |            \r\r
3662 ------------------------------------------------------------------------------------------------------\r\r
3663   TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY    |     7.423ns|     2.577ns|       0|           0\r\r
3664   GRP "TXCLK_GRP_Ethernet_MAC" TO         T |             |            |            |        |            \r\r
3665   IMEGRP "PADS" 10 ns                       |             |            |            |        |            \r\r
3666 ------------------------------------------------------------------------------------------------------\r\r
3667   NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP       |     9.210ns|    13.685ns|       0|           0\r\r
3668   UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.479ns|            |       0|           0\r\r
3669 ------------------------------------------------------------------------------------------------------\r\r
3670   TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP       |    13.663ns|     6.337ns|       0|           0\r\r
3671   M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO      | HOLD        |     0.290ns|            |       0|           0\r\r
3672       TIMEGRP "TNM_CLK90" TS_MC_CLK * 4     |             |            |            |        |            \r\r
3673 ------------------------------------------------------------------------------------------------------\r\r
3674   TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP       |    15.735ns|     4.265ns|       0|           0\r\r
3675    TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO       | HOLD        |     0.915ns|            |       0|           0\r\r
3676      TIMEGRP "TNM_CLK0" TS_MC_CLK * 4       |             |            |            |        |            \r\r
3677 ------------------------------------------------------------------------------------------------------\r\r
3678   TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.698ns|     2.302ns|       0|           0\r\r
3679   NM_GATE_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.003ns|            |       0|           0\r\r
3680     TS_MC_CLK * 4                           |             |            |            |        |            \r\r
3681 ------------------------------------------------------------------------------------------------------\r\r
3682   TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP       |    18.121ns|     1.879ns|       0|           0\r\r
3683   P "TNM_CAL_RDEN_DLY" TO TIMEGRP         " | HOLD        |     0.001ns|            |       0|           0\r\r
3684   TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |            \r\r
3685 ------------------------------------------------------------------------------------------------------\r\r
3686   TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    18.132ns|     1.868ns|       0|           0\r\r
3687   NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.023ns|            |       0|           0\r\r
3688     TS_MC_CLK * 4                           |             |            |            |        |            \r\r
3689 ------------------------------------------------------------------------------------------------------\r\r
3690   NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP       |    26.579ns|     3.421ns|       0|           0\r\r
3691   K_pin_BUFGP/IBUFG" PERIOD = 30 ns         | HOLD        |     0.465ns|            |       0|           0\r\r
3692    HIGH 50%                                 |             |            |            |        |            \r\r
3693 ------------------------------------------------------------------------------------------------------\r\r
3694   NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP       |    32.855ns|     7.145ns|       0|           0\r\r
3695   UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.357ns|            |       0|           0\r\r
3696 ------------------------------------------------------------------------------------------------------\r\r
3697   Pin to Pin Skew Constraint                | MAXDELAY    | 2106523.523ns| 2106523.837ns|       0|           0\r\r
3698 ------------------------------------------------------------------------------------------------------\r\r
3699   TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A         |         N/A|         N/A|     N/A|         N/A\r\r
3700   P "TNM_RDEN_SEL_MUX" TO TIMEGRP         " |             |            |            |        |            \r\r
3701   TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |            \r\r
3702 ------------------------------------------------------------------------------------------------------\r\r
3703   NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A         |         N/A|         N/A|     N/A|         N/A\r\r
3704   s HIGH 50%                                |             |            |            |        |            \r\r
3705 ------------------------------------------------------------------------------------------------------\r\r
3706 \r\r
3707 \r\r
3708 Derived Constraint Report\r\r
3709 Derived Constraints for TS_MC_CLK\r\r
3710 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3711 |                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |\r\r
3712 |           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
3713 |                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |\r\r
3714 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3715 |TS_MC_CLK                      |      5.000ns|      3.990ns|      1.584ns|            0|            0|            0|          345|\r\r
3716 | TS_MC_PHY_INIT_DATA_SEL_0     |     20.000ns|      4.265ns|          N/A|            0|            0|           21|            0|\r\r
3717 | TS_MC_PHY_INIT_DATA_SEL_90    |     20.000ns|      6.337ns|          N/A|            0|            0|          274|            0|\r\r
3718 | TS_MC_GATE_DLY                |     20.000ns|      2.302ns|          N/A|            0|            0|           40|            0|\r\r
3719 | TS_MC_RDEN_DLY                |     20.000ns|      1.868ns|          N/A|            0|            0|            5|            0|\r\r
3720 | TS_MC_CAL_RDEN_DLY            |     20.000ns|      1.879ns|          N/A|            0|            0|            5|            0|\r\r
3721 | TS_MC_RDEN_SEL_MUX            |     20.000ns|          N/A|          N/A|            0|            0|            0|            0|\r\r
3722 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3723 \r\r
3724 Derived Constraints for TS_sys_clk_pin\r\r
3725 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3726 |                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |\r\r
3727 |           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
3728 |                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |\r\r
3729 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3730 |TS_sys_clk_pin                 |     10.000ns|      4.000ns|      9.967ns|            0|            0|            0|      4043451|\r\r
3731 | TS_clock_generator_0_clock_gen|      8.000ns|      4.973ns|          N/A|            0|            0|          626|            0|\r\r
3732 | erator_0_PLL0_CLK_OUT_0_      |             |             |             |             |             |             |             |\r\r
3733 | TS_clock_generator_0_clock_gen|      8.000ns|      3.100ns|          N/A|            0|            0|            0|            0|\r\r
3734 | erator_0_PLL0_CLK_OUT_1_      |             |             |             |             |             |             |             |\r\r
3735 | TS_clock_generator_0_clock_gen|      8.000ns|      7.974ns|          N/A|            0|            0|      4031781|            0|\r\r
3736 | erator_0_PLL0_CLK_OUT_2_      |             |             |             |             |             |             |             |\r\r
3737 | TS_clock_generator_0_clock_gen|      5.000ns|      1.356ns|          N/A|            0|            0|            2|            0|\r\r
3738 | erator_0_PLL0_CLK_OUT_3_      |             |             |             |             |             |             |             |\r\r
3739 | TS_clock_generator_0_clock_gen|     16.000ns|      8.008ns|          N/A|            0|            0|        11042|            0|\r\r
3740 | erator_0_PLL0_CLK_OUT_4_      |             |             |             |             |             |             |             |\r\r
3741 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3742 \r\r
3743 All constraints were met.\r\r
3744 INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the \r\r
3745    constraint does not cover any paths or that it has no requested value.\r\r
3746 \r\r
3747 \r\r
3748 Generating Pad Report.\r\r
3749 \r\r
3750 All signals are completely routed.\r\r
3751 \r\r
3752 WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.\r\r
3753 \r\r
3754 Loading device for application Rf_Device from file '5vlx50t.nph' in environment\r\r
3755 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3756 INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128\r\r
3757 INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints\r\r
3758    found: 128, number successful: 128\r\r
3759 Total REAL time to PAR completion: 10 mins 4 secs \r\r
3760 Total CPU time to PAR completion: 9 mins 36 secs \r\r
3761 \r\r
3762 Peak Memory Usage:  754 MB\r\r
3763 \r\r
3764 Placer: Placement generated during map.\r\r
3765 Routing: Completed - No errors found.\r\r
3766 Timing: Completed - No errors found.\r\r
3767 \r\r
3768 Number of error messages: 0\r\r
3769 Number of warning messages: 9\r\r
3770 Number of info messages: 4\r\r
3771 \r\r
3772 Writing design to file system.ncd\r\r
3773 \r\r
3774 \r\r
3775 \r\r
3776 PAR done!\r\r
3777 \r\r
3778 \r\r
3779 \r\r
3780 #----------------------------------------------#\r\r
3781 # Starting program post_par_trce\r\r
3782 # trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf \r\r
3783 #----------------------------------------------#\r\r
3784 Release 11.2 - Trace  (nt)\r\r
3785 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3786 \r\r
3787 \r\r
3788 PMSPEC -- Overriding Xilinx file\r\r
3789 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
3790 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
3791 Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
3792 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3793    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3794 WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD =\r\r
3795    8 ns HIGH 50%;> [system.pcf(90242)] overrides constraint <NET\r\r
3796    "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(90241)].\r\r
3797 \r\r
3798 WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
3799    TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP        "TNM_CLK0" TS_MC_CLK * 4;\r\r
3800    ignored during timing analysis.\r\r
3801 INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more\r\r
3802    information, see the TSI report.  Please consult the Xilinx Command Line\r\r
3803    Tools User Guide for information on generating a TSI report.\r\r
3804 --------------------------------------------------------------------------------\r\r
3805 Release 11.2 Trace  (nt)\r\r
3806 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3807 \r\r
3808 trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf\r\r
3809 \r\r
3810 \r\r
3811 Design file:              system.ncd\r\r
3812 Physical constraint file: system.pcf\r\r
3813 Device,speed:             xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING\r\r
3814 level 0)\r\r
3815 Report level:             error report\r\r
3816 --------------------------------------------------------------------------------\r\r
3817 \r\r
3818 INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths\r\r
3819    option. All paths that are not constrained will be reported in the\r\r
3820    unconstrained paths section(s) of the report.\r\r
3821 INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a\r\r
3822    50 Ohm transmission line loading model.  For the details of this model, and\r\r
3823    for more information on accounting for different loading conditions, please\r\r
3824    see the device datasheet.\r\r
3825 \r\r
3826 \r\r
3827 Timing summary:\r\r
3828 ---------------\r\r
3829 \r\r
3830 Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)\r\r
3831 \r\r
3832 Constraints cover 4233435 paths, 18 nets, and 96471 connections\r\r
3833 \r\r
3834 Design statistics:\r\r
3835    Minimum period:  13.685ns (Maximum frequency:  73.073MHz)\r\r
3836    Maximum path delay from/to any node:   7.551ns\r\r
3837    Maximum net delay:   0.838ns\r\r
3838    Maximum net skew:   0.578ns\r\r
3839 \r\r
3840 \r\r
3841 Analysis completed Tue Jun 30 23:01:07 2009\r\r
3842 --------------------------------------------------------------------------------\r\r
3843 \r\r
3844 Generating Report ...\r\r
3845 \r\r
3846 Number of warnings: 2\r\r
3847 Number of info messages: 3\r\r
3848 Total time: 1 mins 41 secs \r\r
3849 \r\r
3850 \r\r
3851 xflow done!\r\r
3852 touch __xps/system_routed\r
3853 xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par\r
3854 Analyzing implementation/system.par\r\r
3855 *********************************************\r
3856 Running Bitgen..\r
3857 *********************************************\r
3858 cd implementation; bitgen -w -f bitgen.ut system; cd ..\r
3859 Release 11.2 - Bitgen L.46 (nt)\r\r
3860 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3861 PMSPEC -- Overriding Xilinx file\r\r
3862 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
3863 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
3864 Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
3865 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3866    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3867 Opened constraints file system.pcf.\r\r
3868 \r\r
3869 Tue Jun 30 23:01:40 2009\r\r
3870 \r\r
3871 Running DRC.\r\r
3872 WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.\r\r
3873    Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX\r\r
3874    Transceiver User Guide to ensure that the design SelectIO usage meets the\r\r
3875    guidelines to minimize the impact on GTX performance. \r\r
3876 WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
3877    Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.\r\r
3878    This is not good design practice. Use the CE pin to control the loading of\r\r
3879    data into the flip-flop.\r\r
3880 WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
3881    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w\r\r
3882    rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good\r\r
3883    design practice. Use the CE pin to control the loading of data into the\r\r
3884    flip-flop.\r\r
3885 WARNING:PhysDesignRules:367 - The signal\r\r
3886    <PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does\r\r
3887    not drive any load pins in the design.\r\r
3888 WARNING:PhysDesignRules:367 - The signal\r\r
3889    <PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not\r\r
3890    drive any load pins in the design.\r\r
3891 WARNING:PhysDesignRules:367 - The signal\r\r
3892    <xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not\r\r
3893    drive any load pins in the design.\r\r
3894 WARNING:PhysDesignRules:367 - The signal\r\r
3895    <xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not\r\r
3896    drive any load pins in the design.\r\r
3897 WARNING:PhysDesignRules:367 - The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull>\r\r
3898    is incomplete. The signal does not drive any load pins in the design.\r\r
3899 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3900    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3901    qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3902    used.\r\r
3903 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3904    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3905    qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3906    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3907 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3908    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3909    qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3910    used.\r\r
3911 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3912    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3913    qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3914    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3915 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3916    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3917    qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3918    used.\r\r
3919 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3920    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3921    qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3922    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3923 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3924    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3925    qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3926    used.\r\r
3927 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3928    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3929    qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3930    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3931 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3932    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3933    qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3934    used.\r\r
3935 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3936    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3937    qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3938    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3939 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3940    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3941    qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3942    used.\r\r
3943 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3944    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3945    qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3946    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3947 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3948    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3949    qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3950    used.\r\r
3951 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3952    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3953    qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3954    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3955 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3956    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3957    qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3958    used.\r\r
3959 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3960    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3961    qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3962    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3963 WARNING:PhysDesignRules:367 - The signal\r\r
3964    <ppc440_0_apu_fpu_virtex5/ppc440_0_apu_fpu_virtex5/gen_apu_fpu_dp_lo.netlist/\r\r
3965    fpu_is_full.sqrt_sqrt_flt_pt_op_sqrt_op.spd.op_exp_exp_sig_del_delay_55_2/Pro\r\r
3966    toComp7000.C6LUT.O6> is incomplete. The signal does not drive any load pins\r\r
3967    in the design.\r\r
3968 WARNING:PhysDesignRules:367 - The signal\r\r
3969    <ppc440_0_apu_fpu_virtex5/ppc440_0_apu_fpu_virtex5/gen_apu_fpu_dp_lo.netlist/\r\r
3970    fpu_is_full.sqrt_sqrt_flt_pt_op_sqrt_op.spd.op_exp_exp_sig_del_delay_55_1/Pro\r\r
3971    toComp7000.C6LUT.O6> is incomplete. The signal does not drive any load pins\r\r
3972    in the design.\r\r
3973 DRC detected 0 errors and 26 warnings.  Please see the previously displayed\r\r
3974 individual error or warning messages for more details.\r\r
3975 Creating bit map...\r\r
3976 Saving bit stream in "system.bit".\r\r
3977 Bitstream generation is complete.\r\r
3978 \r
3979 \r
3980 Done!
3981 \r
3982 Writing filter settings....
3983 \r
3984 Done writing filter settings to:
3985         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
3986 \r
3987 Done writing Tab View settings to:
3988         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
3989 \r
3990 Xilinx Platform Studio (XPS)\r
3991 Xilinx EDK 11.2 Build EDK_LS3.47
3992 \r
3993 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3994 \r
3995 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
3996 \r
3997 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
3998 \r
3999 Generating Block Diagram to Buffer
4000 \r
4001 Generated Block Diagram SVG
4002 \r
4003 At Local date and time: Wed Jul 01 10:06:56 2009
4004  make -f system.make download started...
4005 \r
4006 cp -f /cygdrive/c/devtools/Xilinx/11.1/EDK/sw/lib/ppc440/ppc440_bootloop.elf bootloops/ppc440_0.elf\r
4007 *********************************************\r
4008 Initializing BRAM contents of the bitstream\r
4009 *********************************************\r
4010 bitinit -p xc5vfx70tff1136-1 system.mhs  -pe ppc440_0  bootloops/ppc440_0.elf  \\r
4011 -bt implementation/system.bit -o implementation/download.bit\r
4012 \r\r
4013 bitinit version Xilinx EDK 11.2 Build EDK_LS3.47\r\r
4014 Copyright (c) Xilinx Inc. 2002.\r\r
4015 \r\r
4016 Parsing MHS File system.mhs...\r\r
4017 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4018    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4019    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
4020 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
4021    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4022    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
4023 \r\r
4024 Overriding IP level properties ...\r\r
4025 \r\r
4026 Performing IP level DRCs on properties...\r\r
4027 \r\r
4028 Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
4029 Address Map for Processor ppc440_0\r\r
4030   (0b0000000000-0b0011111111) ppc440_0  \r\r
4031   (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC\r\r
4032   (0x81000000-0x8100ffff) Ethernet_MAC  plb_v46_0\r\r
4033   (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0\r\r
4034   (0x81420000-0x8142ffff) LEDs_Positions        plb_v46_0\r\r
4035   (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0\r\r
4036   (0x81460000-0x8146ffff) DIP_Switches_8Bit     plb_v46_0\r\r
4037   (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0\r\r
4038   (0x81800000-0x8180ffff) xps_intc_0    plb_v46_0\r\r
4039   (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0\r\r
4040   (0x84000000-0x8400ffff) RS232_Uart_1  plb_v46_0\r\r
4041   (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0\r\r
4042   (0xc0000000-0xdfffffff) PCIe_Bridge   plb_v46_0\r\r
4043   (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0\r\r
4044   (0xf8000000-0xf80fffff) SRAM  plb_v46_0\r\r
4045   (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0\r\r
4046 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
4047    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
4048    01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
4049    C_SPLB0_P2P value to 0\r\r
4050 \r\r
4051 Computing clock values...\r\r
4052 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
4053    'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
4054    performed for IPs connected to that clock port, unless they are connected\r\r
4055    through the clock generator IP. \r\r
4056 \r\r
4057 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
4058    'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
4059    performed for IPs connected to that clock port, unless they are connected\r\r
4060    through the clock generator IP. \r\r
4061 \r\r
4062 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4063    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4064    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
4065    C_PLBV46_NUM_MASTERS value to 1\r\r
4066 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4067    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4068    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
4069    C_PLBV46_NUM_SLAVES value to 12\r\r
4070 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4071    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4072    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
4073    C_PLBV46_MID_WIDTH value to 1\r\r
4074 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4075    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4076    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
4077    value to 128\r\r
4078 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
4079    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
4080    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
4081    PARAMETER C_SPLB_DWIDTH value to 128\r\r
4082 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
4083    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
4084    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
4085    PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
4086 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
4087    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
4088    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
4089    PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
4090 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
4091    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
4092    \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
4093    value to 0x2000\r\r
4094 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
4095    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
4096    \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
4097    C_PORT_DWIDTH value to 64\r\r
4098 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
4099    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
4100    \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
4101    value to 8\r\r
4102 INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
4103    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
4104    _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
4105    C_SPLB_DWIDTH value to 128\r\r
4106 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
4107    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4108    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4109    value to 128\r\r
4110 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
4111    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4112    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4113    value to 128\r\r
4114 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
4115    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4116    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4117    value to 128\r\r
4118 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
4119    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4120    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4121    value to 128\r\r
4122 INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
4123    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
4124    ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4125    value to 128\r\r
4126 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
4127    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
4128    a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
4129    C_SPLB_DWIDTH value to 128\r\r
4130 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
4131    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
4132    a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
4133    C_SPLB_SMALLEST_MASTER value to 128\r\r
4134 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4135    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4136    b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
4137    C_MPLB_DWIDTH value to 128\r\r
4138 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4139    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4140    b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
4141    C_MPLB_SMALLEST_SLAVE value to 128\r\r
4142 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4143    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4144    b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
4145    C_SPLB_MID_WIDTH value to 1\r\r
4146 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4147    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4148    b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
4149    C_SPLB_NUM_MASTERS value to 1\r\r
4150 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4151    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4152    b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
4153    C_SPLB_SMALLEST_MASTER value to 128\r\r
4154 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4155    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4156    b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
4157    C_SPLB_DWIDTH value to 128\r\r
4158 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4159    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4160    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
4161    C_PLBV46_NUM_MASTERS value to 1\r\r
4162 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4163    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4164    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
4165    C_PLBV46_NUM_SLAVES value to 1\r\r
4166 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4167    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4168    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
4169    C_PLBV46_MID_WIDTH value to 1\r\r
4170 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4171    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4172    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
4173    value to 128\r\r
4174 INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
4175    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
4176    2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
4177    PARAMETER C_SPLB_DWIDTH value to 128\r\r
4178 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
4179    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
4180    \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
4181    C_SPLB_DWIDTH value to 128\r\r
4182 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
4183    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
4184    \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
4185    C_SPLB_MID_WIDTH value to 1\r\r
4186 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
4187    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
4188    \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
4189    C_SPLB_NUM_MASTERS value to 1\r\r
4190 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
4191    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
4192    ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4193    value to 128\r\r
4194 \r\r
4195 Checking platform address map ...\r\r
4196 \r\r
4197 Initializing Memory...\r\r
4198 Running Data2Mem with the following command:\r\r
4199 data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd\r\r
4200 "bootloops/ppc440_0.elf" tag ppc440_0  -o b implementation/download.bit \r\r
4201 Memory Initialization completed successfully.\r\r
4202 \r\r
4203 *********************************************\r
4204 Downloading Bitstream onto the target board\r
4205 *********************************************\r
4206 impact -batch etc/download.cmd\r
4207 Release 11.2 - iMPACT L.46 (nt)\r\r
4208 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4209 Preference Table\r\r
4210 Name                 Setting             \r\r
4211 StartupClock         Auto_Correction     \r\r
4212 AutoSignature        False               \r\r
4213 KeepSVF              False               \r\r
4214 ConcurrentMode       False               \r\r
4215 UseHighz             False               \r\r
4216 ConfigOnFailure      Stop                \r\r
4217 UserLevel            Novice              \r\r
4218 MessageLevel         Detailed            \r\r
4219 svfUseTime           false               \r\r
4220 SpiByteSwap          Auto_Correction     \r\r
4221 AutoDetecting cable. Please wait.\r\r
4222 Connecting to cable (Usb Port - USB21).\r\r
4223 Checking cable driver.\r\r
4224  Driver file xusb_xp2.sys found.\r\r
4225  Driver version: src=2301, dest=2301.\r\r
4226  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
4227 13:58:07, version = 900.\r\r
4228  Cable PID = 0008.\r\r
4229  Max current requested during enumeration is 300 mA.\r\r
4230 Type = 0x0005.\r\r
4231 write (count, cmdBuffer, dataBuffer) failed C0000004.\r\r
4232  Cable Type = 3, Revision = 0.\r\r
4233  Setting cable speed to 6 MHz.\r\r
4234 Cable connection established.\r\r
4235 Firmware version = 2301.\r\r
4236 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
4237 Firmware hex file version = 2401.\r\r
4238 Downloading c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex.\r\r
4239 Downloaded firmware version = 2401.\r\r
4240 PLD file version = 200Dh.\r\r
4241  PLD version = 200Dh.\r\r
4242 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
4243 INFO:iMPACT:1777 - \r
4244    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
4245 \r
4246 ----------------------------------------------------------------------\r\r
4247 ----------------------------------------------------------------------\r\r
4248 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
4249 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
4250 INFO:iMPACT:1777 - \r
4251    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
4252 \r
4253 ----------------------------------------------------------------------\r\r
4254 ----------------------------------------------------------------------\r\r
4255 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
4256 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
4257 \r
4258 INFO:iMPACT:1777 - \r
4259    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
4260 \r
4261 ----------------------------------------------------------------------\r\r
4262 ----------------------------------------------------------------------\r\r
4263 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4264 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
4265 \r
4266 ----------------------------------------------------------------------\r\r
4267 ----------------------------------------------------------------------\r\r
4268 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4269 ----------------------------------------------------------------------\r\r
4270 ----------------------------------------------------------------------\r\r
4271 done.\r\r
4272 Elapsed time =      1 sec.\r\r
4273 Elapsed time =      0 sec.\r\r
4274 '5': Loading file 'implementation/download.bit' ...\r\r
4275 INFO:iMPACT:1777 - \r
4276    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
4277 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4278 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4279 \r
4280 done.\r\r
4281 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
4282 ----------------------------------------------------------------------\r\r
4283 ----------------------------------------------------------------------\r\r
4284 ----------------------------------------------------------------------\r\r
4285 Maximum TCK operating frequency for this device chain: 10000000.\r\r
4286 Validating chain...\r\r
4287 Boundary-scan chain validated successfully.\r\r
4288 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
4289 \r
4290 5: Device Temperature: Current Reading:   41.02 C, Min. Reading:   27.73 C, Max.\r\r
4291 Reading:   41.02 C\r\r
4292 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.\r\r
4293 Reading:   1.002 V\r\r
4294 5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.\r\r
4295 Reading:   2.508 V\r\r
4296 '5': Programming device...\r\r
4297  Match_cycle = 2.\r\r
4298 done.\r\r
4299 '5': Reading status register contents...\r\r
4300 CRC error                                         :         0\r\r
4301 Decryptor security set                            :         0\r\r
4302 DCM locked                                        :         1\r\r
4303 DCI matched                                       :         1\r\r
4304 End of startup signal from Startup block          :         1\r\r
4305 status of GTS_CFG_B                               :         1\r\r
4306 status of GWE                                     :         1\r\r
4307 status of GHIGH                                   :         1\r\r
4308 value of MODE pin M0                              :         1\r\r
4309 value of MODE pin M1                              :         0\r\r
4310 Value of MODE pin M2                              :         1\r\r
4311 Internal signal indicates when housecleaning is completed:         1\r\r
4312 Value driver in from INIT pad                     :         1\r\r
4313 Internal signal indicates that chip is configured :         1\r\r
4314 Value of DONE pin                                 :         1\r\r
4315 Indicates when ID value written does not match chip ID:         0\r\r
4316 Decryptor error Signal                            :         0\r\r
4317 System Monitor Over-Temperature Alarm             :         0\r\r
4318 startup_state[18] CFG startup state machine       :         0\r\r
4319 startup_state[19] CFG startup state machine       :         0\r\r
4320 startup_state[20] CFG startup state machine       :         1\r\r
4321 E-fuse program voltage available                  :         0\r\r
4322 SPI Flash Type[22] Select                         :         1\r\r
4323 SPI Flash Type[23] Select                         :         1\r\r
4324 SPI Flash Type[24] Select                         :         1\r\r
4325 CFG bus width auto detection result               :         0\r\r
4326 CFG bus width auto detection result               :         0\r\r
4327 Reserved                                          :         0\r\r
4328 BPI address wrap around error                     :         0\r\r
4329 IPROG pulsed                                      :         0\r\r
4330 read back crc error                               :         0\r\r
4331 Indicates that efuse logic is busy                :         0\r\r
4332  Match_cycle = 2.\r\r
4333 '5': Programmed successfully.\r\r
4334 Elapsed time =     11 sec.\r\r
4335 ----------------------------------------------------------------------\r\r
4336 ----------------------------------------------------------------------\r\r
4337 ----------------------------------------------------------------------\r\r
4338 ----------------------------------------------------------------------\r\r
4339 ----------------------------------------------------------------------\r\r
4340 ----------------------------------------------------------------------\r\r
4341 ----------------------------------------------------------------------\r\r
4342 ----------------------------------------------------------------------\r\r
4343 INFO:iMPACT:2219 - Status register values:\r
4344 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
4345 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
4346 INFO:iMPACT - '5': Programing completed successfully.\r
4347 INFO:iMPACT - '5': Checking done pin....done.\r
4348 \r
4349 \r
4350 \r
4351 Done!
4352 \r
4353 At Local date and time: Wed Jul 01 10:07:40 2009
4354  make -f system.make program started...
4355 \r
4356 *********************************************\r
4357 Creating software libraries...\r
4358 *********************************************\r
4359 libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss\r
4360 libgen\r\r
4361 Xilinx EDK 11.2 Build EDK_LS3.47\r\r
4362 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4363 \r\r
4364 Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg\r\r
4365 __xps/ise/xmsgprops.lst system.mss \r\r
4366 \r\r
4367 Release 11.2 - psf2Edward EDK_LS3.47 (nt)\r\r
4368 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4369 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4370    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4371    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
4372 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
4373    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4374    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
4375 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4376    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4377    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
4378 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
4379    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4380    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
4381 \r\r
4382 Checking platform configuration ...\r\r
4383 IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4384 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
4385 line 109 - 1 master(s) : 12 slave(s)\r\r
4386 IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4387 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
4388 line 290 - 1 master(s) : 1 slave(s)\r\r
4389 IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -\r\r
4390 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
4391 line 394 - 1 master(s) : 1 slave(s)\r\r
4392 \r\r
4393 Checking port drivers...\r\r
4394 WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
4395    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4396    hs line 461 - floating connection!\r\r
4397 \r\r
4398 Performing Clock DRCs...\r\r
4399 \r\r
4400 Performing Reset DRCs...\r\r
4401 \r\r
4402 Overriding system level properties...\r\r
4403 \r\r
4404 Running system level update procedures...\r\r
4405 \r\r
4406 Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
4407 \r\r
4408 Running system level DRCs...\r\r
4409 \r\r
4410 Performing System level DRCs on properties...\r\r
4411 \r\r
4412 Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
4413 WARNING:EDK:411 - pcie -\r\r
4414    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4415    ss line 77 - deprecated driver!\r\r
4416 WARNING:EDK:411 - emaclite -\r\r
4417    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4418    ss line 83 - deprecated driver!\r\r
4419 INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: \r\r
4420   - DDR2_SDRAM\r\r
4421   - DIP_Switches_8Bit\r\r
4422   - Ethernet_MAC\r\r
4423   - IIC_EEPROM\r\r
4424   - LEDs_8Bit\r\r
4425   - LEDs_Positions\r\r
4426   - PCIe_Bridge\r\r
4427   - Push_Buttons_5Bit\r\r
4428   - RS232_Uart_1\r\r
4429   - SRAM\r\r
4430   - SysACE_CompactFlash\r\r
4431   - ppc440_0_apu_fpu_virtex5\r\r
4432   - xps_bram_if_cntlr_1\r\r
4433   - xps_intc_0\r\r
4434 \r\r
4435 -- Generating libraries for processor: ppc440_0 --\r\r
4436 \r\r
4437 \r\r
4438 Staging source files.\r\r
4439 Running DRCs.\r\r
4440 Running generate.\r\r
4441 Running post_generate.\r\r
4442 Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"\r\r
4443 "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440  -O2 -c"\r\r
4444 "EXTRA_COMPILER_FLAGS=-g"'.\r\r
4445 \r\r
4446 Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"\r\r
4447 "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440  -O2 -c"\r\r
4448 "EXTRA_COMPILER_FLAGS=-g"'.\r\r
4449 Compiling common\r
4450 powerpc-eabi-ar: creating ../../../lib/libxil.a
4451 \r
4452 Compiling lldma\r
4453 Compiling standalone\r
4454 Compiling gpio\r
4455 Compiling emaclite\r
4456 Compiling iic\r
4457 Compiling pci\r
4458 Compiling uartlite\r
4459 Compiling sysace\r
4460 Compiling intc\r
4461 Compiling cpu_ppc440\r
4462 Running execs_generate.\r\r
4463 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
4464     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
4465 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
4466 powerpc-eabi-size RTOSDemo/executable.elf \r
4467    text    data     bss     dec     hex filename\r
4468   51202     372   87844  139418   2209a RTOSDemo/executable.elf\r
4469 \r
4470 \r
4471 Done!
4472 \r
4473 At Local date and time: Wed Jul 01 11:26:01 2009
4474  make -f system.make download started...
4475 \r
4476 *********************************************\r
4477 Downloading Bitstream onto the target board\r
4478 *********************************************\r
4479 impact -batch etc/download.cmd\r
4480 Release 11.2 - iMPACT L.46 (nt)\r\r
4481 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4482 Preference Table\r\r
4483 Name                 Setting             \r\r
4484 StartupClock         Auto_Correction     \r\r
4485 AutoSignature        False               \r\r
4486 KeepSVF              False               \r\r
4487 ConcurrentMode       False               \r\r
4488 UseHighz             False               \r\r
4489 ConfigOnFailure      Stop                \r\r
4490 UserLevel            Novice              \r\r
4491 MessageLevel         Detailed            \r\r
4492 svfUseTime           false               \r\r
4493 SpiByteSwap          Auto_Correction     \r\r
4494 AutoDetecting cable. Please wait.\r\r
4495 Connecting to cable (Usb Port - USB21).\r\r
4496 Checking cable driver.\r\r
4497  Driver file xusb_xp2.sys found.\r\r
4498  Driver version: src=2301, dest=2301.\r\r
4499  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
4500 13:58:07, version = 900.\r\r
4501  Cable PID = 0008.\r\r
4502  Max current requested during enumeration is 300 mA.\r\r
4503 Type = 0x0005.\r\r
4504  Cable Type = 3, Revision = 0.\r\r
4505  Setting cable speed to 6 MHz.\r\r
4506 Cable connection established.\r\r
4507 Firmware version = 2401.\r\r
4508 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
4509 Firmware hex file version = 2401.\r\r
4510 PLD file version = 200Dh.\r\r
4511  PLD version = 200Dh.\r\r
4512 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
4513 INFO:iMPACT:1777 - \r
4514    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
4515 \r
4516 ----------------------------------------------------------------------\r\r
4517 ----------------------------------------------------------------------\r\r
4518 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
4519 ----------------------------------------------------------------------\r\r
4520 ----------------------------------------------------------------------\r\r
4521 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
4522 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
4523 INFO:iMPACT:1777 - \r
4524    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
4525 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
4526 \r
4527 INFO:iMPACT:1777 - \r
4528    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
4529 \r
4530 ----------------------------------------------------------------------\r\r
4531 ----------------------------------------------------------------------\r\r
4532 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4533 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
4534 \r
4535 ----------------------------------------------------------------------\r\r
4536 ----------------------------------------------------------------------\r\r
4537 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4538 ----------------------------------------------------------------------\r\r
4539 ----------------------------------------------------------------------\r\r
4540 done.\r\r
4541 Elapsed time =      1 sec.\r\r
4542 Elapsed time =      0 sec.\r\r
4543 '5': Loading file 'implementation/download.bit' ...\r\r
4544 INFO:iMPACT:1777 - \r
4545    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
4546 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4547 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4548 \r
4549 done.\r\r
4550 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
4551 ----------------------------------------------------------------------\r\r
4552 ----------------------------------------------------------------------\r\r
4553 ----------------------------------------------------------------------\r\r
4554 Maximum TCK operating frequency for this device chain: 10000000.\r\r
4555 Validating chain...\r\r
4556 Boundary-scan chain validated successfully.\r\r
4557 5: Device Temperature: Current Reading:   33.15 C, Min. Reading:   30.69 C, Max.\r\r
4558 Reading:   33.64 C\r\r
4559 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.\r\r
4560 Reading:   1.002 V\r\r
4561 5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.\r\r
4562 Reading:   2.508 V\r\r
4563 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
4564 \r
4565 '5': Programming device...\r\r
4566  Match_cycle = 2.\r\r
4567 done.\r\r
4568 '5': Reading status register contents...\r\r
4569 CRC error                                         :         0\r\r
4570 Decryptor security set                            :         0\r\r
4571 DCM locked                                        :         1\r\r
4572 DCI matched                                       :         1\r\r
4573 End of startup signal from Startup block          :         1\r\r
4574 status of GTS_CFG_B                               :         1\r\r
4575 status of GWE                                     :         1\r\r
4576 status of GHIGH                                   :         1\r\r
4577 value of MODE pin M0                              :         1\r\r
4578 value of MODE pin M1                              :         0\r\r
4579 Value of MODE pin M2                              :         1\r\r
4580 Internal signal indicates when housecleaning is completed:         1\r\r
4581 Value driver in from INIT pad                     :         1\r\r
4582 Internal signal indicates that chip is configured :         1\r\r
4583 Value of DONE pin                                 :         1\r\r
4584 Indicates when ID value written does not match chip ID:         0\r\r
4585 Decryptor error Signal                            :         0\r\r
4586 System Monitor Over-Temperature Alarm             :         0\r\r
4587 startup_state[18] CFG startup state machine       :         0\r\r
4588 startup_state[19] CFG startup state machine       :         0\r\r
4589 startup_state[20] CFG startup state machine       :         1\r\r
4590 E-fuse program voltage available                  :         0\r\r
4591 SPI Flash Type[22] Select                         :         1\r\r
4592 SPI Flash Type[23] Select                         :         1\r\r
4593 SPI Flash Type[24] Select                         :         1\r\r
4594 CFG bus width auto detection result               :         0\r\r
4595 CFG bus width auto detection result               :         0\r\r
4596 Reserved                                          :         0\r\r
4597 BPI address wrap around error                     :         0\r\r
4598 IPROG pulsed                                      :         0\r\r
4599 read back crc error                               :         0\r\r
4600 Indicates that efuse logic is busy                :         0\r\r
4601  Match_cycle = 2.\r\r
4602 '5': Programmed successfully.\r\r
4603 Elapsed time =     11 sec.\r\r
4604 ----------------------------------------------------------------------\r\r
4605 ----------------------------------------------------------------------\r\r
4606 ----------------------------------------------------------------------\r\r
4607 ----------------------------------------------------------------------\r\r
4608 ----------------------------------------------------------------------\r\r
4609 ----------------------------------------------------------------------\r\r
4610 ----------------------------------------------------------------------\r\r
4611 ----------------------------------------------------------------------\r\r
4612 INFO:iMPACT:2219 - Status register values:\r
4613 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
4614 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
4615 INFO:iMPACT - '5': Programing completed successfully.\r
4616 INFO:iMPACT - '5': Checking done pin....done.\r
4617 \r
4618 \r
4619 \r
4620 Done!
4621 \r
4622 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4623 \r
4624 Done.
4625 \r
4626 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4627 \r
4628 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4629 \r
4630 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4631 \r
4632 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4633 \r
4634 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4635 \r
4636 Done.
4637 \r
4638 Done.
4639 \r
4640 Done.
4641 \r
4642 Done.
4643 \r
4644 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4645 \r
4646 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4647 \r
4648 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4649 \r
4650 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4651 \r
4652 Done.
4653 \r
4654 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4655 \r
4656 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4657 \r
4658 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4659 \r
4660 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4661 \r
4662 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4663 \r
4664 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4665 \r
4666 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4667 \r
4668 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4669 \r
4670 Done.
4671 \r
4672 Done.
4673 \r
4674 Done.
4675 \r
4676 Writing filter settings....
4677 \r
4678 Done writing filter settings to:
4679         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
4680 \r
4681 Done writing Tab View settings to:
4682         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
4683 \r
4684 Xilinx Platform Studio (XPS)\r
4685 Xilinx EDK 11.2 Build EDK_LS3.47
4686 \r
4687 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4688 \r
4689 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
4690 \r
4691 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
4692 \r
4693 Generating Block Diagram to Buffer
4694 \r
4695 Generated Block Diagram SVG
4696 \r
4697 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4698 \r
4699 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4700 \r
4701 Done.
4702 \r
4703 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4704 \r
4705 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4706 \r
4707 Writing filter settings....
4708 \r
4709 Done writing filter settings to:
4710         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
4711 \r
4712 Done writing Tab View settings to:
4713         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
4714 \r
4715 Xilinx Platform Studio (XPS)\r
4716 Xilinx EDK 11.2 Build EDK_LS3.47
4717 \r
4718 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4719 \r
4720 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
4721 \r
4722 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
4723 \r
4724 Generating Block Diagram to Buffer
4725 \r
4726 Generated Block Diagram SVG
4727 \r
4728 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4729 \r
4730 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4731 \r
4732 Done.
4733 \r
4734 Writing filter settings....
4735 \r
4736 Done writing filter settings to:
4737         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
4738 \r
4739 Done writing Tab View settings to:
4740         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
4741 \r
4742 Xilinx Platform Studio (XPS)\r
4743 Xilinx EDK 11.2 Build EDK_LS3.47
4744 \r
4745 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4746 \r
4747 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
4748 \r
4749 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
4750 \r
4751 Generating Block Diagram to Buffer
4752 \r
4753 Generated Block Diagram SVG
4754 \r
4755 At Local date and time: Wed Jul 01 17:11:24 2009
4756  make -f system.make download started...
4757 \r
4758 *********************************************\r
4759 Downloading Bitstream onto the target board\r
4760 *********************************************\r
4761 impact -batch etc/download.cmd\r
4762 Release 11.2 - iMPACT L.46 (nt)\r\r
4763 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4764 Preference Table\r\r
4765 Name                 Setting             \r\r
4766 StartupClock         Auto_Correction     \r\r
4767 AutoSignature        False               \r\r
4768 KeepSVF              False               \r\r
4769 ConcurrentMode       False               \r\r
4770 UseHighz             False               \r\r
4771 ConfigOnFailure      Stop                \r\r
4772 UserLevel            Novice              \r\r
4773 MessageLevel         Detailed            \r\r
4774 svfUseTime           false               \r\r
4775 SpiByteSwap          Auto_Correction     \r\r
4776 AutoDetecting cable. Please wait.\r\r
4777 Connecting to cable (Usb Port - USB21).\r\r
4778 Checking cable driver.\r\r
4779  Driver file xusb_xp2.sys found.\r\r
4780  Driver version: src=2301, dest=2301.\r\r
4781  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
4782 13:58:07, version = 900.\r\r
4783  Cable PID = 0008.\r\r
4784  Max current requested during enumeration is 150 mA.\r\r
4785 Type = 0x0005.\r\r
4786  Cable Type = 3, Revision = 0.\r\r
4787  Setting cable speed to 6 MHz.\r\r
4788 Cable connection established.\r\r
4789 Firmware version = 2401.\r\r
4790 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
4791 Firmware hex file version = 2401.\r\r
4792 PLD file version = 200Dh.\r\r
4793  PLD version = 200Dh.\r\r
4794 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
4795 INFO:iMPACT:1777 - \r
4796    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
4797 \r
4798 ----------------------------------------------------------------------\r\r
4799 ----------------------------------------------------------------------\r\r
4800 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
4801 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
4802 INFO:iMPACT:1777 - \r
4803    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
4804 \r
4805 ----------------------------------------------------------------------\r\r
4806 ----------------------------------------------------------------------\r\r
4807 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
4808 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
4809 \r
4810 INFO:iMPACT:1777 - \r
4811    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
4812 \r
4813 ----------------------------------------------------------------------\r\r
4814 ----------------------------------------------------------------------\r\r
4815 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4816 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
4817 \r
4818 INFO:iMPACT:1777 - \r
4819    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
4820 \r
4821 ----------------------------------------------------------------------\r\r
4822 ----------------------------------------------------------------------\r\r
4823 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4824 ----------------------------------------------------------------------\r\r
4825 ----------------------------------------------------------------------\r\r
4826 done.\r\r
4827 Elapsed time =      3 sec.\r\r
4828 Elapsed time =      0 sec.\r\r
4829 '5': Loading file 'implementation/download.bit' ...\r\r
4830 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4831 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4832 \r
4833 done.\r\r
4834 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
4835 ----------------------------------------------------------------------\r\r
4836 ----------------------------------------------------------------------\r\r
4837 ----------------------------------------------------------------------\r\r
4838 Maximum TCK operating frequency for this device chain: 10000000.\r\r
4839 Validating chain...\r\r
4840 Boundary-scan chain validated successfully.\r\r
4841 5: Device Temperature: Current Reading:   42.99 C, Min. Reading:   34.13 C, Max.\r\r
4842 Reading:   42.99 C\r\r
4843 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.\r\r
4844 Reading:   1.002 V\r\r
4845 5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.\r\r
4846 Reading:   2.505 V\r\r
4847 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
4848 \r
4849 '5': Programming device...\r\r
4850  Match_cycle = 2.\r\r
4851 done.\r\r
4852 '5': Reading status register contents...\r\r
4853 CRC error                                         :         0\r\r
4854 Decryptor security set                            :         0\r\r
4855 DCM locked                                        :         1\r\r
4856 DCI matched                                       :         1\r\r
4857 End of startup signal from Startup block          :         1\r\r
4858 status of GTS_CFG_B                               :         1\r\r
4859 status of GWE                                     :         1\r\r
4860 status of GHIGH                                   :         1\r\r
4861 value of MODE pin M0                              :         1\r\r
4862 value of MODE pin M1                              :         0\r\r
4863 Value of MODE pin M2                              :         1\r\r
4864 Internal signal indicates when housecleaning is completed:         1\r\r
4865 Value driver in from INIT pad                     :         1\r\r
4866 Internal signal indicates that chip is configured :         1\r\r
4867 Value of DONE pin                                 :         1\r\r
4868 Indicates when ID value written does not match chip ID:         0\r\r
4869 Decryptor error Signal                            :         0\r\r
4870 System Monitor Over-Temperature Alarm             :         0\r\r
4871 startup_state[18] CFG startup state machine       :         0\r\r
4872 startup_state[19] CFG startup state machine       :         0\r\r
4873 startup_state[20] CFG startup state machine       :         1\r\r
4874 E-fuse program voltage available                  :         0\r\r
4875 SPI Flash Type[22] Select                         :         1\r\r
4876 SPI Flash Type[23] Select                         :         1\r\r
4877 SPI Flash Type[24] Select                         :         1\r\r
4878 CFG bus width auto detection result               :         0\r\r
4879 CFG bus width auto detection result               :         0\r\r
4880 Reserved                                          :         0\r\r
4881 BPI address wrap around error                     :         0\r\r
4882 IPROG pulsed                                      :         0\r\r
4883 read back crc error                               :         0\r\r
4884 Indicates that efuse logic is busy                :         0\r\r
4885  Match_cycle = 2.\r\r
4886 '5': Programmed successfully.\r\r
4887 Elapsed time =     12 sec.\r\r
4888 ----------------------------------------------------------------------\r\r
4889 ----------------------------------------------------------------------\r\r
4890 ----------------------------------------------------------------------\r\r
4891 ----------------------------------------------------------------------\r\r
4892 ----------------------------------------------------------------------\r\r
4893 ----------------------------------------------------------------------\r\r
4894 INFO:iMPACT:2219 - Status register values:\r
4895 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
4896 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
4897 INFO:iMPACT - '5': Programing completed successfully.\r
4898 INFO:iMPACT - '5': Checking done pin....done.\r
4899 \r
4900 ----------------------------------------------------------------------\r\r
4901 ----------------------------------------------------------------------\r\r
4902 \r
4903 \r
4904 Done!
4905 \r
4906 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4907 \r
4908 Done.
4909 \r
4910 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4911 \r
4912 Done.
4913 \r
4914 At Local date and time: Wed Jul 01 17:17:34 2009
4915  make -f system.make download started...
4916 \r
4917 *********************************************\r
4918 Downloading Bitstream onto the target board\r
4919 *********************************************\r
4920 impact -batch etc/download.cmd\r
4921 Release 11.2 - iMPACT L.46 (nt)\r\r
4922 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4923 Preference Table\r\r
4924 Name                 Setting             \r\r
4925 StartupClock         Auto_Correction     \r\r
4926 AutoSignature        False               \r\r
4927 KeepSVF              False               \r\r
4928 ConcurrentMode       False               \r\r
4929 UseHighz             False               \r\r
4930 ConfigOnFailure      Stop                \r\r
4931 UserLevel            Novice              \r\r
4932 MessageLevel         Detailed            \r\r
4933 svfUseTime           false               \r\r
4934 SpiByteSwap          Auto_Correction     \r\r
4935 AutoDetecting cable. Please wait.\r\r
4936 Connecting to cable (Usb Port - USB21).\r\r
4937 Checking cable driver.\r\r
4938  Driver file xusb_xp2.sys found.\r\r
4939  Driver version: src=2301, dest=2301.\r\r
4940  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
4941 13:58:07, version = 900.\r\r
4942  Cable PID = 0008.\r\r
4943  Max current requested during enumeration is 150 mA.\r\r
4944 Type = 0x0005.\r\r
4945  Cable Type = 3, Revision = 0.\r\r
4946  Setting cable speed to 6 MHz.\r\r
4947 Cable connection established.\r\r
4948 Firmware version = 2401.\r\r
4949 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
4950 Firmware hex file version = 2401.\r\r
4951 PLD file version = 200Dh.\r\r
4952  PLD version = 200Dh.\r\r
4953 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
4954 INFO:iMPACT:1777 - \r
4955    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
4956 \r
4957 ----------------------------------------------------------------------\r\r
4958 ----------------------------------------------------------------------\r\r
4959 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
4960 ----------------------------------------------------------------------\r\r
4961 ----------------------------------------------------------------------\r\r
4962 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
4963 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
4964 INFO:iMPACT:1777 - \r
4965    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
4966 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
4967 \r
4968 ----------------------------------------------------------------------\r\r
4969 ----------------------------------------------------------------------\r\r
4970 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4971 ----------------------------------------------------------------------\r\r
4972 ----------------------------------------------------------------------\r\r
4973 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4974 ----------------------------------------------------------------------\r\r
4975 ----------------------------------------------------------------------\r\r
4976 done.\r\r
4977 Elapsed time =      0 sec.\r\r
4978 Elapsed time =      0 sec.\r\r
4979 '5': Loading file 'implementation/download.bit' ...\r\r
4980 INFO:iMPACT:1777 - \r
4981    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
4982 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
4983 INFO:iMPACT:1777 - \r
4984    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
4985 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4986 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4987 \r
4988 done.\r\r
4989 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
4990 ----------------------------------------------------------------------\r\r
4991 ----------------------------------------------------------------------\r\r
4992 ----------------------------------------------------------------------\r\r
4993 Maximum TCK operating frequency for this device chain: 10000000.\r\r
4994 Validating chain...\r\r
4995 Boundary-scan chain validated successfully.\r\r
4996 5: Device Temperature: Current Reading:   62.68 C, Min. Reading:   62.68 C, Max.\r\r
4997 Reading:   66.13 C\r\r
4998 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.996 V, Max.\r\r
4999 Reading:   0.999 V\r\r
5000 5: VCCAUX Supply: Current Reading:   2.502 V, Min. Reading:   2.502 V, Max.\r\r
5001 Reading:   2.505 V\r\r
5002 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
5003 \r
5004 '5': Programming device...\r\r
5005  Match_cycle = 2.\r\r
5006 done.\r\r
5007 '5': Reading status register contents...\r\r
5008 CRC error                                         :         0\r\r
5009 Decryptor security set                            :         0\r\r
5010 DCM locked                                        :         1\r\r
5011 DCI matched                                       :         1\r\r
5012 End of startup signal from Startup block          :         1\r\r
5013 status of GTS_CFG_B                               :         1\r\r
5014 status of GWE                                     :         1\r\r
5015 status of GHIGH                                   :         1\r\r
5016 value of MODE pin M0                              :         1\r\r
5017 value of MODE pin M1                              :         0\r\r
5018 Value of MODE pin M2                              :         1\r\r
5019 Internal signal indicates when housecleaning is completed:         1\r\r
5020 Value driver in from INIT pad                     :         1\r\r
5021 Internal signal indicates that chip is configured :         1\r\r
5022 Value of DONE pin                                 :         1\r\r
5023 Indicates when ID value written does not match chip ID:         0\r\r
5024 Decryptor error Signal                            :         0\r\r
5025 System Monitor Over-Temperature Alarm             :         0\r\r
5026 startup_state[18] CFG startup state machine       :         0\r\r
5027 startup_state[19] CFG startup state machine       :         0\r\r
5028 startup_state[20] CFG startup state machine       :         1\r\r
5029 E-fuse program voltage available                  :         0\r\r
5030 SPI Flash Type[22] Select                         :         1\r\r
5031 SPI Flash Type[23] Select                         :         1\r\r
5032 SPI Flash Type[24] Select                         :         1\r\r
5033 CFG bus width auto detection result               :         0\r\r
5034 CFG bus width auto detection result               :         0\r\r
5035 Reserved                                          :         0\r\r
5036 BPI address wrap around error                     :         0\r\r
5037 IPROG pulsed                                      :         0\r\r
5038 read back crc error                               :         0\r\r
5039 Indicates that efuse logic is busy                :         0\r\r
5040  Match_cycle = 2.\r\r
5041 '5': Programmed successfully.\r\r
5042 Elapsed time =     11 sec.\r\r
5043 ----------------------------------------------------------------------\r\r
5044 ----------------------------------------------------------------------\r\r
5045 ----------------------------------------------------------------------\r\r
5046 ----------------------------------------------------------------------\r\r
5047 ----------------------------------------------------------------------\r\r
5048 ----------------------------------------------------------------------\r\r
5049 ----------------------------------------------------------------------\r\r
5050 ----------------------------------------------------------------------\r\r
5051 INFO:iMPACT:2219 - Status register values:\r
5052 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
5053 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
5054 INFO:iMPACT - '5': Programing completed successfully.\r
5055 INFO:iMPACT - '5': Checking done pin....done.\r
5056 \r
5057 \r
5058 \r
5059 Done!
5060 \r
5061 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5062 \r
5063 Done.
5064 \r
5065 Done.
5066 \r
5067 Done.
5068 \r
5069 Done.
5070 \r
5071 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5072 \r
5073 Writing filter settings....
5074 \r
5075 Done writing filter settings to:
5076         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
5077 \r
5078 Done writing Tab View settings to:
5079         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
5080 \r
5081 Xilinx Platform Studio (XPS)\r
5082 Xilinx EDK 11.2 Build EDK_LS3.47
5083 \r
5084 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
5085 \r
5086 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
5087 \r
5088 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
5089 \r
5090 Generating Block Diagram to Buffer
5091 \r
5092 Generated Block Diagram SVG
5093 \r
5094 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5095 \r
5096 Writing filter settings....
5097 \r
5098 Done writing filter settings to:
5099         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
5100 \r
5101 Done writing Tab View settings to:
5102         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
5103 \r
5104 Xilinx Platform Studio (XPS)\r
5105 Xilinx EDK 11.2 Build EDK_LS3.47
5106 \r
5107 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
5108 \r
5109 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
5110 \r
5111 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
5112 \r
5113 Generating Block Diagram to Buffer
5114 \r
5115 Generated Block Diagram SVG
5116 \r
5117 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5118 \r
5119 At Local date and time: Wed Jul 01 18:45:58 2009
5120  make -f system.make download started...
5121 \r
5122 *********************************************\r
5123 Downloading Bitstream onto the target board\r
5124 *********************************************\r
5125 impact -batch etc/download.cmd\r
5126 Release 11.2 - iMPACT L.46 (nt)\r\r
5127 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
5128 Preference Table\r\r
5129 Name                 Setting             \r\r
5130 StartupClock         Auto_Correction     \r\r
5131 AutoSignature        False               \r\r
5132 KeepSVF              False               \r\r
5133 ConcurrentMode       False               \r\r
5134 UseHighz             False               \r\r
5135 ConfigOnFailure      Stop                \r\r
5136 UserLevel            Novice              \r\r
5137 MessageLevel         Detailed            \r\r
5138 svfUseTime           false               \r\r
5139 SpiByteSwap          Auto_Correction     \r\r
5140 AutoDetecting cable. Please wait.\r\r
5141 Connecting to cable (Usb Port - USB21).\r\r
5142 Checking cable driver.\r\r
5143  Driver file xusb_xp2.sys found.\r\r
5144  Driver version: src=2301, dest=2301.\r\r
5145  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
5146 13:58:07, version = 900.\r\r
5147  Cable PID = 0008.\r\r
5148  Max current requested during enumeration is 300 mA.\r\r
5149 Type = 0x0005.\r\r
5150  Cable Type = 3, Revision = 0.\r\r
5151  Setting cable speed to 6 MHz.\r\r
5152 Cable connection established.\r\r
5153 Firmware version = 2401.\r\r
5154 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
5155 Firmware hex file version = 2401.\r\r
5156 PLD file version = 200Dh.\r\r
5157  PLD version = 200Dh.\r\r
5158 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
5159 INFO:iMPACT:1777 - \r
5160    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
5161 \r
5162 ----------------------------------------------------------------------\r\r
5163 ----------------------------------------------------------------------\r\r
5164 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
5165 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
5166 \r
5167 INFO:iMPACT:1777 - \r
5168    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
5169 \r
5170 ----------------------------------------------------------------------\r\r
5171 ----------------------------------------------------------------------\r\r
5172 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
5173 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
5174 \r
5175 INFO:iMPACT:1777 - \r
5176    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
5177 \r
5178 ----------------------------------------------------------------------\r\r
5179 ----------------------------------------------------------------------\r\r
5180 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5181 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
5182 \r
5183 INFO:iMPACT:1777 - \r
5184    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
5185 \r
5186 ----------------------------------------------------------------------\r\r
5187 ----------------------------------------------------------------------\r\r
5188 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5189 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5190 \r
5191 ----------------------------------------------------------------------\r\r
5192 ----------------------------------------------------------------------\r\r
5193 done.\r\r
5194 Elapsed time =      3 sec.\r\r
5195 Elapsed time =      0 sec.\r\r
5196 '5': Loading file 'implementation/download.bit' ...\r\r
5197 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5198 \r
5199 done.\r\r
5200 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
5201 ----------------------------------------------------------------------\r\r
5202 ----------------------------------------------------------------------\r\r
5203 ----------------------------------------------------------------------\r\r
5204 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
5205 \r
5206 Maximum TCK operating frequency for this device chain: 10000000.\r\r
5207 Validating chain...\r\r
5208 Boundary-scan chain validated successfully.\r\r
5209 5: Device Temperature: Current Reading:   42.99 C, Min. Reading:   37.58 C, Max.\r\r
5210 Reading:   42.99 C\r\r
5211 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.\r\r
5212 Reading:   0.999 V\r\r
5213 5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.\r\r
5214 Reading:   2.505 V\r\r
5215 '5': Programming device...\r\r
5216  Match_cycle = 2.\r\r
5217 done.\r\r
5218 '5': Reading status register contents...\r\r
5219 CRC error                                         :         0\r\r
5220 Decryptor security set                            :         0\r\r
5221 DCM locked                                        :         1\r\r
5222 DCI matched                                       :         1\r\r
5223 End of startup signal from Startup block          :         1\r\r
5224 status of GTS_CFG_B                               :         1\r\r
5225 status of GWE                                     :         1\r\r
5226 status of GHIGH                                   :         1\r\r
5227 value of MODE pin M0                              :         1\r\r
5228 value of MODE pin M1                              :         0\r\r
5229 Value of MODE pin M2                              :         1\r\r
5230 Internal signal indicates when housecleaning is completed:         1\r\r
5231 Value driver in from INIT pad                     :         1\r\r
5232 Internal signal indicates that chip is configured :         1\r\r
5233 Value of DONE pin                                 :         1\r\r
5234 Indicates when ID value written does not match chip ID:         0\r\r
5235 Decryptor error Signal                            :         0\r\r
5236 System Monitor Over-Temperature Alarm             :         0\r\r
5237 startup_state[18] CFG startup state machine       :         0\r\r
5238 startup_state[19] CFG startup state machine       :         0\r\r
5239 startup_state[20] CFG startup state machine       :         1\r\r
5240 E-fuse program voltage available                  :         0\r\r
5241 SPI Flash Type[22] Select                         :         1\r\r
5242 SPI Flash Type[23] Select                         :         1\r\r
5243 SPI Flash Type[24] Select                         :         1\r\r
5244 CFG bus width auto detection result               :         0\r\r
5245 CFG bus width auto detection result               :         0\r\r
5246 Reserved                                          :         0\r\r
5247 BPI address wrap around error                     :         0\r\r
5248 IPROG pulsed                                      :         0\r\r
5249 read back crc error                               :         0\r\r
5250 Indicates that efuse logic is busy                :         0\r\r
5251  Match_cycle = 2.\r\r
5252 '5': Programmed successfully.\r\r
5253 Elapsed time =     11 sec.\r\r
5254 ----------------------------------------------------------------------\r\r
5255 ----------------------------------------------------------------------\r\r
5256 ----------------------------------------------------------------------\r\r
5257 ----------------------------------------------------------------------\r\r
5258 ----------------------------------------------------------------------\r\r
5259 ----------------------------------------------------------------------\r\r
5260 ----------------------------------------------------------------------\r\r
5261 ----------------------------------------------------------------------\r\r
5262 INFO:iMPACT:2219 - Status register values:\r
5263 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
5264 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
5265 INFO:iMPACT - '5': Programing completed successfully.\r
5266 INFO:iMPACT - '5': Checking done pin....done.\r
5267 \r
5268 \r
5269 \r
5270 Done!
5271 \r
5272 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5273 \r
5274 Done.
5275 \r
5276 Writing filter settings....
5277 \r
5278 Done writing filter settings to:
5279         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
5280 \r
5281 Done writing Tab View settings to:
5282         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
5283 \r
5284 Xilinx Platform Studio (XPS)\r
5285 Xilinx EDK 11.2 Build EDK_LS3.47
5286 \r
5287 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
5288 \r
5289 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
5290 \r
5291 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
5292 \r
5293 Generating Block Diagram to Buffer
5294 \r
5295 Generated Block Diagram SVG
5296 \r
5297 At Local date and time: Thu Jul 02 09:58:07 2009
5298  make -f system.make program started...
5299 \r
5300 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5301     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5302 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5303 powerpc-eabi-size RTOSDemo/executable.elf \r
5304    text    data     bss     dec     hex filename\r
5305   51202     372   87844  139418   2209a RTOSDemo/executable.elf\r
5306 \r
5307 \r
5308 Done!
5309 \r
5310 At Local date and time: Thu Jul 02 09:58:40 2009
5311  make -f system.make download started...
5312 \r
5313 *********************************************\r
5314 Downloading Bitstream onto the target board\r
5315 *********************************************\r
5316 impact -batch etc/download.cmd\r
5317 Release 11.2 - iMPACT L.46 (nt)\r\r
5318 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
5319 Preference Table\r\r
5320 Name                 Setting             \r\r
5321 StartupClock         Auto_Correction     \r\r
5322 AutoSignature        False               \r\r
5323 KeepSVF              False               \r\r
5324 ConcurrentMode       False               \r\r
5325 UseHighz             False               \r\r
5326 ConfigOnFailure      Stop                \r\r
5327 UserLevel            Novice              \r\r
5328 MessageLevel         Detailed            \r\r
5329 svfUseTime           false               \r\r
5330 SpiByteSwap          Auto_Correction     \r\r
5331 AutoDetecting cable. Please wait.\r\r
5332 Connecting to cable (Usb Port - USB21).\r\r
5333 Checking cable driver.\r\r
5334  Driver file xusb_xp2.sys found.\r\r
5335  Driver version: src=2301, dest=2301.\r\r
5336  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
5337 13:58:07, version = 900.\r\r
5338  Cable PID = 0008.\r\r
5339  Max current requested during enumeration is 300 mA.\r\r
5340 Type = 0x0005.\r\r
5341 write (count, cmdBuffer, dataBuffer) failed C0000004.\r\r
5342  Cable Type = 3, Revision = 0.\r\r
5343  Setting cable speed to 6 MHz.\r\r
5344 Cable connection established.\r\r
5345 Firmware version = 2301.\r\r
5346 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
5347 Firmware hex file version = 2401.\r\r
5348 Downloading c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex.\r\r
5349 Downloaded firmware version = 2401.\r\r
5350 PLD file version = 200Dh.\r\r
5351  PLD version = 200Dh.\r\r
5352 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
5353 INFO:iMPACT:1777 - \r
5354    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
5355 \r
5356 ----------------------------------------------------------------------\r\r
5357 ----------------------------------------------------------------------\r\r
5358 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
5359 ----------------------------------------------------------------------\r\r
5360 ----------------------------------------------------------------------\r\r
5361 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
5362 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
5363 INFO:iMPACT:1777 - \r
5364    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
5365 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
5366 \r
5367 ----------------------------------------------------------------------\r\r
5368 ----------------------------------------------------------------------\r\r
5369 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5370 INFO:iMPACT:1777 - \r
5371    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
5372 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
5373 \r
5374 ----------------------------------------------------------------------\r\r
5375 ----------------------------------------------------------------------\r\r
5376 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5377 ----------------------------------------------------------------------\r\r
5378 ----------------------------------------------------------------------\r\r
5379 done.\r\r
5380 Elapsed time =      2 sec.\r\r
5381 Elapsed time =      0 sec.\r\r
5382 '5': Loading file 'implementation/download.bit' ...\r\r
5383 INFO:iMPACT:1777 - \r
5384    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
5385 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5386 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5387 \r
5388 done.\r\r
5389 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
5390 ----------------------------------------------------------------------\r\r
5391 ----------------------------------------------------------------------\r\r
5392 ----------------------------------------------------------------------\r\r
5393 Maximum TCK operating frequency for this device chain: 10000000.\r\r
5394 Validating chain...\r\r
5395 Boundary-scan chain validated successfully.\r\r
5396 5: Device Temperature: Current Reading:   32.16 C, Min. Reading:   30.20 C, Max.\r\r
5397 Reading:   32.66 C\r\r
5398 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.\r\r
5399 Reading:   1.002 V\r\r
5400 5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.505 V, Max.\r\r
5401 Reading:   2.508 V\r\r
5402 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
5403 \r
5404 '5': Programming device...\r\r
5405  Match_cycle = 2.\r\r
5406 done.\r\r
5407 '5': Reading status register contents...\r\r
5408 CRC error                                         :         0\r\r
5409 Decryptor security set                            :         0\r\r
5410 DCM locked                                        :         1\r\r
5411 DCI matched                                       :         1\r\r
5412 End of startup signal from Startup block          :         1\r\r
5413 status of GTS_CFG_B                               :         1\r\r
5414 status of GWE                                     :         1\r\r
5415 status of GHIGH                                   :         1\r\r
5416 value of MODE pin M0                              :         1\r\r
5417 value of MODE pin M1                              :         0\r\r
5418 Value of MODE pin M2                              :         1\r\r
5419 Internal signal indicates when housecleaning is completed:         1\r\r
5420 Value driver in from INIT pad                     :         1\r\r
5421 Internal signal indicates that chip is configured :         1\r\r
5422 Value of DONE pin                                 :         1\r\r
5423 Indicates when ID value written does not match chip ID:         0\r\r
5424 Decryptor error Signal                            :         0\r\r
5425 System Monitor Over-Temperature Alarm             :         0\r\r
5426 startup_state[18] CFG startup state machine       :         0\r\r
5427 startup_state[19] CFG startup state machine       :         0\r\r
5428 startup_state[20] CFG startup state machine       :         1\r\r
5429 E-fuse program voltage available                  :         0\r\r
5430 SPI Flash Type[22] Select                         :         1\r\r
5431 SPI Flash Type[23] Select                         :         1\r\r
5432 SPI Flash Type[24] Select                         :         1\r\r
5433 CFG bus width auto detection result               :         0\r\r
5434 CFG bus width auto detection result               :         0\r\r
5435 Reserved                                          :         0\r\r
5436 BPI address wrap around error                     :         0\r\r
5437 IPROG pulsed                                      :         0\r\r
5438 read back crc error                               :         0\r\r
5439 Indicates that efuse logic is busy                :         0\r\r
5440  Match_cycle = 2.\r\r
5441 '5': Programmed successfully.\r\r
5442 Elapsed time =     11 sec.\r\r
5443 ----------------------------------------------------------------------\r\r
5444 ----------------------------------------------------------------------\r\r
5445 ----------------------------------------------------------------------\r\r
5446 ----------------------------------------------------------------------\r\r
5447 ----------------------------------------------------------------------\r\r
5448 ----------------------------------------------------------------------\r\r
5449 ----------------------------------------------------------------------\r\r
5450 ----------------------------------------------------------------------\r\r
5451 INFO:iMPACT:2219 - Status register values:\r
5452 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
5453 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
5454 INFO:iMPACT - '5': Programing completed successfully.\r
5455 INFO:iMPACT - '5': Checking done pin....done.\r
5456 \r
5457 \r
5458 \r
5459 Done!
5460 \r
5461 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5462 \r
5463 Done.
5464 \r
5465 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
5466 \r
5467 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
5468 \r
5469 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
5470 \r
5471 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
5472 \r
5473 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5474 \r
5475 At Local date and time: Thu Jul 02 10:23:31 2009
5476  make -f system.make program started...
5477 \r
5478 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5479     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5480 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5481 powerpc-eabi-size RTOSDemo/executable.elf \r
5482    text    data     bss     dec     hex filename\r
5483   50962     372   87844  139178   21faa RTOSDemo/executable.elf\r
5484 \r
5485 \r
5486 Done!
5487 \r
5488 Done.
5489 \r
5490 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5491 \r
5492 At Local date and time: Thu Jul 02 10:27:44 2009
5493  make -f system.make download started...
5494 \r
5495 *********************************************\r
5496 Downloading Bitstream onto the target board\r
5497 *********************************************\r
5498 impact -batch etc/download.cmd\r
5499 Release 11.2 - iMPACT L.46 (nt)\r\r
5500 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
5501 Preference Table\r\r
5502 Name                 Setting             \r\r
5503 StartupClock         Auto_Correction     \r\r
5504 AutoSignature        False               \r\r
5505 KeepSVF              False               \r\r
5506 ConcurrentMode       False               \r\r
5507 UseHighz             False               \r\r
5508 ConfigOnFailure      Stop                \r\r
5509 UserLevel            Novice              \r\r
5510 MessageLevel         Detailed            \r\r
5511 svfUseTime           false               \r\r
5512 SpiByteSwap          Auto_Correction     \r\r
5513 AutoDetecting cable. Please wait.\r\r
5514 Connecting to cable (Usb Port - USB21).\r\r
5515 Checking cable driver.\r\r
5516  Driver file xusb_xp2.sys found.\r\r
5517  Driver version: src=2301, dest=2301.\r\r
5518  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
5519 13:58:07, version = 900.\r\r
5520  Cable PID = 0008.\r\r
5521  Max current requested during enumeration is 300 mA.\r\r
5522 Type = 0x0005.\r\r
5523  Cable Type = 3, Revision = 0.\r\r
5524  Setting cable speed to 6 MHz.\r\r
5525 Cable connection established.\r\r
5526 Firmware version = 2401.\r\r
5527 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
5528 Firmware hex file version = 2401.\r\r
5529 PLD file version = 200Dh.\r\r
5530  PLD version = 200Dh.\r\r
5531 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
5532 INFO:iMPACT:1777 - \r
5533    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
5534 \r
5535 ----------------------------------------------------------------------\r\r
5536 ----------------------------------------------------------------------\r\r
5537 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
5538 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
5539 \r
5540 ----------------------------------------------------------------------\r\r
5541 ----------------------------------------------------------------------\r\r
5542 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
5543 INFO:iMPACT:1777 - \r
5544    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
5545 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
5546 \r
5547 INFO:iMPACT:1777 - \r
5548    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
5549 \r
5550 ----------------------------------------------------------------------\r\r
5551 ----------------------------------------------------------------------\r\r
5552 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5553 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
5554 INFO:iMPACT:1777 - \r
5555    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
5556 \r
5557 ----------------------------------------------------------------------\r\r
5558 ----------------------------------------------------------------------\r\r
5559 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5560 ----------------------------------------------------------------------\r\r
5561 ----------------------------------------------------------------------\r\r
5562 done.\r\r
5563 Elapsed time =      1 sec.\r\r
5564 Elapsed time =      0 sec.\r\r
5565 '5': Loading file 'implementation/download.bit' ...\r\r
5566 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5567 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5568 \r
5569 done.\r\r
5570 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
5571 ----------------------------------------------------------------------\r\r
5572 ----------------------------------------------------------------------\r\r
5573 ----------------------------------------------------------------------\r\r
5574 Maximum TCK operating frequency for this device chain: 10000000.\r\r
5575 Validating chain...\r\r
5576 Boundary-scan chain validated successfully.\r\r
5577 5: Device Temperature: Current Reading:   41.02 C, Min. Reading:   36.10 C, Max.\r\r
5578 Reading:   41.02 C\r\r
5579 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.\r\r
5580 Reading:   1.002 V\r\r
5581 5: VCCAUX Supply: Current Reading:   2.502 V, Min. Reading:   2.502 V, Max.\r\r
5582 Reading:   2.505 V\r\r
5583 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
5584 \r
5585 '5': Programming device...\r\r
5586  Match_cycle = 2.\r\r
5587 done.\r\r
5588 '5': Reading status register contents...\r\r
5589 CRC error                                         :         0\r\r
5590 Decryptor security set                            :         0\r\r
5591 DCM locked                                        :         1\r\r
5592 DCI matched                                       :         1\r\r
5593 End of startup signal from Startup block          :         1\r\r
5594 status of GTS_CFG_B                               :         1\r\r
5595 status of GWE                                     :         1\r\r
5596 status of GHIGH                                   :         1\r\r
5597 value of MODE pin M0                              :         1\r\r
5598 value of MODE pin M1                              :         0\r\r
5599 Value of MODE pin M2                              :         1\r\r
5600 Internal signal indicates when housecleaning is completed:         1\r\r
5601 Value driver in from INIT pad                     :         1\r\r
5602 Internal signal indicates that chip is configured :         1\r\r
5603 Value of DONE pin                                 :         1\r\r
5604 Indicates when ID value written does not match chip ID:         0\r\r
5605 Decryptor error Signal                            :         0\r\r
5606 System Monitor Over-Temperature Alarm             :         0\r\r
5607 startup_state[18] CFG startup state machine       :         0\r\r
5608 startup_state[19] CFG startup state machine       :         0\r\r
5609 startup_state[20] CFG startup state machine       :         1\r\r
5610 E-fuse program voltage available                  :         0\r\r
5611 SPI Flash Type[22] Select                         :         1\r\r
5612 SPI Flash Type[23] Select                         :         1\r\r
5613 SPI Flash Type[24] Select                         :         1\r\r
5614 CFG bus width auto detection result               :         0\r\r
5615 CFG bus width auto detection result               :         0\r\r
5616 Reserved                                          :         0\r\r
5617 BPI address wrap around error                     :         0\r\r
5618 IPROG pulsed                                      :         0\r\r
5619 read back crc error                               :         0\r\r
5620 Indicates that efuse logic is busy                :         0\r\r
5621  Match_cycle = 2.\r\r
5622 '5': Programmed successfully.\r\r
5623 Elapsed time =     11 sec.\r\r
5624 ----------------------------------------------------------------------\r\r
5625 ----------------------------------------------------------------------\r\r
5626 ----------------------------------------------------------------------\r\r
5627 ----------------------------------------------------------------------\r\r
5628 ----------------------------------------------------------------------\r\r
5629 ----------------------------------------------------------------------\r\r
5630 ----------------------------------------------------------------------\r\r
5631 ----------------------------------------------------------------------\r\r
5632 INFO:iMPACT:2219 - Status register values:\r
5633 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
5634 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
5635 INFO:iMPACT - '5': Programing completed successfully.\r
5636 INFO:iMPACT - '5': Checking done pin....done.\r
5637 \r
5638 \r
5639 \r
5640 Done!
5641 \r
5642 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5643 \r
5644 Done.
5645 \r
5646 At Local date and time: Thu Jul 02 11:09:53 2009
5647  make -f system.make program started...
5648 \r
5649 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5650     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5651 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5652 powerpc-eabi-size RTOSDemo/executable.elf \r
5653    text    data     bss     dec     hex filename\r
5654   51014     372   87852  139238   21fe6 RTOSDemo/executable.elf\r
5655 \r
5656 \r
5657 Done!
5658 \r
5659 Done.
5660 \r
5661 At Local date and time: Thu Jul 02 11:19:46 2009
5662  make -f system.make program started...
5663 \r
5664 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5665     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5666 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5667 powerpc-eabi-size RTOSDemo/executable.elf \r
5668    text    data     bss     dec     hex filename\r
5669   50970     372   87852  139194   21fba RTOSDemo/executable.elf\r
5670 \r
5671 \r
5672 Done!
5673 \r
5674 Done.
5675 \r
5676 At Local date and time: Thu Jul 02 11:36:56 2009
5677  make -f system.make program started...
5678 \r
5679 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5680     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5681 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5682 powerpc-eabi-size RTOSDemo/executable.elf \r
5683    text    data     bss     dec     hex filename\r
5684   50962     372   87844  139178   21faa RTOSDemo/executable.elf\r
5685 \r
5686 \r
5687 Done!
5688 \r
5689 Done.
5690 \r
5691 At Local date and time: Thu Jul 02 11:45:58 2009
5692  make -f system.make program started...
5693 \r
5694 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5695     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5696 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5697 powerpc-eabi-size RTOSDemo/executable.elf \r
5698    text    data     bss     dec     hex filename\r
5699   51002     372   87852  139226   21fda RTOSDemo/executable.elf\r
5700 \r
5701 \r
5702 Done!
5703 \r
5704 Done.
5705 \r
5706 At Local date and time: Thu Jul 02 11:50:02 2009
5707  make -f system.make program started...
5708 \r
5709 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5710     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5711 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5712 powerpc-eabi-size RTOSDemo/executable.elf \r
5713    text    data     bss     dec     hex filename\r
5714   51010     372   87860  139242   21fea RTOSDemo/executable.elf\r
5715 \r
5716 \r
5717 Done!
5718 \r
5719 Done.
5720 \r
5721 At Local date and time: Thu Jul 02 11:55:33 2009
5722  make -f system.make program started...
5723 \r
5724 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5725     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5726 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5727 powerpc-eabi-size RTOSDemo/executable.elf \r
5728    text    data     bss     dec     hex filename\r
5729   51006     372   87860  139238   21fe6 RTOSDemo/executable.elf\r
5730 \r
5731 \r
5732 Done!
5733 \r
5734 Done.
5735 \r
5736 At Local date and time: Thu Jul 02 13:28:01 2009
5737  make -f system.make program started...
5738 \r
5739 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5740     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5741 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5742 powerpc-eabi-size RTOSDemo/executable.elf \r
5743    text    data     bss     dec     hex filename\r
5744   51250     372   87860  139482   220da RTOSDemo/executable.elf\r
5745 \r
5746 \r
5747 Done!
5748 \r
5749 Done.
5750 \r
5751 At Local date and time: Thu Jul 02 13:29:26 2009
5752  make -f system.make program started...
5753 \r
5754 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
5755     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
5756 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
5757 powerpc-eabi-size RTOSDemo/executable.elf \r
5758    text    data     bss     dec     hex filename\r
5759   51242     372   87852  139466   220ca RTOSDemo/executable.elf\r
5760 \r
5761 \r
5762 Done!
5763 \r
5764 Done.
5765 \r
5766 At Local date and time: Thu Jul 02 13:31:57 2009
5767  make -f system.make download started...
5768 \r
5769 *********************************************\r
5770 Downloading Bitstream onto the target board\r
5771 *********************************************\r
5772 impact -batch etc/download.cmd\r
5773 Release 11.2 - iMPACT L.46 (nt)\r\r
5774 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
5775 Preference Table\r\r
5776 Name                 Setting             \r\r
5777 StartupClock         Auto_Correction     \r\r
5778 AutoSignature        False               \r\r
5779 KeepSVF              False               \r\r
5780 ConcurrentMode       False               \r\r
5781 UseHighz             False               \r\r
5782 ConfigOnFailure      Stop                \r\r
5783 UserLevel            Novice              \r\r
5784 MessageLevel         Detailed            \r\r
5785 svfUseTime           false               \r\r
5786 SpiByteSwap          Auto_Correction     \r\r
5787 AutoDetecting cable. Please wait.\r\r
5788 Connecting to cable (Usb Port - USB21).\r\r
5789 Checking cable driver.\r\r
5790  Driver file xusb_xp2.sys found.\r\r
5791  Driver version: src=2301, dest=2301.\r\r
5792  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
5793 13:58:07, version = 900.\r\r
5794  Cable PID = 0008.\r\r
5795  Max current requested during enumeration is 300 mA.\r\r
5796 Type = 0x0005.\r\r
5797  Cable Type = 3, Revision = 0.\r\r
5798  Setting cable speed to 6 MHz.\r\r
5799 Cable connection established.\r\r
5800 Firmware version = 2401.\r\r
5801 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
5802 Firmware hex file version = 2401.\r\r
5803 PLD file version = 200Dh.\r\r
5804  PLD version = 200Dh.\r\r
5805 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
5806 INFO:iMPACT:1777 - \r
5807    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
5808 \r
5809 ----------------------------------------------------------------------\r\r
5810 ----------------------------------------------------------------------\r\r
5811 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
5812 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
5813 \r
5814 ----------------------------------------------------------------------\r\r
5815 ----------------------------------------------------------------------\r\r
5816 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
5817 INFO:iMPACT:1777 - \r
5818    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
5819 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
5820 \r
5821 INFO:iMPACT:1777 - \r
5822    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
5823 \r
5824 ----------------------------------------------------------------------\r\r
5825 ----------------------------------------------------------------------\r\r
5826 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5827 ----------------------------------------------------------------------\r\r
5828 ----------------------------------------------------------------------\r\r
5829 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5830 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
5831 INFO:iMPACT:1777 - \r
5832    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
5833 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5834 \r
5835 ----------------------------------------------------------------------\r\r
5836 ----------------------------------------------------------------------\r\r
5837 done.\r\r
5838 Elapsed time =      1 sec.\r\r
5839 Elapsed time =      0 sec.\r\r
5840 '5': Loading file 'implementation/download.bit' ...\r\r
5841 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5842 \r
5843 done.\r\r
5844 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
5845 ----------------------------------------------------------------------\r\r
5846 ----------------------------------------------------------------------\r\r
5847 ----------------------------------------------------------------------\r\r
5848 Maximum TCK operating frequency for this device chain: 10000000.\r\r
5849 Validating chain...\r\r
5850 Boundary-scan chain validated successfully.\r\r
5851 5: Device Temperature: Current Reading:   74.00 C, Min. Reading:   41.02 C, Max.\r\r
5852 Reading:   74.49 C\r\r
5853 5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.993 V, Max.\r\r
5854 Reading:   1.002 V\r\r
5855 5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.\r\r
5856 Reading:   2.505 V\r\r
5857 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
5858 \r
5859 '5': Programming device...\r\r
5860  Match_cycle = 2.\r\r
5861 done.\r\r
5862 '5': Reading status register contents...\r\r
5863 CRC error                                         :         0\r\r
5864 Decryptor security set                            :         0\r\r
5865 DCM locked                                        :         1\r\r
5866 DCI matched                                       :         1\r\r
5867 End of startup signal from Startup block          :         1\r\r
5868 status of GTS_CFG_B                               :         1\r\r
5869 status of GWE                                     :         1\r\r
5870 status of GHIGH                                   :         1\r\r
5871 value of MODE pin M0                              :         1\r\r
5872 value of MODE pin M1                              :         0\r\r
5873 Value of MODE pin M2                              :         1\r\r
5874 Internal signal indicates when housecleaning is completed:         1\r\r
5875 Value driver in from INIT pad                     :         1\r\r
5876 Internal signal indicates that chip is configured :         1\r\r
5877 Value of DONE pin                                 :         1\r\r
5878 Indicates when ID value written does not match chip ID:         0\r\r
5879 Decryptor error Signal                            :         0\r\r
5880 System Monitor Over-Temperature Alarm             :         0\r\r
5881 startup_state[18] CFG startup state machine       :         0\r\r
5882 startup_state[19] CFG startup state machine       :         0\r\r
5883 startup_state[20] CFG startup state machine       :         1\r\r
5884 E-fuse program voltage available                  :         0\r\r
5885 SPI Flash Type[22] Select                         :         1\r\r
5886 SPI Flash Type[23] Select                         :         1\r\r
5887 SPI Flash Type[24] Select                         :         1\r\r
5888 CFG bus width auto detection result               :         0\r\r
5889 CFG bus width auto detection result               :         0\r\r
5890 Reserved                                          :         0\r\r
5891 BPI address wrap around error                     :         0\r\r
5892 IPROG pulsed                                      :         0\r\r
5893 read back crc error                               :         0\r\r
5894 Indicates that efuse logic is busy                :         0\r\r
5895  Match_cycle = 2.\r\r
5896 '5': Programmed successfully.\r\r
5897 Elapsed time =     11 sec.\r\r
5898 ----------------------------------------------------------------------\r\r
5899 ----------------------------------------------------------------------\r\r
5900 ----------------------------------------------------------------------\r\r
5901 ----------------------------------------------------------------------\r\r
5902 ----------------------------------------------------------------------\r\r
5903 ----------------------------------------------------------------------\r\r
5904 ----------------------------------------------------------------------\r\r
5905 ----------------------------------------------------------------------\r\r
5906 INFO:iMPACT:2219 - Status register values:\r
5907 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
5908 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
5909 INFO:iMPACT - '5': Programing completed successfully.\r
5910 INFO:iMPACT - '5': Checking done pin....done.\r
5911 \r
5912 \r
5913 \r
5914 Done!
5915 \r
5916 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5917 \r
5918 Done.
5919 \r
5920 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5921 \r
5922 At Local date and time: Thu Jul 02 13:35:43 2009
5923  make -f system.make download started...
5924 \r
5925 *********************************************\r
5926 Downloading Bitstream onto the target board\r
5927 *********************************************\r
5928 impact -batch etc/download.cmd\r
5929 Release 11.2 - iMPACT L.46 (nt)\r\r
5930 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
5931 Preference Table\r\r
5932 Name                 Setting             \r\r
5933 StartupClock         Auto_Correction     \r\r
5934 AutoSignature        False               \r\r
5935 KeepSVF              False               \r\r
5936 ConcurrentMode       False               \r\r
5937 UseHighz             False               \r\r
5938 ConfigOnFailure      Stop                \r\r
5939 UserLevel            Novice              \r\r
5940 MessageLevel         Detailed            \r\r
5941 svfUseTime           false               \r\r
5942 SpiByteSwap          Auto_Correction     \r\r
5943 AutoDetecting cable. Please wait.\r\r
5944 Connecting to cable (Usb Port - USB21).\r\r
5945 Checking cable driver.\r\r
5946  Driver file xusb_xp2.sys found.\r\r
5947  Driver version: src=2301, dest=2301.\r\r
5948  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
5949 13:58:07, version = 900.\r\r
5950  Cable PID = 0008.\r\r
5951  Max current requested during enumeration is 300 mA.\r\r
5952 Type = 0x0005.\r\r
5953  Cable Type = 3, Revision = 0.\r\r
5954  Setting cable speed to 6 MHz.\r\r
5955 Cable connection established.\r\r
5956 Firmware version = 2401.\r\r
5957 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
5958 Firmware hex file version = 2401.\r\r
5959 PLD file version = 200Dh.\r\r
5960  PLD version = 200Dh.\r\r
5961 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
5962 INFO:iMPACT:1777 - \r
5963    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
5964 \r
5965 ----------------------------------------------------------------------\r\r
5966 ----------------------------------------------------------------------\r\r
5967 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
5968 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
5969 \r
5970 ----------------------------------------------------------------------\r\r
5971 ----------------------------------------------------------------------\r\r
5972 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
5973 INFO:iMPACT:1777 - \r
5974    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
5975 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
5976 \r
5977 ----------------------------------------------------------------------\r\r
5978 ----------------------------------------------------------------------\r\r
5979 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5980 INFO:iMPACT:1777 - \r
5981    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
5982 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
5983 \r
5984 ----------------------------------------------------------------------\r\r
5985 ----------------------------------------------------------------------\r\r
5986 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
5987 ----------------------------------------------------------------------\r\r
5988 ----------------------------------------------------------------------\r\r
5989 done.\r\r
5990 Elapsed time =      1 sec.\r\r
5991 Elapsed time =      0 sec.\r\r
5992 '5': Loading file 'implementation/download.bit' ...\r\r
5993 INFO:iMPACT:1777 - \r
5994    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
5995 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5996 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
5997 \r
5998 done.\r\r
5999 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
6000 ----------------------------------------------------------------------\r\r
6001 ----------------------------------------------------------------------\r\r
6002 ----------------------------------------------------------------------\r\r
6003 Maximum TCK operating frequency for this device chain: 10000000.\r\r
6004 Validating chain...\r\r
6005 Boundary-scan chain validated successfully.\r\r
6006 5: Device Temperature: Current Reading:   73.02 C, Min. Reading:   70.06 C, Max.\r\r
6007 Reading:   74.00 C\r\r
6008 5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.993 V, Max.\r\r
6009 Reading:   0.999 V\r\r
6010 5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.\r\r
6011 Reading:   2.502 V\r\r
6012 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
6013 \r
6014 '5': Programming device...\r\r
6015  Match_cycle = 2.\r\r
6016 done.\r\r
6017 '5': Reading status register contents...\r\r
6018 CRC error                                         :         0\r\r
6019 Decryptor security set                            :         0\r\r
6020 DCM locked                                        :         1\r\r
6021 DCI matched                                       :         1\r\r
6022 End of startup signal from Startup block          :         1\r\r
6023 status of GTS_CFG_B                               :         1\r\r
6024 status of GWE                                     :         1\r\r
6025 status of GHIGH                                   :         1\r\r
6026 value of MODE pin M0                              :         1\r\r
6027 value of MODE pin M1                              :         0\r\r
6028 Value of MODE pin M2                              :         1\r\r
6029 Internal signal indicates when housecleaning is completed:         1\r\r
6030 Value driver in from INIT pad                     :         1\r\r
6031 Internal signal indicates that chip is configured :         1\r\r
6032 Value of DONE pin                                 :         1\r\r
6033 Indicates when ID value written does not match chip ID:         0\r\r
6034 Decryptor error Signal                            :         0\r\r
6035 System Monitor Over-Temperature Alarm             :         0\r\r
6036 startup_state[18] CFG startup state machine       :         0\r\r
6037 startup_state[19] CFG startup state machine       :         0\r\r
6038 startup_state[20] CFG startup state machine       :         1\r\r
6039 E-fuse program voltage available                  :         0\r\r
6040 SPI Flash Type[22] Select                         :         1\r\r
6041 SPI Flash Type[23] Select                         :         1\r\r
6042 SPI Flash Type[24] Select                         :         1\r\r
6043 CFG bus width auto detection result               :         0\r\r
6044 CFG bus width auto detection result               :         0\r\r
6045 Reserved                                          :         0\r\r
6046 BPI address wrap around error                     :         0\r\r
6047 IPROG pulsed                                      :         0\r\r
6048 read back crc error                               :         0\r\r
6049 Indicates that efuse logic is busy                :         0\r\r
6050  Match_cycle = 2.\r\r
6051 '5': Programmed successfully.\r\r
6052 Elapsed time =     12 sec.\r\r
6053 ----------------------------------------------------------------------\r\r
6054 ----------------------------------------------------------------------\r\r
6055 ----------------------------------------------------------------------\r\r
6056 ----------------------------------------------------------------------\r\r
6057 ----------------------------------------------------------------------\r\r
6058 ----------------------------------------------------------------------\r\r
6059 ----------------------------------------------------------------------\r\r
6060 ----------------------------------------------------------------------\r\r
6061 INFO:iMPACT:2219 - Status register values:\r
6062 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
6063 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
6064 INFO:iMPACT - '5': Programing completed successfully.\r
6065 INFO:iMPACT - '5': Checking done pin....done.\r
6066 \r
6067 \r
6068 \r
6069 Done!
6070 \r
6071 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
6072 \r
6073 At Local date and time: Thu Jul 02 13:38:54 2009
6074  make -f system.make program started...
6075 \r
6076 make: Nothing to be done for `program'.\r
6077 \r
6078 \r
6079 Done!
6080 \r
6081 At Local date and time: Thu Jul 02 13:39:15 2009
6082  make -f system.make programclean started...
6083 \r
6084 rm -f RTOSDemo/executable.elf \r
6085 \r
6086 \r
6087 Done!
6088 \r
6089 At Local date and time: Thu Jul 02 13:39:21 2009
6090  make -f system.make program started...
6091 \r
6092 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6093     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6094 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6095 powerpc-eabi-size RTOSDemo/executable.elf \r
6096    text    data     bss     dec     hex filename\r
6097   50774     372   87852  138998   21ef6 RTOSDemo/executable.elf\r
6098 \r
6099 \r
6100 Done!
6101 \r
6102 Done.
6103 \r
6104 At Local date and time: Thu Jul 02 13:52:39 2009
6105  make -f system.make program started...
6106 \r
6107 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6108     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6109 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6110 powerpc-eabi-size RTOSDemo/executable.elf \r
6111    text    data     bss     dec     hex filename\r
6112   50566     372   87852  138790   21e26 RTOSDemo/executable.elf\r
6113 \r
6114 \r
6115 Done!
6116 \r
6117 At Local date and time: Thu Jul 02 13:53:08 2009
6118  make -f system.make program started...
6119 \r
6120 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6121     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6122 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6123 powerpc-eabi-size RTOSDemo/executable.elf \r
6124    text    data     bss     dec     hex filename\r
6125   50542     372   87860  138774   21e16 RTOSDemo/executable.elf\r
6126 \r
6127 \r
6128 Done!
6129 \r
6130 Done.
6131 \r
6132 At Local date and time: Thu Jul 02 14:02:13 2009
6133  make -f system.make program started...
6134 \r
6135 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6136     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6137 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6138 powerpc-eabi-size RTOSDemo/executable.elf \r
6139    text    data     bss     dec     hex filename\r
6140   50222     372   87860  138454   21cd6 RTOSDemo/executable.elf\r
6141 \r
6142 \r
6143 Done!
6144 \r
6145 At Local date and time: Thu Jul 02 14:20:50 2009
6146  make -f system.make program started...
6147 \r
6148 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6149     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6150 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6151 powerpc-eabi-size RTOSDemo/executable.elf \r
6152    text    data     bss     dec     hex filename\r
6153   50298     372   87852  138522   21d1a RTOSDemo/executable.elf\r
6154 \r
6155 \r
6156 Done!
6157 \r
6158 At Local date and time: Thu Jul 02 15:31:05 2009
6159  make -f system.make program started...
6160 \r
6161 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6162     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6163 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6164 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c: In function 'vSecondaryBlockTimeTestTask':
6165 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: 'tskTCB' has no member named 'xEventTaskList'
6166 \r
6167 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
6168 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1542: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6169 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6170 \r
6171 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6172 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
6173 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6174 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
6175 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6176 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
6177 \r
6178 make: *** [RTOSDemo/executable.elf] Error 1
6179 \r
6180 \r
6181 \r
6182 Done!
6183 \r
6184 At Local date and time: Thu Jul 02 15:31:42 2009
6185  make -f system.make program started...
6186 \r
6187 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6188     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6189 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6190 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c: In function 'vSecondaryBlockTimeTestTask':
6191 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: 'tskTCB' has no member named 'xEventList'
6192 \r
6193 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
6194 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1542: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6195 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6196 \r
6197 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6198 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
6199 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6200 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
6201 \r
6202 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6203 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
6204 \r
6205 make: *** [RTOSDemo/executable.elf] Error 1
6206 \r
6207 \r
6208 \r
6209 Done!
6210 \r
6211 At Local date and time: Thu Jul 02 15:32:24 2009
6212  make -f system.make program started...
6213 \r
6214 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6215     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6216 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6217 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
6218 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1542: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6219 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6220 \r
6221 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6222 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
6223 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6224 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
6225 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6226 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
6227 \r
6228 powerpc-eabi-size RTOSDemo/executable.elf \r
6229    text    data     bss     dec     hex filename\r
6230   51246     372   87844  139462   220c6 RTOSDemo/executable.elf\r
6231 \r
6232 \r
6233 Done!
6234 \r
6235 At Local date and time: Thu Jul 02 15:38:48 2009
6236  make -f system.make program started...
6237 \r
6238 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6239     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6240 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6241 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
6242 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1548: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6243 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1549: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6244 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
6245 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: 'xSecondary' undeclared (first use in this function)
6246 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: (Each undeclared identifier is reported only once
6247 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: for each function it appears in.)
6248 \r
6249 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6250 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
6251 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6252 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
6253 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6254 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
6255 \r
6256 make: *** [RTOSDemo/executable.elf] Error 1
6257 \r
6258 \r
6259 \r
6260 Done!
6261 \r
6262 At Local date and time: Thu Jul 02 15:46:20 2009
6263  make -f system.make program started...
6264 \r
6265 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6266     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6267 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6268 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
6269 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1548: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6270 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1549: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6271 \r
6272 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
6273 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: 'xSecondary' undeclared (first use in this function)
6274 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: (Each undeclared identifier is reported only once
6275 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: for each function it appears in.)
6276 \r
6277 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6278 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
6279 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6280 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
6281 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6282 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
6283 \r
6284 make: *** [RTOSDemo/executable.elf] Error 1
6285 \r
6286 \r
6287 \r
6288 Done!
6289 \r
6290 At Local date and time: Thu Jul 02 15:47:05 2009
6291  make -f system.make program started...
6292 \r
6293 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6294     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6295 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6296 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
6297 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1550: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6298 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1551: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6299 \r
6300 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6301 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
6302 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6303 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
6304 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6305 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
6306 \r
6307 powerpc-eabi-size RTOSDemo/executable.elf \r
6308    text    data     bss     dec     hex filename\r
6309   51334     372   87852  139558   22126 RTOSDemo/executable.elf\r
6310 \r
6311 \r
6312 Done!
6313 \r
6314 At Local date and time: Thu Jul 02 15:48:10 2009
6315  make -f system.make download started...
6316 \r
6317 *********************************************\r
6318 Downloading Bitstream onto the target board\r
6319 *********************************************\r
6320 impact -batch etc/download.cmd\r
6321 Release 11.2 - iMPACT L.46 (nt)\r\r
6322 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
6323 Preference Table\r\r
6324 Name                 Setting             \r\r
6325 StartupClock         Auto_Correction     \r\r
6326 AutoSignature        False               \r\r
6327 KeepSVF              False               \r\r
6328 ConcurrentMode       False               \r\r
6329 UseHighz             False               \r\r
6330 ConfigOnFailure      Stop                \r\r
6331 UserLevel            Novice              \r\r
6332 MessageLevel         Detailed            \r\r
6333 svfUseTime           false               \r\r
6334 SpiByteSwap          Auto_Correction     \r\r
6335 AutoDetecting cable. Please wait.\r\r
6336 Connecting to cable (Usb Port - USB21).\r\r
6337 Checking cable driver.\r\r
6338  Driver file xusb_xp2.sys found.\r\r
6339  Driver version: src=2301, dest=2301.\r\r
6340  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
6341 13:58:07, version = 900.\r\r
6342  Cable PID = 0008.\r\r
6343  Max current requested during enumeration is 300 mA.\r\r
6344 Type = 0x0005.\r\r
6345  Cable Type = 3, Revision = 0.\r\r
6346  Setting cable speed to 6 MHz.\r\r
6347 Cable connection established.\r\r
6348 Firmware version = 2401.\r\r
6349 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
6350 Firmware hex file version = 2401.\r\r
6351 PLD file version = 200Dh.\r\r
6352  PLD version = 200Dh.\r\r
6353 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
6354 INFO:iMPACT:1777 - \r
6355    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
6356 \r
6357 ----------------------------------------------------------------------\r\r
6358 ----------------------------------------------------------------------\r\r
6359 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
6360 ----------------------------------------------------------------------\r\r
6361 ----------------------------------------------------------------------\r\r
6362 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
6363 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
6364 INFO:iMPACT:1777 - \r
6365    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
6366 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
6367 \r
6368 INFO:iMPACT:1777 - \r
6369    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
6370 \r
6371 ----------------------------------------------------------------------\r\r
6372 ----------------------------------------------------------------------\r\r
6373 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
6374 ----------------------------------------------------------------------\r\r
6375 ----------------------------------------------------------------------\r\r
6376 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
6377 ----------------------------------------------------------------------\r\r
6378 ----------------------------------------------------------------------\r\r
6379 done.\r\r
6380 Elapsed time =      0 sec.\r\r
6381 Elapsed time =      0 sec.\r\r
6382 '5': Loading file 'implementation/download.bit' ...\r\r
6383 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
6384 INFO:iMPACT:1777 - \r
6385    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
6386 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
6387 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
6388 \r
6389 done.\r\r
6390 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
6391 ----------------------------------------------------------------------\r\r
6392 ----------------------------------------------------------------------\r\r
6393 ----------------------------------------------------------------------\r\r
6394 Maximum TCK operating frequency for this device chain: 10000000.\r\r
6395 Validating chain...\r\r
6396 Boundary-scan chain validated successfully.\r\r
6397 5: Device Temperature: Current Reading:   69.08 C, Min. Reading:   66.62 C, Max.\r\r
6398 Reading:   75.48 C\r\r
6399 5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.990 V, Max.\r\r
6400 Reading:   0.999 V\r\r
6401 5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.\r\r
6402 Reading:   2.505 V\r\r
6403 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
6404 \r
6405 '5': Programming device...\r\r
6406  Match_cycle = 2.\r\r
6407 done.\r\r
6408 '5': Reading status register contents...\r\r
6409 CRC error                                         :         0\r\r
6410 Decryptor security set                            :         0\r\r
6411 DCM locked                                        :         1\r\r
6412 DCI matched                                       :         1\r\r
6413 End of startup signal from Startup block          :         1\r\r
6414 status of GTS_CFG_B                               :         1\r\r
6415 status of GWE                                     :         1\r\r
6416 status of GHIGH                                   :         1\r\r
6417 value of MODE pin M0                              :         1\r\r
6418 value of MODE pin M1                              :         0\r\r
6419 Value of MODE pin M2                              :         1\r\r
6420 Internal signal indicates when housecleaning is completed:         1\r\r
6421 Value driver in from INIT pad                     :         1\r\r
6422 Internal signal indicates that chip is configured :         1\r\r
6423 Value of DONE pin                                 :         1\r\r
6424 Indicates when ID value written does not match chip ID:         0\r\r
6425 Decryptor error Signal                            :         0\r\r
6426 System Monitor Over-Temperature Alarm             :         0\r\r
6427 startup_state[18] CFG startup state machine       :         0\r\r
6428 startup_state[19] CFG startup state machine       :         0\r\r
6429 startup_state[20] CFG startup state machine       :         1\r\r
6430 E-fuse program voltage available                  :         0\r\r
6431 SPI Flash Type[22] Select                         :         1\r\r
6432 SPI Flash Type[23] Select                         :         1\r\r
6433 SPI Flash Type[24] Select                         :         1\r\r
6434 CFG bus width auto detection result               :         0\r\r
6435 CFG bus width auto detection result               :         0\r\r
6436 Reserved                                          :         0\r\r
6437 BPI address wrap around error                     :         0\r\r
6438 IPROG pulsed                                      :         0\r\r
6439 read back crc error                               :         0\r\r
6440 Indicates that efuse logic is busy                :         0\r\r
6441  Match_cycle = 2.\r\r
6442 '5': Programmed successfully.\r\r
6443 Elapsed time =     11 sec.\r\r
6444 ----------------------------------------------------------------------\r\r
6445 ----------------------------------------------------------------------\r\r
6446 ----------------------------------------------------------------------\r\r
6447 ----------------------------------------------------------------------\r\r
6448 ----------------------------------------------------------------------\r\r
6449 ----------------------------------------------------------------------\r\r
6450 ----------------------------------------------------------------------\r\r
6451 ----------------------------------------------------------------------\r\r
6452 INFO:iMPACT:2219 - Status register values:\r
6453 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
6454 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
6455 INFO:iMPACT - '5': Programing completed successfully.\r
6456 INFO:iMPACT - '5': Checking done pin....done.\r
6457 \r
6458 \r
6459 \r
6460 Done!
6461 \r
6462 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
6463 \r
6464 At Local date and time: Thu Jul 02 15:52:34 2009
6465  make -f system.make program started...
6466 \r
6467 make: Nothing to be done for `program'.\r
6468 \r
6469 \r
6470 Done!
6471 \r
6472 At Local date and time: Thu Jul 02 15:54:04 2009
6473  make -f system.make program started...
6474 \r
6475 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6476     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6477 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6478 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c: In function 'vSecondaryBlockTimeTestTask':
6479 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: warning: dereferencing 'void *' pointer
6480 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: request for member 'xEventListItem' in something not a structure or union
6481 \r
6482 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSuspend':
6483 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: warning: dereferencing 'void *' pointer
6484 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: error: request for member 'xEventListItem' in something not a structure or union
6485 \r
6486 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
6487 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1593: error: invalid operands to binary ==
6488 \r
6489 make: *** [RTOSDemo/executable.elf] Error 1
6490 \r
6491 \r
6492 \r
6493 Done!
6494 \r
6495 At Local date and time: Thu Jul 02 15:55:43 2009
6496  make -f system.make program started...
6497 \r
6498 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6499     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6500 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6501 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSuspend':
6502 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: warning: dereferencing 'void *' pointer
6503 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: error: request for member 'xEventListItem' in something not a structure or union
6504 \r
6505 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
6506 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1593: error: invalid operands to binary ==
6507 \r
6508 make: *** [RTOSDemo/executable.elf] Error 1
6509 \r
6510 \r
6511 \r
6512 Done!
6513 \r
6514 At Local date and time: Thu Jul 02 15:57:13 2009
6515  make -f system.make program started...
6516 \r
6517 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6518     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6519 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6520 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskPlaceOnEventList':
6521 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1593: error: cannot convert to a pointer type
6522 \r
6523 make: *** [RTOSDemo/executable.elf] Error 1
6524 \r
6525 \r
6526 \r
6527 Done!
6528 \r
6529 At Local date and time: Thu Jul 02 15:58:01 2009
6530  make -f system.make program started...
6531 \r
6532 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6533     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6534 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6535 powerpc-eabi-size RTOSDemo/executable.elf \r
6536    text    data     bss     dec     hex filename\r
6537   51338     372   87852  139562   2212a RTOSDemo/executable.elf\r
6538 \r
6539 \r
6540 Done!
6541 \r
6542 Done.
6543 \r
6544 At Local date and time: Thu Jul 02 16:00:52 2009
6545  make -f system.make program started...
6546 \r
6547 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6548     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6549 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6550 powerpc-eabi-size RTOSDemo/executable.elf \r
6551    text    data     bss     dec     hex filename\r
6552   51338     372   87852  139562   2212a RTOSDemo/executable.elf\r
6553 \r
6554 \r
6555 Done!
6556 \r
6557 At Local date and time: Thu Jul 02 16:32:08 2009
6558  make -f system.make program started...
6559 \r
6560 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6561     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6562 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6563 powerpc-eabi-size RTOSDemo/executable.elf \r
6564    text    data     bss     dec     hex filename\r
6565   51878     372   87852  140102   22346 RTOSDemo/executable.elf\r
6566 \r
6567 \r
6568 Done!
6569 \r
6570 Done.
6571 \r
6572 Writing filter settings....
6573 \r
6574 Done writing filter settings to:
6575         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
6576 \r
6577 Done writing Tab View settings to:
6578         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
6579 \r
6580 Xilinx Platform Studio (XPS)\r
6581 Xilinx EDK 11.2 Build EDK_LS3.47
6582 \r
6583 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
6584 \r
6585 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
6586 \r
6587 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
6588 \r
6589 Generating Block Diagram to Buffer
6590 \r
6591 Generated Block Diagram SVG
6592 \r
6593 At Local date and time: Thu Jul 02 17:37:11 2009
6594  make -f system.make program started...
6595 \r
6596 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6597     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6598 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6599 powerpc-eabi-size RTOSDemo/executable.elf \r
6600    text    data     bss     dec     hex filename\r
6601   51910     372   87852  140134   22366 RTOSDemo/executable.elf\r
6602 \r
6603 \r
6604 Done!
6605 \r
6606 At Local date and time: Thu Jul 02 17:37:43 2009
6607  make -f system.make download started...
6608 \r
6609 *********************************************\r
6610 Downloading Bitstream onto the target board\r
6611 *********************************************\r
6612 impact -batch etc/download.cmd\r
6613 Release 11.2 - iMPACT L.46 (nt)\r\r
6614 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
6615 Preference Table\r\r
6616 Name                 Setting             \r\r
6617 StartupClock         Auto_Correction     \r\r
6618 AutoSignature        False               \r\r
6619 KeepSVF              False               \r\r
6620 ConcurrentMode       False               \r\r
6621 UseHighz             False               \r\r
6622 ConfigOnFailure      Stop                \r\r
6623 UserLevel            Novice              \r\r
6624 MessageLevel         Detailed            \r\r
6625 svfUseTime           false               \r\r
6626 SpiByteSwap          Auto_Correction     \r\r
6627 AutoDetecting cable. Please wait.\r\r
6628 Connecting to cable (Usb Port - USB21).\r\r
6629 Checking cable driver.\r\r
6630  Driver file xusb_xp2.sys found.\r\r
6631  Driver version: src=2301, dest=2301.\r\r
6632  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
6633 13:58:07, version = 900.\r\r
6634  Cable PID = 0008.\r\r
6635  Max current requested during enumeration is 300 mA.\r\r
6636 Type = 0x0005.\r\r
6637 write (count, cmdBuffer, dataBuffer) failed C0000004.\r\r
6638  Cable Type = 3, Revision = 0.\r\r
6639  Setting cable speed to 6 MHz.\r\r
6640 Cable connection established.\r\r
6641 Firmware version = 2301.\r\r
6642 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
6643 Firmware hex file version = 2401.\r\r
6644 Downloading c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex.\r\r
6645 Downloaded firmware version = 2401.\r\r
6646 PLD file version = 200Dh.\r\r
6647  PLD version = 200Dh.\r\r
6648 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
6649 INFO:iMPACT:1777 - \r
6650    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
6651 \r
6652 ----------------------------------------------------------------------\r\r
6653 ----------------------------------------------------------------------\r\r
6654 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
6655 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
6656 INFO:iMPACT:1777 - \r
6657    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
6658 \r
6659 ----------------------------------------------------------------------\r\r
6660 ----------------------------------------------------------------------\r\r
6661 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
6662 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
6663 \r
6664 INFO:iMPACT:1777 - \r
6665    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
6666 \r
6667 ----------------------------------------------------------------------\r\r
6668 ----------------------------------------------------------------------\r\r
6669 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
6670 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
6671 \r
6672 ----------------------------------------------------------------------\r\r
6673 ----------------------------------------------------------------------\r\r
6674 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
6675 ----------------------------------------------------------------------\r\r
6676 ----------------------------------------------------------------------\r\r
6677 done.\r\r
6678 Elapsed time =      2 sec.\r\r
6679 Elapsed time =      0 sec.\r\r
6680 '5': Loading file 'implementation/download.bit' ...\r\r
6681 INFO:iMPACT:1777 - \r
6682    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
6683 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
6684 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
6685 \r
6686 done.\r\r
6687 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
6688 ----------------------------------------------------------------------\r\r
6689 ----------------------------------------------------------------------\r\r
6690 ----------------------------------------------------------------------\r\r
6691 Maximum TCK operating frequency for this device chain: 10000000.\r\r
6692 Validating chain...\r\r
6693 Boundary-scan chain validated successfully.\r\r
6694 5: Device Temperature: Current Reading:   42.99 C, Min. Reading:   37.58 C, Max.\r\r
6695 Reading:   44.47 C\r\r
6696 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.\r\r
6697 Reading:   1.002 V\r\r
6698 5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.\r\r
6699 Reading:   2.508 V\r\r
6700 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
6701 \r
6702 '5': Programming device...\r\r
6703  Match_cycle = 2.\r\r
6704 done.\r\r
6705 '5': Reading status register contents...\r\r
6706 CRC error                                         :         0\r\r
6707 Decryptor security set                            :         0\r\r
6708 DCM locked                                        :         1\r\r
6709 DCI matched                                       :         1\r\r
6710 End of startup signal from Startup block          :         1\r\r
6711 status of GTS_CFG_B                               :         1\r\r
6712 status of GWE                                     :         1\r\r
6713 status of GHIGH                                   :         1\r\r
6714 value of MODE pin M0                              :         1\r\r
6715 value of MODE pin M1                              :         0\r\r
6716 Value of MODE pin M2                              :         1\r\r
6717 Internal signal indicates when housecleaning is completed:         1\r\r
6718 Value driver in from INIT pad                     :         1\r\r
6719 Internal signal indicates that chip is configured :         1\r\r
6720 Value of DONE pin                                 :         1\r\r
6721 Indicates when ID value written does not match chip ID:         0\r\r
6722 Decryptor error Signal                            :         0\r\r
6723 System Monitor Over-Temperature Alarm             :         0\r\r
6724 startup_state[18] CFG startup state machine       :         0\r\r
6725 startup_state[19] CFG startup state machine       :         0\r\r
6726 startup_state[20] CFG startup state machine       :         1\r\r
6727 E-fuse program voltage available                  :         0\r\r
6728 SPI Flash Type[22] Select                         :         1\r\r
6729 SPI Flash Type[23] Select                         :         1\r\r
6730 SPI Flash Type[24] Select                         :         1\r\r
6731 CFG bus width auto detection result               :         0\r\r
6732 CFG bus width auto detection result               :         0\r\r
6733 Reserved                                          :         0\r\r
6734 BPI address wrap around error                     :         0\r\r
6735 IPROG pulsed                                      :         0\r\r
6736 read back crc error                               :         0\r\r
6737 Indicates that efuse logic is busy                :         0\r\r
6738  Match_cycle = 2.\r\r
6739 '5': Programmed successfully.\r\r
6740 Elapsed time =     11 sec.\r\r
6741 ----------------------------------------------------------------------\r\r
6742 ----------------------------------------------------------------------\r\r
6743 ----------------------------------------------------------------------\r\r
6744 ----------------------------------------------------------------------\r\r
6745 ----------------------------------------------------------------------\r\r
6746 ----------------------------------------------------------------------\r\r
6747 ----------------------------------------------------------------------\r\r
6748 ----------------------------------------------------------------------\r\r
6749 INFO:iMPACT:2219 - Status register values:\r
6750 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
6751 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
6752 INFO:iMPACT - '5': Programing completed successfully.\r
6753 INFO:iMPACT - '5': Checking done pin....done.\r
6754 \r
6755 \r
6756 \r
6757 Done!
6758 \r
6759 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
6760 \r
6761 Done.
6762 \r
6763 At Local date and time: Thu Jul 02 18:25:53 2009
6764  make -f system.make program started...
6765 \r
6766 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6767     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6768 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6769 powerpc-eabi-size RTOSDemo/executable.elf \r
6770    text    data     bss     dec     hex filename\r
6771   51950     372   87844  140166   22386 RTOSDemo/executable.elf\r
6772 \r
6773 \r
6774 Done!
6775 \r
6776 Done.
6777 \r
6778 At Local date and time: Thu Jul 02 20:25:21 2009
6779  make -f system.make program started...
6780 \r
6781 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6782     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6783 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6784 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'xTaskCheckForTimeOut':
6785 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: error: 'xNumOfOverflows' undeclared (first use in this function)
6786 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: error: (Each undeclared identifier is reported only once
6787 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: error: for each function it appears in.)
6788 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:77: error: 'pdTRUE' undeclared (first use in this function)
6789 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:84: error: 'pdFALSE' undeclared (first use in this function)
6790 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: At top level:
6791 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:96: warning: conflicting types for 'vTaskSetTimeOutState'
6792 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:83: warning: previous implicit declaration of 'vTaskSetTimeOutState' was here
6793 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'vTaskSetTimeOutState':
6794 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:97: error: 'xNumOfOverflows' undeclared (first use in this function)
6795 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6796 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:109: warning: comparison is always true due to limited range of data type
6797 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:111: warning: comparison is always true due to limited range of data type
6798 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:116: error: expected expression before 'xTimeOutType'
6799 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:132: error: 'pdTRUE' undeclared (first use in this function)
6800 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:134: warning: incompatible implicit declaration of built-in function 'printf'
6801 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:142: warning: incompatible implicit declaration of built-in function 'printf'
6802 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:150: warning: incompatible implicit declaration of built-in function 'printf'
6803 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:103: warning: return type of 'main' is not 'int'
6804 make: *** [RTOSDemo/executable.elf] Error 1
6805 \r
6806 \r
6807 \r
6808 Done!
6809 \r
6810 At Local date and time: Thu Jul 02 20:27:35 2009
6811  make -f system.make program started...
6812 \r
6813 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6814     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6815 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6816 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:53:19: error: conio.h: No such file or directory
6817 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6818 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:113: warning: comparison is always true due to limited range of data type
6819 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:115: warning: comparison is always true due to limited range of data type
6820 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:184: warning: incompatible implicit declaration of built-in function 'exit'
6821 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:107: warning: return type of 'main' is not 'int'
6822 make: *** [RTOSDemo/executable.elf] Error 1
6823 \r
6824 \r
6825 \r
6826 Done!
6827 \r
6828 At Local date and time: Thu Jul 02 20:28:16 2009
6829  make -f system.make program started...
6830 \r
6831 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6832     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6833 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6834 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6835 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:111: warning: comparison is always true due to limited range of data type
6836 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:113: warning: comparison is always true due to limited range of data type
6837 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:136: warning: incompatible implicit declaration of built-in function 'printf'
6838 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:144: warning: incompatible implicit declaration of built-in function 'printf'
6839 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:152: warning: incompatible implicit declaration of built-in function 'printf'
6840 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:157: warning: incompatible implicit declaration of built-in function 'printf'
6841 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:176: warning: incompatible implicit declaration of built-in function 'printf'
6842 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:181: warning: incompatible implicit declaration of built-in function 'printf'
6843 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:182: warning: incompatible implicit declaration of built-in function 'exit'
6844 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:105: warning: return type of 'main' is not 'int'
6845 \r
6846 /\r
6847 cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o: In function `vTaskSetTimeOutState':
6848 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: multiple definition of `vTaskSetTimeOutState'
6849 /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o:/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1697: first defined here
6850 /cygdrive/c/devtools/Xilinx/11.1/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: Warning: size of symbol `vTaskSetTimeOutState' changed from 68 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o to 72 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o
6851 /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o: In function `xTaskCheckForTimeOut':
6852 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:77: multiple definition of `xTaskCheckForTimeOut'
6853 /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o:/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1704: first defined here
6854 /cygdrive/c/devtools/Xilinx/11.1/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: Warning: size of symbol `xTaskCheckForTimeOut' changed from 388 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o to 276 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o
6855 /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o: In function `vTaskSwitchContext':
6856 tasks.c:(.text+0x1798): undefined reference to `vApplicationStackOverflowHook'
6857 tasks.c:(.text+0x17e8): undefined reference to `vApplicationStackOverflowHook'
6858 /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o: In function `main':
6859 main.c:(.text+0x2f4): undefined reference to `kbhit'
6860 main.c:(.text+0x304): undefined reference to `getch'
6861 collect2: ld returned 1 exit status
6862 make: *** [RTOSDemo/executable.elf] Error 1
6863 \r
6864 \r
6865 \r
6866 Done!
6867 \r
6868 At Local date and time: Thu Jul 02 20:31:20 2009
6869  make -f system.make program started...
6870 \r
6871 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6872     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6873 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6874 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6875 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:117: warning: comparison is always true due to limited range of data type
6876 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6877 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:143: warning: incompatible implicit declaration of built-in function 'printf'
6878 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:105: warning: return type of 'main' is not 'int'
6879 \r
6880 /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccZOTZW1.o: In function `vTaskSwitchContext':
6881 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1556: undefined reference to `vApplicationStackOverflowHook'
6882 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1557: undefined reference to `vApplicationStackOverflowHook'
6883 collect2: ld returned 1 exit status
6884 make: *** [RTOSDemo/executable.elf] Error 1
6885 \r
6886 \r
6887 \r
6888 Done!
6889 \r
6890 At Local date and time: Thu Jul 02 20:31:50 2009
6891  make -f system.make program started...
6892 \r
6893 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6894     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6895 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6896 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6897 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6898 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
6899 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:146: warning: incompatible implicit declaration of built-in function 'printf'
6900 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6901 \r
6902 powerpc-eabi-size RTOSDemo/executable.elf \r
6903    text    data     bss     dec     hex filename\r
6904   50578     368   87832  138778   21e1a RTOSDemo/executable.elf\r
6905 \r
6906 \r
6907 Done!
6908 \r
6909 At Local date and time: Thu Jul 02 20:32:59 2009
6910  make -f system.make program started...
6911 \r
6912 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6913     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6914 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6915 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6916 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6917 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
6918 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:148: warning: incompatible implicit declaration of built-in function 'printf'
6919 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6920 \r
6921 powerpc-eabi-size RTOSDemo/executable.elf \r
6922    text    data     bss     dec     hex filename\r
6923   50706     368   87832  138906   21e9a RTOSDemo/executable.elf\r
6924 \r
6925 \r
6926 Done!
6927 \r
6928 Done.
6929 \r
6930 At Local date and time: Thu Jul 02 20:38:30 2009
6931  make -f system.make program started...
6932 \r
6933 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6934     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6935 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6936 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6937 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6938 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
6939 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:148: warning: incompatible implicit declaration of built-in function 'printf'
6940 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6941 \r
6942 powerpc-eabi-size RTOSDemo/executable.elf \r
6943    text    data     bss     dec     hex filename\r
6944   50706     368   87832  138906   21e9a RTOSDemo/executable.elf\r
6945 \r
6946 \r
6947 Done!
6948 \r
6949 At Local date and time: Thu Jul 02 20:40:24 2009
6950  make -f system.make program started...
6951 \r
6952 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6953     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6954 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6955 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6956 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6957 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
6958 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:151: warning: incompatible implicit declaration of built-in function 'printf'
6959 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6960 \r
6961 powerpc-eabi-size RTOSDemo/executable.elf \r
6962    text    data     bss     dec     hex filename\r
6963   50730     368   87840  138938   21eba RTOSDemo/executable.elf\r
6964 \r
6965 \r
6966 Done!
6967 \r
6968 Done.
6969 \r
6970 At Local date and time: Thu Jul 02 20:43:10 2009
6971  make -f system.make program started...
6972 \r
6973 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6974     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6975 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6976 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6977 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6978 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
6979 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:151: warning: incompatible implicit declaration of built-in function 'printf'
6980 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6981 \r
6982 powerpc-eabi-size RTOSDemo/executable.elf \r
6983    text    data     bss     dec     hex filename\r
6984   50730     368   87840  138938   21eba RTOSDemo/executable.elf\r
6985 \r
6986 \r
6987 Done!
6988 \r
6989 At Local date and time: Thu Jul 02 20:46:15 2009
6990  make -f system.make program started...
6991 \r
6992 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
6993     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
6994 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
6995 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6996 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6997 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
6998 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6999 \r
7000 powerpc-eabi-size RTOSDemo/executable.elf \r
7001    text    data     bss     dec     hex filename\r
7002   50694     368   87840  138902   21e96 RTOSDemo/executable.elf\r
7003 \r
7004 \r
7005 Done!
7006 \r
7007 Done.
7008 \r
7009 At Local date and time: Thu Jul 02 20:49:41 2009
7010  make -f system.make program started...
7011 \r
7012 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
7013     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
7014 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
7015 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
7016 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
7017 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
7018 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
7019 \r
7020 powerpc-eabi-size RTOSDemo/executable.elf \r
7021    text    data     bss     dec     hex filename\r
7022   50730     368   87840  138938   21eba RTOSDemo/executable.elf\r
7023 \r
7024 \r
7025 Done!
7026 \r
7027 Done.
7028 \r
7029 At Local date and time: Thu Jul 02 20:54:28 2009
7030  make -f system.make program started...
7031 \r
7032 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
7033     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
7034 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
7035 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
7036 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
7037 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
7038 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
7039 \r
7040 powerpc-eabi-size RTOSDemo/executable.elf \r
7041    text    data     bss     dec     hex filename\r
7042   50802     368   87832  139002   21efa RTOSDemo/executable.elf\r
7043 \r
7044 \r
7045 Done!
7046 \r
7047 Done.
7048 \r
7049 At Local date and time: Thu Jul 02 20:58:12 2009
7050  make -f system.make program started...
7051 \r
7052 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
7053     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
7054 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
7055 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
7056 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
7057 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
7058 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
7059 \r
7060 powerpc-eabi-size RTOSDemo/executable.elf \r
7061    text    data     bss     dec     hex filename\r
7062   50846     368   87832  139046   21f26 RTOSDemo/executable.elf\r
7063 \r
7064 \r
7065 Done!
7066 \r
7067 Done.
7068 \r
7069 At Local date and time: Thu Jul 02 20:59:39 2009
7070  make -f system.make program started...
7071 \r
7072 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
7073     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
7074 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
7075 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
7076 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
7077 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:124: warning: comparison is always true due to limited range of data type
7078 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
7079 \r
7080 powerpc-eabi-size RTOSDemo/executable.elf \r
7081    text    data     bss     dec     hex filename\r
7082   50866     368   87832  139066   21f3a RTOSDemo/executable.elf\r
7083 \r
7084 \r
7085 Done!
7086 \r
7087 Done.
7088 \r
7089 At Local date and time: Thu Jul 02 21:29:34 2009
7090  make -f system.make program started...
7091 \r
7092 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
7093     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
7094 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
7095 powerpc-eabi-size RTOSDemo/executable.elf \r
7096    text    data     bss     dec     hex filename\r
7097   50622     372   87856  138850   21e62 RTOSDemo/executable.elf\r
7098 \r
7099 \r
7100 Done!
7101 \r
7102 Done.
7103 \r
7104 Done.
7105 \r
7106 At Local date and time: Fri Jul 03 02:08:31 2009
7107  make -f system.make download started...
7108 \r
7109 *********************************************\r
7110 Downloading Bitstream onto the target board\r
7111 *********************************************\r
7112 impact -batch etc/download.cmd\r
7113 Release 11.2 - iMPACT L.46 (nt)\r\r
7114 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
7115 Preference Table\r\r
7116 Name                 Setting             \r\r
7117 StartupClock         Auto_Correction     \r\r
7118 AutoSignature        False               \r\r
7119 KeepSVF              False               \r\r
7120 ConcurrentMode       False               \r\r
7121 UseHighz             False               \r\r
7122 ConfigOnFailure      Stop                \r\r
7123 UserLevel            Novice              \r\r
7124 MessageLevel         Detailed            \r\r
7125 svfUseTime           false               \r\r
7126 SpiByteSwap          Auto_Correction     \r\r
7127 AutoDetecting cable. Please wait.\r\r
7128 Connecting to cable (Usb Port - USB21).\r\r
7129 Checking cable driver.\r\r
7130  Driver file xusb_xp2.sys found.\r\r
7131  Driver version: src=2301, dest=2301.\r\r
7132  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
7133 13:58:07, version = 900.\r\r
7134  Cable PID = 0008.\r\r
7135  Max current requested during enumeration is 300 mA.\r\r
7136 Type = 0x0005.\r\r
7137  Cable Type = 3, Revision = 0.\r\r
7138  Setting cable speed to 6 MHz.\r\r
7139 Cable connection established.\r\r
7140 Firmware version = 2401.\r\r
7141 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
7142 Firmware hex file version = 2401.\r\r
7143 PLD file version = 200Dh.\r\r
7144  PLD version = 200Dh.\r\r
7145 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
7146 INFO:iMPACT:1777 - \r
7147    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
7148 \r
7149 ----------------------------------------------------------------------\r\r
7150 ----------------------------------------------------------------------\r\r
7151 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
7152 ----------------------------------------------------------------------\r\r
7153 ----------------------------------------------------------------------\r\r
7154 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
7155 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
7156 INFO:iMPACT:1777 - \r
7157    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
7158 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
7159 \r
7160 INFO:iMPACT:1777 - \r
7161    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
7162 \r
7163 ----------------------------------------------------------------------\r\r
7164 ----------------------------------------------------------------------\r\r
7165 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
7166 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
7167 INFO:iMPACT:1777 - \r
7168    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
7169 \r
7170 ----------------------------------------------------------------------\r\r
7171 ----------------------------------------------------------------------\r\r
7172 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
7173 ----------------------------------------------------------------------\r\r
7174 ----------------------------------------------------------------------\r\r
7175 done.\r\r
7176 Elapsed time =      1 sec.\r\r
7177 Elapsed time =      0 sec.\r\r
7178 '5': Loading file 'implementation/download.bit' ...\r\r
7179 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
7180 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
7181 \r
7182 done.\r\r
7183 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
7184 ----------------------------------------------------------------------\r\r
7185 ----------------------------------------------------------------------\r\r
7186 ----------------------------------------------------------------------\r\r
7187 Maximum TCK operating frequency for this device chain: 10000000.\r\r
7188 Validating chain...\r\r
7189 Boundary-scan chain validated successfully.\r\r
7190 5: Device Temperature: Current Reading:   38.07 C, Min. Reading:   35.12 C, Max.\r\r
7191 Reading:   38.56 C\r\r
7192 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.\r\r
7193 Reading:   1.002 V\r\r
7194 5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.\r\r
7195 Reading:   2.505 V\r\r
7196 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
7197 \r
7198 '5': Programming device...\r\r
7199  Match_cycle = 2.\r\r
7200 done.\r\r
7201 '5': Reading status register contents...\r\r
7202 CRC error                                         :         0\r\r
7203 Decryptor security set                            :         0\r\r
7204 DCM locked                                        :         1\r\r
7205 DCI matched                                       :         1\r\r
7206 End of startup signal from Startup block          :         1\r\r
7207 status of GTS_CFG_B                               :         1\r\r
7208 status of GWE                                     :         1\r\r
7209 status of GHIGH                                   :         1\r\r
7210 value of MODE pin M0                              :         1\r\r
7211 value of MODE pin M1                              :         0\r\r
7212 Value of MODE pin M2                              :         1\r\r
7213 Internal signal indicates when housecleaning is completed:         1\r\r
7214 Value driver in from INIT pad                     :         1\r\r
7215 Internal signal indicates that chip is configured :         1\r\r
7216 Value of DONE pin                                 :         1\r\r
7217 Indicates when ID value written does not match chip ID:         0\r\r
7218 Decryptor error Signal                            :         0\r\r
7219 System Monitor Over-Temperature Alarm             :         0\r\r
7220 startup_state[18] CFG startup state machine       :         0\r\r
7221 startup_state[19] CFG startup state machine       :         0\r\r
7222 startup_state[20] CFG startup state machine       :         1\r\r
7223 E-fuse program voltage available                  :         0\r\r
7224 SPI Flash Type[22] Select                         :         1\r\r
7225 SPI Flash Type[23] Select                         :         1\r\r
7226 SPI Flash Type[24] Select                         :         1\r\r
7227 CFG bus width auto detection result               :         0\r\r
7228 CFG bus width auto detection result               :         0\r\r
7229 Reserved                                          :         0\r\r
7230 BPI address wrap around error                     :         0\r\r
7231 IPROG pulsed                                      :         0\r\r
7232 read back crc error                               :         0\r\r
7233 Indicates that efuse logic is busy                :         0\r\r
7234  Match_cycle = 2.\r\r
7235 '5': Programmed successfully.\r\r
7236 Elapsed time =     11 sec.\r\r
7237 ----------------------------------------------------------------------\r\r
7238 ----------------------------------------------------------------------\r\r
7239 ----------------------------------------------------------------------\r\r
7240 ----------------------------------------------------------------------\r\r
7241 ----------------------------------------------------------------------\r\r
7242 ----------------------------------------------------------------------\r\r
7243 ----------------------------------------------------------------------\r\r
7244 ----------------------------------------------------------------------\r\r
7245 INFO:iMPACT:2219 - Status register values:\r
7246 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
7247 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
7248 INFO:iMPACT - '5': Programing completed successfully.\r
7249 INFO:iMPACT - '5': Checking done pin....done.\r
7250 \r
7251 \r
7252 \r
7253 Done!
7254 \r
7255 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
7256 \r
7257 Done.
7258 \r
7259 Writing filter settings....
7260 \r
7261 Done writing filter settings to:
7262         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
7263 \r
7264 Done writing Tab View settings to:
7265         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
7266 \r
7267 Xilinx Platform Studio (XPS)\r
7268 Xilinx EDK 11.2 Build EDK_LS3.47
7269 \r
7270 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
7271 \r
7272 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
7273 \r
7274 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
7275 \r
7276 Generating Block Diagram to Buffer
7277 \r
7278 Generated Block Diagram SVG
7279 \r
7280 At Local date and time: Fri Jul 03 18:19:28 2009
7281  make -f system.make download started...
7282 \r
7283 *********************************************\r
7284 Downloading Bitstream onto the target board\r
7285 *********************************************\r
7286 impact -batch etc/download.cmd\r
7287 Release 11.2 - iMPACT L.46 (nt)\r\r
7288 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
7289 Preference Table\r\r
7290 Name                 Setting             \r\r
7291 StartupClock         Auto_Correction     \r\r
7292 AutoSignature        False               \r\r
7293 KeepSVF              False               \r\r
7294 ConcurrentMode       False               \r\r
7295 UseHighz             False               \r\r
7296 ConfigOnFailure      Stop                \r\r
7297 UserLevel            Novice              \r\r
7298 MessageLevel         Detailed            \r\r
7299 svfUseTime           false               \r\r
7300 SpiByteSwap          Auto_Correction     \r\r
7301 AutoDetecting cable. Please wait.\r\r
7302 Connecting to cable (Usb Port - USB21).\r\r
7303 Checking cable driver.\r\r
7304  Driver file xusb_xp2.sys found.\r\r
7305  Driver version: src=2301, dest=2301.\r\r
7306  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
7307 13:58:07, version = 900.\r\r
7308  Cable PID = 0008.\r\r
7309  Max current requested during enumeration is 300 mA.\r\r
7310 Type = 0x0005.\r\r
7311  Cable Type = 3, Revision = 0.\r\r
7312  Setting cable speed to 6 MHz.\r\r
7313 Cable connection established.\r\r
7314 Firmware version = 2401.\r\r
7315 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
7316 Firmware hex file version = 2401.\r\r
7317 PLD file version = 200Dh.\r\r
7318  PLD version = 200Dh.\r\r
7319 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
7320 INFO:iMPACT:1777 - \r
7321    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
7322 \r
7323 ----------------------------------------------------------------------\r\r
7324 ----------------------------------------------------------------------\r\r
7325 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
7326 ----------------------------------------------------------------------\r\r
7327 ----------------------------------------------------------------------\r\r
7328 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
7329 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
7330 INFO:iMPACT:1777 - \r
7331    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
7332 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
7333 \r
7334 INFO:iMPACT:1777 - \r
7335    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
7336 \r
7337 ----------------------------------------------------------------------\r\r
7338 ----------------------------------------------------------------------\r\r
7339 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
7340 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
7341 \r
7342 INFO:iMPACT:1777 - \r
7343    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
7344 \r
7345 ----------------------------------------------------------------------\r\r
7346 ----------------------------------------------------------------------\r\r
7347 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
7348 ----------------------------------------------------------------------\r\r
7349 ----------------------------------------------------------------------\r\r
7350 done.\r\r
7351 Elapsed time =      5 sec.\r\r
7352 Elapsed time =      0 sec.\r\r
7353 '5': Loading file 'implementation/download.bit' ...\r\r
7354 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
7355 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
7356 \r
7357 done.\r\r
7358 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
7359 ----------------------------------------------------------------------\r\r
7360 ----------------------------------------------------------------------\r\r
7361 ----------------------------------------------------------------------\r\r
7362 Maximum TCK operating frequency for this device chain: 10000000.\r\r
7363 Validating chain...\r\r
7364 Boundary-scan chain validated successfully.\r\r
7365 5: Device Temperature: Current Reading:   59.23 C, Min. Reading:   38.07 C, Max.\r\r
7366 Reading:   74.99 C\r\r
7367 5: VCCINT Supply: Current Reading:   0.996 V, Min. Reading:   0.993 V, Max.\r\r
7368 Reading:   1.002 V\r\r
7369 5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.\r\r
7370 Reading:   2.505 V\r\r
7371 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
7372 \r
7373 '5': Programming device...\r\r
7374  Match_cycle = 2.\r\r
7375 done.\r\r
7376 '5': Reading status register contents...\r\r
7377 CRC error                                         :         0\r\r
7378 Decryptor security set                            :         0\r\r
7379 DCM locked                                        :         1\r\r
7380 DCI matched                                       :         1\r\r
7381 End of startup signal from Startup block          :         1\r\r
7382 status of GTS_CFG_B                               :         1\r\r
7383 status of GWE                                     :         1\r\r
7384 status of GHIGH                                   :         1\r\r
7385 value of MODE pin M0                              :         1\r\r
7386 value of MODE pin M1                              :         0\r\r
7387 Value of MODE pin M2                              :         1\r\r
7388 Internal signal indicates when housecleaning is completed:         1\r\r
7389 Value driver in from INIT pad                     :         1\r\r
7390 Internal signal indicates that chip is configured :         1\r\r
7391 Value of DONE pin                                 :         1\r\r
7392 Indicates when ID value written does not match chip ID:         0\r\r
7393 Decryptor error Signal                            :         0\r\r
7394 System Monitor Over-Temperature Alarm             :         0\r\r
7395 startup_state[18] CFG startup state machine       :         0\r\r
7396 startup_state[19] CFG startup state machine       :         0\r\r
7397 startup_state[20] CFG startup state machine       :         1\r\r
7398 E-fuse program voltage available                  :         0\r\r
7399 SPI Flash Type[22] Select                         :         1\r\r
7400 SPI Flash Type[23] Select                         :         1\r\r
7401 SPI Flash Type[24] Select                         :         1\r\r
7402 CFG bus width auto detection result               :         0\r\r
7403 CFG bus width auto detection result               :         0\r\r
7404 Reserved                                          :         0\r\r
7405 BPI address wrap around error                     :         0\r\r
7406 IPROG pulsed                                      :         0\r\r
7407 read back crc error                               :         0\r\r
7408 Indicates that efuse logic is busy                :         0\r\r
7409  Match_cycle = 2.\r\r
7410 '5': Programmed successfully.\r\r
7411 Elapsed time =     11 sec.\r\r
7412 ----------------------------------------------------------------------\r\r
7413 ----------------------------------------------------------------------\r\r
7414 ----------------------------------------------------------------------\r\r
7415 ----------------------------------------------------------------------\r\r
7416 ----------------------------------------------------------------------\r\r
7417 ----------------------------------------------------------------------\r\r
7418 ----------------------------------------------------------------------\r\r
7419 ----------------------------------------------------------------------\r\r
7420 INFO:iMPACT:2219 - Status register values:\r
7421 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
7422 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
7423 INFO:iMPACT - '5': Programing completed successfully.\r
7424 INFO:iMPACT - '5': Checking done pin....done.\r
7425 \r
7426 \r
7427 \r
7428 Done!
7429 \r
7430 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
7431 \r
7432 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
7433 \r
7434 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
7435 \r
7436 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
7437 \r
7438 At Local date and time: Fri Jul 03 18:20:05 2009
7439  make -f system.make program started...
7440 \r
7441 powerpc-eabi-gcc -O3 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
7442     -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
7443 -D USE_DP_FPU -D GCC_PPC440 -mregnames  \r
7444 powerpc-eabi-size RTOSDemo/executable.elf \r
7445    text    data     bss     dec     hex filename\r
7446   44758     372   87852  132982   20776 RTOSDemo/executable.elf\r
7447 \r
7448 \r
7449 Done!
7450 \r
7451 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
7452 \r
7453 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
7454 \r
7455 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
7456 \r
7457 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
7458 \r
7459 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
7460 \r
7461 Writing filter settings....
7462 \r
7463 Done writing filter settings to:
7464         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
7465 \r
7466 Done writing Tab View settings to:
7467         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
7468 \r
7469 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
7470 \r
7471 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
7472 \r
7473 Generating Block Diagram to Buffer
7474 \r
7475 Generated Block Diagram SVG
7476 \r
7477 At Local date and time: Sun Jul 05 09:36:55 2009
7478  make -f system.make hwclean started...
7479 \r
7480 rm -f implementation/system.ngc\r
7481 rm -f platgen.log\r
7482 rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
7483 rm -f implementation/system.bmm\r
7484 rm -f implementation/system.bit\r
7485 rm -f implementation/system.ncd\r
7486 rm -f implementation/system_bd.bmm \r
7487 rm -f implementation/system_map.ncd \r
7488 rm -f __xps/system_routed\r
7489 rm -rf implementation synthesis xst hdl\r
7490 rm -rf xst.srp system.srp\r
7491 rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
7492 \r
7493 \r
7494 Done!
7495 \r
7496 At Local date and time: Sun Jul 05 09:37:10 2009
7497  make -f system.make swclean started...
7498 \r
7499 rm -rf ppc440_0/\r
7500 rm -f libgen.log\r
7501 rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
7502 rm -f RTOSDemo/executable.elf \r
7503 \r
7504 \r
7505 Done!
7506 \r
7507 Writing filter settings....
7508 \r
7509 Done writing filter settings to:
7510         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
7511 \r
7512 Done writing Tab View settings to:
7513         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
7514 \r