git.sur5r.net Git - freertos/blob - Demo/PPC440_Xilinx_Virtex5_GCC/__xps/ise/system.xise

   1 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
   2 <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
   3
   4   <header>
   5     <!-- ISE source project file created by Project Navigator.             -->
   6     <!--                                                                   -->
   7     <!-- This file contains project source information including a list of -->
   8     <!-- project source files, project and process properties.  This file, -->
   9     <!-- along with the project source files, is sufficient to open and    -->
  10     <!-- implement in ISE Project Navigator.                               -->
  11     <!--                                                                   -->
  12     <!-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved. -->
  13   </header>
  14
  15   <version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
  16
  17   <files/>
  18
  19   <properties>
  20     <property xil_pn:name="Device" xil_pn:value="xa2c*"/>
  21     <property xil_pn:name="Device Family" xil_pn:value="Automotive CoolRunner2"/>
  22     <property xil_pn:name="PROP_DesignName" xil_pn:value="system"/>
  23     <property xil_pn:name="PROP_Enable_Incremental_Messaging" xil_pn:value="true"/>
  24     <property xil_pn:name="PROP_Enable_Message_Filtering" xil_pn:value="true"/>
  25     <property xil_pn:name="Package" xil_pn:value="*"/>
  26     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
  27     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
  28     <property xil_pn:name="Speed Grade" xil_pn:value="-*"/>
  29     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
  30     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
  31     <property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
  32   </properties>
  33
  34   <bindings/>
  35
  36   <libraries/>
  37
  38   <partitions>
  39     <partition xil_pn:name="/"/>
  40   </partitions>
  41
  42 </project>