2 # ##############################################################################
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3 # Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1
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4 # Thu Jun 11 19:28:07 2009
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5 # Target Board: Xilinx Virtex 5 ML507 Evaluation Platform Rev A
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10 # Processor number: 1
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11 # Processor 1: ppc440_0
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12 # Processor clock frequency: 125.0
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13 # Bus clock frequency: 125.0
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14 # Debug Interface: FPGA JTAG
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15 # ##############################################################################
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16 PARAMETER VERSION = 2.1.0
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19 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
\r
20 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
\r
21 PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
\r
22 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]
\r
23 PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4]
\r
24 PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
\r
25 PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO
\r
26 PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO
\r
27 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
\r
28 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O
\r
29 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O
\r
30 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O
\r
31 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3]
\r
32 PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O
\r
33 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31]
\r
34 PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O
\r
35 PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
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36 PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I
\r
37 PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I
\r
38 PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O
\r
39 PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O
\r
40 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I
\r
41 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I
\r
42 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I
\r
43 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I
\r
44 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0]
\r
45 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I
\r
46 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I
\r
47 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O
\r
48 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O
\r
49 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0]
\r
50 PORT fpga_0_Ethernet_MAC_MDINT_pin = fpga_0_Ethernet_MAC_MDINT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
\r
51 PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
\r
52 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
\r
53 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin, DIR = IO, VEC = [7:0]
\r
54 PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A_pin, DIR = O, VEC = [12:0]
\r
55 PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA_pin, DIR = O, VEC = [1:0]
\r
56 PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin, DIR = O
\r
57 PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin, DIR = O
\r
58 PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin, DIR = O
\r
59 PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin, DIR = O
\r
60 PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]
\r
61 PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE_pin, DIR = O
\r
62 PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]
\r
63 PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK_pin, DIR = O, VEC = [1:0]
\r
64 PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin, DIR = O, VEC = [1:0]
\r
65 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
\r
66 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
\r
67 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
\r
68 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
\r
69 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
\r
70 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
\r
71 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
\r
72 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
\r
73 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
\r
74 PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK
\r
75 PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK
\r
78 BEGIN ppc440_virtex5
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79 PARAMETER INSTANCE = ppc440_0
\r
80 PARAMETER C_IDCR_BASEADDR = 0b0000000000
\r
81 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
\r
82 PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00
\r
83 PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000
\r
84 PARAMETER C_PPC440MC_CONTROL = 0xF810008F
\r
85 PARAMETER C_SPLB0_USE_MPLB_ADDR = 1
\r
86 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1
\r
87 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
\r
88 PARAMETER HW_VER = 1.01.a
\r
89 PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000
\r
90 PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff
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91 PARAMETER C_SPLB0_RNG_MC_BASEADDR = 0x00000000
\r
92 PARAMETER C_SPLB0_RNG_MC_HIGHADDR = 0x0fffffff
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93 BUS_INTERFACE MPLB = plb_v46_0
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94 BUS_INTERFACE SPLB0 = ppc440_0_SPLB0
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95 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
\r
96 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
\r
97 BUS_INTERFACE RESETPPC = ppc_reset_bus
\r
98 PORT CPMC440CLK = clk_125_0000MHzPLL0
\r
99 PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0
\r
100 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
\r
101 PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
\r
102 PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST
\r
103 PORT CPMPPCMPLBCLK = clk_125_0000MHzPLL0_ADJUST
\r
104 PORT CPMPPCS0PLBCLK = clk_125_0000MHzPLL0_ADJUST
\r
108 PARAMETER INSTANCE = plb_v46_0
\r
109 PARAMETER C_DCR_INTFCE = 0
\r
110 PARAMETER C_FAMILY = virtex5
\r
111 PARAMETER HW_VER = 1.04.a
\r
112 PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
\r
113 PORT SYS_Rst = sys_bus_reset
\r
116 BEGIN xps_bram_if_cntlr
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117 PARAMETER INSTANCE = xps_bram_if_cntlr_1
\r
118 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
\r
119 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
\r
120 PARAMETER C_SPLB_P2P = 0
\r
121 PARAMETER C_FAMILY = virtex5
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122 PARAMETER HW_VER = 1.00.b
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123 PARAMETER C_BASEADDR = 0xffffe000
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124 PARAMETER C_HIGHADDR = 0xffffffff
\r
125 BUS_INTERFACE SPLB = plb_v46_0
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126 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
\r
130 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
\r
131 PARAMETER C_FAMILY = virtex5
\r
132 PARAMETER HW_VER = 1.00.a
\r
133 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
\r
137 PARAMETER INSTANCE = RS232_Uart_1
\r
138 PARAMETER C_FAMILY = virtex5
\r
139 PARAMETER C_BAUDRATE = 9600
\r
140 PARAMETER C_DATA_BITS = 8
\r
141 PARAMETER C_USE_PARITY = 0
\r
142 PARAMETER C_ODD_PARITY = 0
\r
143 PARAMETER HW_VER = 1.01.a
\r
144 PARAMETER C_BASEADDR = 0x84000000
\r
145 PARAMETER C_HIGHADDR = 0x8400ffff
\r
146 BUS_INTERFACE SPLB = plb_v46_0
\r
147 PORT RX = fpga_0_RS232_Uart_1_RX_pin
\r
148 PORT TX = fpga_0_RS232_Uart_1_TX_pin
\r
149 PORT Interrupt = RS232_Uart_1_Interrupt
\r
153 PARAMETER INSTANCE = LEDs_8Bit
\r
154 PARAMETER C_FAMILY = virtex5
\r
155 PARAMETER C_ALL_INPUTS = 0
\r
156 PARAMETER C_GPIO_WIDTH = 8
\r
157 PARAMETER C_INTERRUPT_PRESENT = 0
\r
158 PARAMETER C_IS_DUAL = 0
\r
159 PARAMETER HW_VER = 2.00.a
\r
160 PARAMETER C_BASEADDR = 0x81440000
\r
161 PARAMETER C_HIGHADDR = 0x8144ffff
\r
162 BUS_INTERFACE SPLB = plb_v46_0
\r
163 PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin
\r
167 PARAMETER INSTANCE = LEDs_Positions
\r
168 PARAMETER C_FAMILY = virtex5
\r
169 PARAMETER C_ALL_INPUTS = 0
\r
170 PARAMETER C_GPIO_WIDTH = 5
\r
171 PARAMETER C_INTERRUPT_PRESENT = 0
\r
172 PARAMETER C_IS_DUAL = 0
\r
173 PARAMETER HW_VER = 2.00.a
\r
174 PARAMETER C_BASEADDR = 0x81420000
\r
175 PARAMETER C_HIGHADDR = 0x8142ffff
\r
176 BUS_INTERFACE SPLB = plb_v46_0
\r
177 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin
\r
181 PARAMETER INSTANCE = Push_Buttons_5Bit
\r
182 PARAMETER C_FAMILY = virtex5
\r
183 PARAMETER C_ALL_INPUTS = 1
\r
184 PARAMETER C_GPIO_WIDTH = 5
\r
185 PARAMETER C_INTERRUPT_PRESENT = 0
\r
186 PARAMETER C_IS_DUAL = 0
\r
187 PARAMETER HW_VER = 2.00.a
\r
188 PARAMETER C_BASEADDR = 0x81400000
\r
189 PARAMETER C_HIGHADDR = 0x8140ffff
\r
190 BUS_INTERFACE SPLB = plb_v46_0
\r
191 PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin
\r
195 PARAMETER INSTANCE = DIP_Switches_8Bit
\r
196 PARAMETER C_FAMILY = virtex5
\r
197 PARAMETER C_ALL_INPUTS = 1
\r
198 PARAMETER C_GPIO_WIDTH = 8
\r
199 PARAMETER C_INTERRUPT_PRESENT = 0
\r
200 PARAMETER C_IS_DUAL = 0
\r
201 PARAMETER HW_VER = 2.00.a
\r
202 PARAMETER C_BASEADDR = 0x81460000
\r
203 PARAMETER C_HIGHADDR = 0x8146ffff
\r
204 BUS_INTERFACE SPLB = plb_v46_0
\r
205 PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin
\r
209 PARAMETER INSTANCE = IIC_EEPROM
\r
210 PARAMETER C_IIC_FREQ = 100000
\r
211 PARAMETER C_TEN_BIT_ADR = 0
\r
212 PARAMETER C_FAMILY = virtex5
\r
213 PARAMETER HW_VER = 2.01.a
\r
214 PARAMETER C_BASEADDR = 0x81600000
\r
215 PARAMETER C_HIGHADDR = 0x8160ffff
\r
216 BUS_INTERFACE SPLB = plb_v46_0
\r
217 PORT Sda = fpga_0_IIC_EEPROM_Sda_pin
\r
218 PORT Scl = fpga_0_IIC_EEPROM_Scl_pin
\r
222 PARAMETER INSTANCE = SRAM
\r
223 PARAMETER C_FAMILY = virtex5
\r
224 PARAMETER C_NUM_BANKS_MEM = 1
\r
225 PARAMETER C_NUM_CHANNELS = 0
\r
226 PARAMETER C_MEM0_WIDTH = 32
\r
227 PARAMETER C_MAX_MEM_WIDTH = 32
\r
228 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
\r
229 PARAMETER C_SYNCH_MEM_0 = 1
\r
230 PARAMETER C_TCEDV_PS_MEM_0 = 0
\r
231 PARAMETER C_TAVDV_PS_MEM_0 = 0
\r
232 PARAMETER C_THZCE_PS_MEM_0 = 0
\r
233 PARAMETER C_THZOE_PS_MEM_0 = 0
\r
234 PARAMETER C_TWC_PS_MEM_0 = 0
\r
235 PARAMETER C_TWP_PS_MEM_0 = 0
\r
236 PARAMETER C_TLZWE_PS_MEM_0 = 0
\r
237 PARAMETER HW_VER = 3.00.a
\r
238 PARAMETER C_MEM0_BASEADDR = 0xf8000000
\r
239 PARAMETER C_MEM0_HIGHADDR = 0xf80fffff
\r
240 BUS_INTERFACE SPLB = plb_v46_0
\r
241 PORT RdClk = clk_125_0000MHzPLL0_ADJUST
\r
242 PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0
\r
243 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin
\r
244 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin
\r
245 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin
\r
246 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin
\r
247 PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin
\r
248 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin
\r
252 PARAMETER INSTANCE = PCIe_Bridge
\r
253 PARAMETER C_FAMILY = virtex5
\r
254 PARAMETER C_IPIFBAR_NUM = 2
\r
255 PARAMETER C_PCIBAR_NUM = 1
\r
256 PARAMETER C_DEVICE_ID = 0x0505
\r
257 PARAMETER C_VENDOR_ID = 0x10EE
\r
258 PARAMETER C_CLASS_CODE = 0x058000
\r
259 PARAMETER C_REV_ID = 0x00
\r
260 PARAMETER C_SUBSYSTEM_ID = 0x0000
\r
261 PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x0000
\r
262 PARAMETER C_COMP_TIMEOUT = 1
\r
263 PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000
\r
264 PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000
\r
265 PARAMETER C_PCIBAR2IPIFBAR_0 = 0xf8000000
\r
266 PARAMETER C_PCIBAR2IPIFBAR_1 = 0x00000000
\r
267 PARAMETER C_PCIBAR_LEN_0 = 20
\r
268 PARAMETER C_PCIBAR_LEN_1 = 28
\r
269 PARAMETER C_BOARD = ml507
\r
270 PARAMETER HW_VER = 3.00.b
\r
271 PARAMETER C_BASEADDR = 0x85c00000
\r
272 PARAMETER C_HIGHADDR = 0x85c0ffff
\r
273 PARAMETER C_IPIFBAR_0 = 0xc0000000
\r
274 PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff
\r
275 PARAMETER C_IPIFBAR_1 = 0xe0000000
\r
276 PARAMETER C_IPIFBAR_HIGHADDR_1 = 0xefffffff
\r
277 BUS_INTERFACE SPLB = plb_v46_0
\r
278 BUS_INTERFACE MPLB = ppc440_0_SPLB0
\r
279 PORT PERSTN = net_vcc
\r
280 PORT REFCLK = PCIe_Diff_Clk
\r
281 PORT RXN = fpga_0_PCIe_Bridge_RXN_pin
\r
282 PORT RXP = fpga_0_PCIe_Bridge_RXP_pin
\r
283 PORT TXN = fpga_0_PCIe_Bridge_TXN_pin
\r
284 PORT TXP = fpga_0_PCIe_Bridge_TXP_pin
\r
285 PORT MSI_request = net_gnd
\r
289 PARAMETER INSTANCE = ppc440_0_SPLB0
\r
290 PARAMETER C_FAMILY = virtex5
\r
291 PARAMETER HW_VER = 1.04.a
\r
292 PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
\r
293 PORT SYS_Rst = sys_bus_reset
\r
296 BEGIN xps_ethernetlite
\r
297 PARAMETER INSTANCE = Ethernet_MAC
\r
298 PARAMETER C_FAMILY = virtex5
\r
299 PARAMETER HW_VER = 2.01.a
\r
300 PARAMETER C_BASEADDR = 0x81000000
\r
301 PARAMETER C_HIGHADDR = 0x8100ffff
\r
302 BUS_INTERFACE SPLB = plb_v46_0
\r
303 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin
\r
304 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin
\r
305 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin
\r
306 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin
\r
307 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin
\r
308 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin
\r
309 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin
\r
310 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin
\r
311 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin
\r
312 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin
\r
315 BEGIN ppc440mc_ddr2
\r
316 PARAMETER INSTANCE = DDR2_SDRAM
\r
317 PARAMETER C_DDR_BAWIDTH = 2
\r
318 PARAMETER C_NUM_CLK_PAIRS = 2
\r
319 PARAMETER C_DDR_DWIDTH = 64
\r
320 PARAMETER C_DDR_CAWIDTH = 10
\r
321 PARAMETER C_NUM_RANKS_MEM = 1
\r
322 PARAMETER C_CS_BITS = 0
\r
323 PARAMETER C_DDR_DM_WIDTH = 8
\r
324 PARAMETER C_DQ_BITS = 8
\r
325 PARAMETER C_DDR2_ODT_WIDTH = 2
\r
326 PARAMETER C_DDR2_ADDT_LAT = 0
\r
327 PARAMETER C_INCLUDE_ECC_SUPPORT = 0
\r
328 PARAMETER C_DDR2_ODT_SETTING = 1
\r
329 PARAMETER C_DQS_BITS = 3
\r
330 PARAMETER C_DDR_DQS_WIDTH = 8
\r
331 PARAMETER C_DDR_RAWIDTH = 13
\r
332 PARAMETER C_DDR_BURST_LENGTH = 4
\r
333 PARAMETER C_DDR_CAS_LAT = 4
\r
334 PARAMETER C_REG_DIMM = 0
\r
335 PARAMETER C_MIB_MC_CLOCK_RATIO = 1
\r
336 PARAMETER C_DDR_TREFI = 3900
\r
337 PARAMETER C_DDR_TRAS = 40000
\r
338 PARAMETER C_DDR_TRCD = 15000
\r
339 PARAMETER C_DDR_TRFC = 75000
\r
340 PARAMETER C_DDR_TRP = 15000
\r
341 PARAMETER C_DDR_TRTP = 7500
\r
342 PARAMETER C_DDR_TWR = 15000
\r
343 PARAMETER C_DDR_TWTR = 7500
\r
344 PARAMETER C_MC_MIBCLK_PERIOD_PS = 8000
\r
345 PARAMETER C_IDEL_HIGH_PERF = TRUE
\r
346 PARAMETER C_NUM_IDELAYCTRL = 3
\r
347 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
\r
348 PARAMETER C_DQS_IO_COL = 0b000000000000000000
\r
349 PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100
\r
350 PARAMETER HW_VER = 2.00.b
\r
351 PARAMETER C_MEM_BASEADDR = 0x00000000
\r
352 PARAMETER C_MEM_HIGHADDR = 0x0fffffff
\r
353 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
\r
354 PORT mc_mibclk = clk_125_0000MHzPLL0_ADJUST
\r
355 PORT mi_mcclk90 = clk_125_0000MHz90PLL0_ADJUST
\r
356 PORT mi_mcreset = sys_bus_reset
\r
357 PORT mi_mcclkdiv2 = clk_62_5000MHzPLL0_ADJUST
\r
358 PORT mi_mcclk_200 = clk_200_0000MHz
\r
359 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
\r
360 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
\r
361 PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin
\r
362 PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A_pin
\r
363 PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA_pin
\r
364 PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin
\r
365 PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin
\r
366 PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin
\r
367 PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin
\r
368 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
\r
369 PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE_pin
\r
370 PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
\r
371 PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK_pin
\r
372 PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin
\r
376 PARAMETER INSTANCE = SysACE_CompactFlash
\r
377 PARAMETER C_MEM_WIDTH = 16
\r
378 PARAMETER C_FAMILY = virtex5
\r
379 PARAMETER HW_VER = 1.01.a
\r
380 PARAMETER C_BASEADDR = 0x83600000
\r
381 PARAMETER C_HIGHADDR = 0x8360ffff
\r
382 BUS_INTERFACE SPLB = plb_v46_0
\r
383 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
\r
384 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
\r
385 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
\r
386 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
\r
387 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
\r
388 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
\r
389 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
\r
392 BEGIN clock_generator
\r
393 PARAMETER INSTANCE = clock_generator_0
\r
394 PARAMETER C_CLKIN_FREQ = 100000000
\r
395 PARAMETER C_CLKFBIN_FREQ = 125000000
\r
396 PARAMETER C_CLKOUT0_FREQ = 125000000
\r
397 PARAMETER C_CLKOUT0_PHASE = 90
\r
398 PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
\r
399 PARAMETER C_CLKOUT0_BUF = TRUE
\r
400 PARAMETER C_CLKOUT1_FREQ = 125000000
\r
401 PARAMETER C_CLKOUT1_PHASE = 0
\r
402 PARAMETER C_CLKOUT1_GROUP = PLL0
\r
403 PARAMETER C_CLKOUT1_BUF = TRUE
\r
404 PARAMETER C_CLKOUT2_FREQ = 125000000
\r
405 PARAMETER C_CLKOUT2_PHASE = 0
\r
406 PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
\r
407 PARAMETER C_CLKOUT2_BUF = TRUE
\r
408 PARAMETER C_CLKOUT3_FREQ = 200000000
\r
409 PARAMETER C_CLKOUT3_PHASE = 0
\r
410 PARAMETER C_CLKOUT3_GROUP = NONE
\r
411 PARAMETER C_CLKOUT3_BUF = TRUE
\r
412 PARAMETER C_CLKOUT4_FREQ = 62500000
\r
413 PARAMETER C_CLKOUT4_PHASE = 0
\r
414 PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
\r
415 PARAMETER C_CLKOUT4_BUF = TRUE
\r
416 PARAMETER C_CLKFBOUT_FREQ = 125000000
\r
417 PARAMETER C_CLKFBOUT_BUF = TRUE
\r
418 PARAMETER HW_VER = 3.01.a
\r
419 PORT CLKIN = dcm_clk_s
\r
420 PORT CLKFBIN = SRAM_CLK_FB_s
\r
421 PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST
\r
422 PORT CLKOUT1 = clk_125_0000MHzPLL0
\r
423 PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST
\r
424 PORT CLKOUT3 = clk_200_0000MHz
\r
425 PORT CLKOUT4 = clk_62_5000MHzPLL0_ADJUST
\r
426 PORT CLKFBOUT = SRAM_CLK_OUT_s
\r
428 PORT LOCKED = Dcm_all_locked
\r
431 BEGIN jtagppc_cntlr
\r
432 PARAMETER INSTANCE = jtagppc_cntlr_inst
\r
433 PARAMETER HW_VER = 2.01.c
\r
434 BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
\r
437 BEGIN proc_sys_reset
\r
438 PARAMETER INSTANCE = proc_sys_reset_0
\r
439 PARAMETER C_EXT_RESET_HIGH = 0
\r
440 PARAMETER HW_VER = 2.00.a
\r
441 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
\r
442 PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST
\r
443 PORT Ext_Reset_In = sys_rst_s
\r
444 PORT Dcm_locked = Dcm_all_locked
\r
445 PORT Bus_Struct_Reset = sys_bus_reset
\r
446 PORT Peripheral_Reset = sys_periph_reset
\r
450 PARAMETER INSTANCE = xps_intc_0
\r
451 PARAMETER HW_VER = 2.00.a
\r
452 PARAMETER C_BASEADDR = 0x81800000
\r
453 PARAMETER C_HIGHADDR = 0x8180ffff
\r
454 BUS_INTERFACE SPLB = plb_v46_0
\r
455 PORT Intr = fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt
\r
456 PORT Irq = ppc440_0_EICC440EXTIRQ
\r