2 FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.
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4 ***************************************************************************
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20 * and 8pm GMT (although please allow up to 24 hours in case of *
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21 * exceptional circumstances). Thank you for your support! *
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23 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 ***NOTE*** The exception to the GPL is included to allow you to distribute
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31 a combined work that includes FreeRTOS without being obliged to provide the
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32 source code for proprietary components outside of the FreeRTOS kernel.
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33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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54 /* Hardware specific includes. */
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55 #include "iodefine.h"
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56 #include "typedefine.h"
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57 #include "r_ether.h"
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60 /* FreeRTOS includes. */
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61 #include "FreeRTOS.h"
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66 #include "net/uip.h"
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68 /* The time to wait between attempts to obtain a free buffer. */
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69 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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71 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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72 up on attempting to obtain a free buffer all together. */
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73 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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75 /* The number of Rx descriptors. */
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76 #define emacNUM_RX_DESCRIPTORS 8
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78 /* The number of Tx descriptors. When using uIP there is not point in having
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80 #define emacNUM_TX_BUFFERS 2
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82 /* The total number of EMAC buffers to allocate. */
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83 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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85 /* The time to wait for the Tx descriptor to become free. */
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86 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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88 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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90 #define emacTX_WAIT_ATTEMPTS ( 50 )
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92 /* Only Rx end and Tx end interrupts are used by this driver. */
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93 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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94 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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96 /*-----------------------------------------------------------*/
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98 /* The buffers and descriptors themselves. */
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99 static volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ] __attribute__((aligned(16)));
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100 static volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ] __attribute__((aligned(16)));
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101 static char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ] __attribute__((aligned(16)));
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103 /* Used to indicate which buffers are free and which are in use. If an index
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104 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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105 the buffer is in use or about to be used. */
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106 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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108 /*-----------------------------------------------------------*/
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111 * Initialise both the Rx and Tx descriptors.
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113 static void prvInitialiseDescriptors( void );
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116 * Return a pointer to a free buffer within xEthernetBuffers.
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118 static unsigned char *prvGetNextBuffer( void );
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121 * Return a buffer to the list of free buffers.
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123 static void prvReturnBuffer( unsigned char *pucBuffer );
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126 * Examine the status of the next Rx FIFO to see if it contains new data.
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128 static unsigned long prvCheckRxFifoStatus( void );
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131 * Setup the microcontroller for communication with the PHY.
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133 static void prvResetMAC( void );
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136 * Configure the Ethernet interface peripherals.
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138 static void prvConfigureEtherCAndEDMAC( void );
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141 * Something has gone wrong with the descriptor usage. Reset all the buffers
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144 static void prvResetEverything( void );
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147 * Wrapper and handler for the EMAC peripheral. See the documentation for this
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148 * port on http://www.FreeRTOS.org for more information on defining interrupt
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151 void vEMAC_ISR_Wrapper( void ) __attribute__((naked));
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152 static void vEMAC_ISR_Handler( void ) __attribute__((noinline));
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154 /*-----------------------------------------------------------*/
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156 /* Points to the Rx descriptor currently in use. */
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157 static ethfifo *pxCurrentRxDesc = NULL;
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159 /* The buffer used by the uIP stack to both receive and send. This points to
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160 one of the Ethernet buffers when its actually in use. */
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161 unsigned char *uip_buf = NULL;
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163 /*-----------------------------------------------------------*/
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165 void vInitEmac( void )
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167 /* Software reset. */
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170 /* Set the Rx and Tx descriptors into their initial state. */
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171 prvInitialiseDescriptors();
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173 /* Set the MAC address into the ETHERC */
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174 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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175 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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176 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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177 ( unsigned long ) configMAC_ADDR3;
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179 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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180 ( unsigned long ) configMAC_ADDR5;
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182 /* Perform rest of interface hardware configuration. */
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183 prvConfigureEtherCAndEDMAC();
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185 /* Nothing received yet, so uip_buf points nowhere. */
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188 /* Initialize the PHY */
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191 /*-----------------------------------------------------------*/
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193 void vEMACWrite( void )
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197 /* Wait until the second transmission of the last packet has completed. */
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198 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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200 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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202 /* Descriptor is still active. */
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203 vTaskDelay( emacTX_WAIT_DELAY_ms );
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211 /* Is the descriptor free after waiting for it? */
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212 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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214 /* Something has gone wrong. */
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215 prvResetEverything();
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218 /* Setup both descriptors to transmit the frame. */
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219 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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220 xTxDescriptors[ 0 ].bufsize = uip_len;
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221 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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222 xTxDescriptors[ 1 ].bufsize = uip_len;
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224 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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225 for use by the stack. */
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226 uip_buf = prvGetNextBuffer();
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228 /* Clear previous settings and go. */
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229 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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230 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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231 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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232 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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234 EDMAC.EDTRR.LONG = 0x00000001;
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236 /*-----------------------------------------------------------*/
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238 unsigned long ulEMACRead( void )
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240 unsigned long ulBytesReceived;
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242 ulBytesReceived = prvCheckRxFifoStatus();
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244 if( ulBytesReceived > 0 )
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246 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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247 pxCurrentRxDesc->status |= ACT;
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249 if( EDMAC.EDRRR.LONG == 0x00000000L )
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251 /* Restart Ethernet if it has stopped */
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252 EDMAC.EDRRR.LONG = 0x00000001L;
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255 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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256 the buffer that contains the received data. */
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257 prvReturnBuffer( uip_buf );
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259 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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261 /* Move onto the next buffer in the ring. */
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262 pxCurrentRxDesc = pxCurrentRxDesc->next;
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265 return ulBytesReceived;
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267 /*-----------------------------------------------------------*/
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269 long lEMACWaitForLink( void )
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273 /* Set the link status. */
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274 switch( phy_set_autonegotiate() )
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276 /* Half duplex link */
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277 case PHY_LINK_100H:
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278 ETHERC.ECMR.BIT.DM = 0;
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279 ETHERC.ECMR.BIT.RTM = 1;
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284 ETHERC.ECMR.BIT.DM = 0;
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285 ETHERC.ECMR.BIT.RTM = 0;
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290 /* Full duplex link */
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291 case PHY_LINK_100F:
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292 ETHERC.ECMR.BIT.DM = 1;
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293 ETHERC.ECMR.BIT.RTM = 1;
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298 ETHERC.ECMR.BIT.DM = 1;
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299 ETHERC.ECMR.BIT.RTM = 0;
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308 if( lReturn == pdPASS )
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310 /* Enable receive and transmit. */
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311 ETHERC.ECMR.BIT.RE = 1;
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312 ETHERC.ECMR.BIT.TE = 1;
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314 /* Enable EDMAC receive */
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315 EDMAC.EDRRR.LONG = 0x1;
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320 /*-----------------------------------------------------------*/
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322 static void prvInitialiseDescriptors( void )
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324 volatile ethfifo *pxDescriptor;
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327 for( x = 0; x < emacNUM_BUFFERS; x++ )
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329 /* Ensure none of the buffers are shown as in use at the start. */
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330 ucBufferInUse[ x ] = pdFALSE;
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333 /* Initialise the Rx descriptors. */
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334 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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336 pxDescriptor = &( xRxDescriptors[ x ] );
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337 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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339 pxDescriptor->bufsize = UIP_BUFSIZE;
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340 pxDescriptor->size = 0;
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341 pxDescriptor->status = ACT;
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342 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ x + 1 ];
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344 /* Mark this buffer as in use. */
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345 ucBufferInUse[ x ] = pdTRUE;
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348 /* The last descriptor points back to the start. */
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349 pxDescriptor->status |= DL;
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350 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ 0 ];
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352 /* Initialise the Tx descriptors. */
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353 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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355 pxDescriptor = &( xTxDescriptors[ x ] );
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357 /* A buffer is not allocated to the Tx descriptor until a send is
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358 actually required. */
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359 pxDescriptor->buf_p = NULL;
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361 pxDescriptor->bufsize = UIP_BUFSIZE;
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362 pxDescriptor->size = 0;
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363 pxDescriptor->status = 0;
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364 pxDescriptor->next = ( struct Descriptor * ) &xTxDescriptors[ x + 1 ];
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367 /* The last descriptor points back to the start. */
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368 pxDescriptor->status |= DL;
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369 pxDescriptor->next = ( struct Descriptor * ) &( xTxDescriptors[ 0 ] );
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371 /* Use the first Rx descriptor to start with. */
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372 pxCurrentRxDesc = ( struct Descriptor * ) &( xRxDescriptors[ 0 ] );
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374 /*-----------------------------------------------------------*/
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376 static unsigned char *prvGetNextBuffer( void )
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379 unsigned char *pucReturn = NULL;
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380 unsigned long ulAttempts = 0;
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382 while( pucReturn == NULL )
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384 /* Look through the buffers to find one that is not in use by
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386 for( x = 0; x < emacNUM_BUFFERS; x++ )
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388 if( ucBufferInUse[ x ] == pdFALSE )
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390 ucBufferInUse[ x ] = pdTRUE;
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391 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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396 /* Was a buffer found? */
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397 if( pucReturn == NULL )
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401 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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406 /* Wait then look again. */
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407 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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413 /*-----------------------------------------------------------*/
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415 static void prvReturnBuffer( unsigned char *pucBuffer )
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419 /* Return a buffer to the pool of free buffers. */
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420 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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422 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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424 ucBufferInUse[ ul ] = pdFALSE;
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429 /*-----------------------------------------------------------*/
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431 static void prvResetEverything( void )
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433 /* Temporary code just to see if this gets called. This function has not
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434 been implemented. */
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435 portDISABLE_INTERRUPTS();
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438 /*-----------------------------------------------------------*/
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440 static unsigned long prvCheckRxFifoStatus( void )
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442 unsigned long ulReturn = 0;
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444 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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446 /* Current descriptor is still active. */
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448 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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450 /* Frame error. Clear the error. */
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451 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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452 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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453 pxCurrentRxDesc->status |= ACT;
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454 pxCurrentRxDesc = pxCurrentRxDesc->next;
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456 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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458 /* Restart Ethernet if it has stopped. */
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459 EDMAC.EDRRR.LONG = 0x00000001UL;
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464 /* The descriptor contains a frame. Because of the size of the buffers
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465 the frame should always be complete. */
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466 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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468 ulReturn = pxCurrentRxDesc->size;
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472 /* Do not expect to get here. */
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473 prvResetEverything();
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479 /*-----------------------------------------------------------*/
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481 static void prvResetMAC( void )
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483 /* Ensure the EtherC and EDMAC are enabled. */
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484 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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485 vTaskDelay( 100 / portTICK_RATE_MS );
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487 EDMAC.EDMR.BIT.SWR = 1;
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489 /* Crude wait for reset to complete. */
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490 vTaskDelay( 500 / portTICK_RATE_MS );
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492 /*-----------------------------------------------------------*/
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494 static void prvConfigureEtherCAndEDMAC( void )
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496 /* Initialisation code taken from Renesas example project. */
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498 /* TODO: Check bit 5 */
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499 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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501 /* Set the EDMAC interrupt priority. */
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502 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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504 /* TODO: Check bit 5 */
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505 /* Enable interrupts of interest only. */
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506 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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507 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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508 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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511 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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512 #ifdef __RX_LITTLE_ENDIAN__
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513 EDMAC.EDMR.BIT.DE = 1;
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515 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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516 EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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517 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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518 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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519 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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520 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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522 /* Enable the interrupt... */
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523 _IEN( _ETHER_EINT ) = 1;
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525 /*-----------------------------------------------------------*/
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527 void vEMAC_ISR_Wrapper( void )
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529 /* This is a naked function. See the documentation for this port on
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530 http://www.FreeRTOS.org for more information on writing interrupts.
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532 /* Save the registers and enable interrupts. */
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533 portENTER_INTERRUPT();
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535 /* Perform the actual EMAC processing. */
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536 vEMAC_ISR_Handler();
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538 /* Restore the registers and return. */
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539 portEXIT_INTERRUPT();
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541 /*-----------------------------------------------------------*/
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543 static void vEMAC_ISR_Handler( void )
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545 unsigned long ul = EDMAC.EESR.LONG;
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546 long lHigherPriorityTaskWoken = pdFALSE;
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547 extern xSemaphoreHandle xEMACSemaphore;
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548 static long ulTxEndInts = 0;
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550 /* Has a Tx end occurred? */
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551 if( ul & emacTX_END_INTERRUPT )
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554 if( ulTxEndInts >= 2 )
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556 /* Only return the buffer to the pool once both Txes have completed. */
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557 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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560 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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563 /* Has an Rx end occurred? */
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564 if( ul & emacRX_END_INTERRUPT )
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566 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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567 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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568 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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569 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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