2 FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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5 ***************************************************************************
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7 * FreeRTOS tutorial books are available in pdf and paperback. *
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8 * Complete, revised, and edited pdf reference manuals are also *
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11 * Purchasing FreeRTOS documentation will not only help you, by *
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12 * ensuring you get running as quickly as possible and with an *
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13 * in-depth knowledge of how to use FreeRTOS, it will also help *
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14 * the FreeRTOS project to continue with its mission of providing *
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15 * professional grade, cross platform, de facto standard solutions *
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16 * for microcontrollers - completely free of charge! *
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18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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20 * Thank you for using FreeRTOS, and thank you for your support! *
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22 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 >>>NOTE<<< The modification to the GPL is included to allow you to
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31 distribute a combined work that includes FreeRTOS without being obliged to
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32 provide the source code for proprietary components outside of the FreeRTOS
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33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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54 /* Hardware specific includes. */
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55 #include <iorx62n.h>
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56 #include "typedefine.h"
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57 #include "r_ether.h"
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60 /* FreeRTOS includes. */
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61 #include "FreeRTOS.h"
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66 #include "net/uip.h"
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68 /* The time to wait between attempts to obtain a free buffer. */
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69 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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71 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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72 up on attempting to obtain a free buffer all together. */
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73 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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75 /* The number of Rx descriptors. */
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76 #define emacNUM_RX_DESCRIPTORS 8
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78 /* The number of Tx descriptors. When using uIP there is not point in having
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80 #define emacNUM_TX_BUFFERS 2
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82 /* The total number of EMAC buffers to allocate. */
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83 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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85 /* The time to wait for the Tx descriptor to become free. */
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86 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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88 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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90 #define emacTX_WAIT_ATTEMPTS ( 50 )
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92 /* Only Rx end and Tx end interrupts are used by this driver. */
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93 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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94 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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96 /*-----------------------------------------------------------*/
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98 /* The buffers and descriptors themselves. */
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99 #pragma data_alignment=32
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100 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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102 #pragma data_alignment=32
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103 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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105 #pragma data_alignment=32
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106 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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109 /* Used to indicate which buffers are free and which are in use. If an index
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110 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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111 the buffer is in use or about to be used. */
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112 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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114 /*-----------------------------------------------------------*/
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117 * Initialise both the Rx and Tx descriptors.
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119 static void prvInitialiseDescriptors( void );
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122 * Return a pointer to a free buffer within xEthernetBuffers.
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124 static unsigned char *prvGetNextBuffer( void );
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127 * Return a buffer to the list of free buffers.
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129 static void prvReturnBuffer( unsigned char *pucBuffer );
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132 * Examine the status of the next Rx FIFO to see if it contains new data.
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134 static unsigned long prvCheckRxFifoStatus( void );
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137 * Setup the microcontroller for communication with the PHY.
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139 static void prvResetMAC( void );
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142 * Configure the Ethernet interface peripherals.
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144 static void prvConfigureEtherCAndEDMAC( void );
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147 * Something has gone wrong with the descriptor usage. Reset all the buffers
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150 static void prvResetEverything( void );
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152 /*-----------------------------------------------------------*/
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154 /* Points to the Rx descriptor currently in use. */
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155 static volatile ethfifo *pxCurrentRxDesc = NULL;
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157 /* The buffer used by the uIP stack to both receive and send. This points to
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158 one of the Ethernet buffers when its actually in use. */
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159 unsigned char *uip_buf = NULL;
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161 /*-----------------------------------------------------------*/
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163 void vInitEmac( void )
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165 /* Software reset. */
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168 /* Set the Rx and Tx descriptors into their initial state. */
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169 prvInitialiseDescriptors();
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171 /* Set the MAC address into the ETHERC */
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172 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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173 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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174 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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175 ( unsigned long ) configMAC_ADDR3;
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177 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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178 ( unsigned long ) configMAC_ADDR5;
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180 /* Perform rest of interface hardware configuration. */
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181 prvConfigureEtherCAndEDMAC();
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183 /* Nothing received yet, so uip_buf points nowhere. */
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186 /* Initialize the PHY */
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189 /*-----------------------------------------------------------*/
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191 void vEMACWrite( void )
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195 /* Wait until the second transmission of the last packet has completed. */
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196 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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198 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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200 /* Descriptor is still active. */
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201 vTaskDelay( emacTX_WAIT_DELAY_ms );
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209 /* Is the descriptor free after waiting for it? */
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210 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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212 /* Something has gone wrong. */
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213 prvResetEverything();
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216 /* Setup both descriptors to transmit the frame. */
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217 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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218 xTxDescriptors[ 0 ].bufsize = uip_len;
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219 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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220 xTxDescriptors[ 1 ].bufsize = uip_len;
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222 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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223 for use by the stack. */
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224 uip_buf = prvGetNextBuffer();
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226 /* Clear previous settings and go. */
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227 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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228 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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229 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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230 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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232 EDMAC.EDTRR.LONG = 0x00000001;
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234 /*-----------------------------------------------------------*/
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236 unsigned long ulEMACRead( void )
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238 unsigned long ulBytesReceived;
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240 ulBytesReceived = prvCheckRxFifoStatus();
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242 if( ulBytesReceived > 0 )
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244 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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245 the buffer that contains the received data. */
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246 prvReturnBuffer( uip_buf );
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248 /* Point uip_buf to the data about ot be processed. */
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249 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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251 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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253 pxCurrentRxDesc->buf_p = ( char * ) prvGetNextBuffer();
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255 /* Prepare the descriptor to go again. */
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256 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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257 pxCurrentRxDesc->status |= ACT;
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259 /* Move onto the next buffer in the ring. */
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260 pxCurrentRxDesc = pxCurrentRxDesc->next;
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262 if( EDMAC.EDRRR.LONG == 0x00000000L )
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264 /* Restart Ethernet if it has stopped */
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265 EDMAC.EDRRR.LONG = 0x00000001L;
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269 return ulBytesReceived;
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271 /*-----------------------------------------------------------*/
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273 long lEMACWaitForLink( void )
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277 /* Set the link status. */
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278 switch( phy_set_autonegotiate() )
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280 /* Half duplex link */
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281 case PHY_LINK_100H:
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282 ETHERC.ECMR.BIT.DM = 0;
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283 ETHERC.ECMR.BIT.RTM = 1;
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288 ETHERC.ECMR.BIT.DM = 0;
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289 ETHERC.ECMR.BIT.RTM = 0;
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294 /* Full duplex link */
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295 case PHY_LINK_100F:
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296 ETHERC.ECMR.BIT.DM = 1;
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297 ETHERC.ECMR.BIT.RTM = 1;
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302 ETHERC.ECMR.BIT.DM = 1;
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303 ETHERC.ECMR.BIT.RTM = 0;
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312 if( lReturn == pdPASS )
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314 /* Enable receive and transmit. */
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315 ETHERC.ECMR.BIT.RE = 1;
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316 ETHERC.ECMR.BIT.TE = 1;
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318 /* Enable EDMAC receive */
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319 EDMAC.EDRRR.LONG = 0x1;
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324 /*-----------------------------------------------------------*/
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326 static void prvInitialiseDescriptors( void )
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328 volatile ethfifo *pxDescriptor;
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331 for( x = 0; x < emacNUM_BUFFERS; x++ )
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333 /* Ensure none of the buffers are shown as in use at the start. */
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334 ucBufferInUse[ x ] = pdFALSE;
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337 /* Initialise the Rx descriptors. */
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338 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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340 pxDescriptor = &( xRxDescriptors[ x ] );
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341 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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343 pxDescriptor->bufsize = UIP_BUFSIZE;
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344 pxDescriptor->size = 0;
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345 pxDescriptor->status = ACT;
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346 pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ x + 1 ];
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348 /* Mark this buffer as in use. */
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349 ucBufferInUse[ x ] = pdTRUE;
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352 /* The last descriptor points back to the start. */
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353 pxDescriptor->status |= DL;
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354 pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ 0 ];
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356 /* Initialise the Tx descriptors. */
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357 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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359 pxDescriptor = &( xTxDescriptors[ x ] );
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361 /* A buffer is not allocated to the Tx descriptor until a send is
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362 actually required. */
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363 pxDescriptor->buf_p = NULL;
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365 pxDescriptor->bufsize = UIP_BUFSIZE;
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366 pxDescriptor->size = 0;
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367 pxDescriptor->status = 0;
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368 pxDescriptor->next = ( ethfifo * ) &xTxDescriptors[ x + 1 ];
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371 /* The last descriptor points back to the start. */
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372 pxDescriptor->status |= DL;
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373 pxDescriptor->next = ( ethfifo * ) &( xTxDescriptors[ 0 ] );
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375 /* Use the first Rx descriptor to start with. */
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376 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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378 /*-----------------------------------------------------------*/
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380 static unsigned char *prvGetNextBuffer( void )
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383 unsigned char *pucReturn = NULL;
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384 unsigned long ulAttempts = 0;
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386 while( pucReturn == NULL )
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388 /* Look through the buffers to find one that is not in use by
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390 for( x = 0; x < emacNUM_BUFFERS; x++ )
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392 if( ucBufferInUse[ x ] == pdFALSE )
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394 ucBufferInUse[ x ] = pdTRUE;
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395 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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400 /* Was a buffer found? */
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401 if( pucReturn == NULL )
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405 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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410 /* Wait then look again. */
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411 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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417 /*-----------------------------------------------------------*/
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419 static void prvReturnBuffer( unsigned char *pucBuffer )
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423 /* Return a buffer to the pool of free buffers. */
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424 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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426 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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428 ucBufferInUse[ ul ] = pdFALSE;
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433 /*-----------------------------------------------------------*/
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435 static void prvResetEverything( void )
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437 /* Temporary code just to see if this gets called. This function has not
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438 been implemented. */
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439 portDISABLE_INTERRUPTS();
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442 /*-----------------------------------------------------------*/
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444 static unsigned long prvCheckRxFifoStatus( void )
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446 unsigned long ulReturn = 0;
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448 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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450 /* Current descriptor is still active. */
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452 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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454 /* Frame error. Clear the error. */
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455 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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456 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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457 pxCurrentRxDesc->status |= ACT;
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458 pxCurrentRxDesc = pxCurrentRxDesc->next;
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460 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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462 /* Restart Ethernet if it has stopped. */
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463 EDMAC.EDRRR.LONG = 0x00000001UL;
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468 /* The descriptor contains a frame. Because of the size of the buffers
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469 the frame should always be complete. */
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470 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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472 ulReturn = pxCurrentRxDesc->size;
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476 /* Do not expect to get here. */
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477 prvResetEverything();
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483 /*-----------------------------------------------------------*/
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485 static void prvResetMAC( void )
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487 /* Ensure the EtherC and EDMAC are enabled. */
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488 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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489 vTaskDelay( 100 / portTICK_RATE_MS );
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491 EDMAC.EDMR.BIT.SWR = 1;
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493 /* Crude wait for reset to complete. */
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494 vTaskDelay( 500 / portTICK_RATE_MS );
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496 /*-----------------------------------------------------------*/
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498 static void prvConfigureEtherCAndEDMAC( void )
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500 /* Initialisation code taken from Renesas example project. */
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502 /* TODO: Check bit 5 */
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503 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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505 /* Set the EDMAC interrupt priority. */
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506 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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508 /* TODO: Check bit 5 */
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509 /* Enable interrupts of interest only. */
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510 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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511 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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512 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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515 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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516 #if __LITTLE_ENDIAN__ == 1
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517 EDMAC.EDMR.BIT.DE = 1;
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519 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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520 EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] );/* Initialaize Tx Descriptor List Address */
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521 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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522 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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523 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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524 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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525 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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527 /* Enable the interrupt... */
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528 _IEN( _ETHER_EINT ) = 1;
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530 /*-----------------------------------------------------------*/
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532 #pragma vector = VECT_ETHER_EINT
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533 __interrupt void vEMAC_ISR_Handler( void )
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535 unsigned long ul = EDMAC.EESR.LONG;
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536 long lHigherPriorityTaskWoken = pdFALSE;
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537 extern xQueueHandle xEMACEventQueue;
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538 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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540 __enable_interrupt();
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542 /* Has a Tx end occurred? */
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543 if( ul & emacTX_END_INTERRUPT )
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545 /* Only return the buffer to the pool once both Txes have completed. */
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546 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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547 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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550 /* Has an Rx end occurred? */
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551 if( ul & emacRX_END_INTERRUPT )
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553 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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554 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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555 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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556 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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