2 FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.
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4 ***************************************************************************
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20 * and 8pm GMT (although please allow up to 24 hours in case of *
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21 * exceptional circumstances). Thank you for your support! *
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23 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 ***NOTE*** The exception to the GPL is included to allow you to distribute
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31 a combined work that includes FreeRTOS without being obliged to provide the
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32 source code for proprietary components outside of the FreeRTOS kernel.
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33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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54 /* Hardware specific includes. */
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55 #include "iodefine.h"
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56 #include "typedefine.h"
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57 #include "r_ether.h"
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60 /* FreeRTOS includes. */
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61 #include "FreeRTOS.h"
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66 #include "net/uip.h"
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68 /* The time to wait between attempts to obtain a free buffer. */
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69 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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71 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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72 up on attempting to obtain a free buffer all together. */
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73 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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75 /* The number of Rx descriptors. */
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76 #define emacNUM_RX_DESCRIPTORS 3
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78 /* The number of Tx descriptors. When using uIP there is not point in having
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80 #define emacNUM_TX_BUFFERS 2
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82 /* The total number of EMAC buffers to allocate. */
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83 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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85 /* The time to wait for the Tx descriptor to become free. */
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86 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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88 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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90 #define emacTX_WAIT_ATTEMPTS ( 5 )
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92 /* Only Rx end and Tx end interrupts are used by this driver. */
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93 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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94 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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96 /*-----------------------------------------------------------*/
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98 /* The buffers and descriptors themselves. */
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99 static union x_RX_Desc
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101 unsigned long long ullAlignmentVariable;
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102 ethfifo xDescriptorArray[ emacNUM_RX_DESCRIPTORS ];
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105 static union x_TX_Desc
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107 unsigned long long ullAlignmentVariable;
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108 ethfifo xDescriptorArray[ emacNUM_TX_BUFFERS ];
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111 static union x_ETH_Buffers
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113 unsigned long long ullAlignmentVariable;
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114 char xDataBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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115 } xEthernetBuffers;
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118 /* Used to indicate which buffers are free and which are in use. If an index
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119 contains 0 then the corresponding buffer in xEthernetBuffers.xDataBuffers is free, otherwise
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120 the buffer is in use or about to be used. */
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121 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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123 /*-----------------------------------------------------------*/
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126 * Initialise both the Rx and Tx descriptors.
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128 static void prvInitialiseDescriptors( void );
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131 * Return a pointer to a free buffer within xEthernetBuffers.xDataBuffers.
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133 static unsigned char *prvGetNextBuffer( void );
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136 * Return a buffer to the list of free buffers.
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138 static void prvReturnBuffer( unsigned char *pucBuffer );
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141 * Examine the status of the next Rx FIFO to see if it contains new data.
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143 static unsigned long prvCheckRxFifoStatus( void );
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146 * Setup the microcontroller for communication with the PHY.
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148 static void prvResetMAC( void );
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151 * Configure the Ethernet interface peripherals.
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153 static void prvConfigureEtherCAndEDMAC( void );
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156 * Something has gone wrong with the descriptor usage. Reset all the buffers
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159 static void prvResetEverything( void );
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161 /*-----------------------------------------------------------*/
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163 /* Points to the Rx descriptor currently in use. */
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164 static ethfifo *xCurrentRxDesc = NULL;
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166 /* The buffer used by the uIP stack to both receive and send. This points to
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167 one of the Ethernet buffers when its actually in use. */
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168 unsigned char *uip_buf = NULL;
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170 /*-----------------------------------------------------------*/
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172 void vInitEmac( void )
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174 /* Software reset. */
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177 /* Set the Rx and Tx descriptors into their initial state. */
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178 prvInitialiseDescriptors();
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180 /* Set the MAC address into the ETHERC */
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181 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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182 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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183 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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184 ( unsigned long ) configMAC_ADDR3;
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186 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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187 ( unsigned long ) configMAC_ADDR5;
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189 /* Perform rest of interface hardware configuration. */
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190 prvConfigureEtherCAndEDMAC();
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192 /* Nothing received yet, so uip_buf points nowhere. */
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195 /* Initialize the PHY */
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198 /*-----------------------------------------------------------*/
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200 void vEMACWrite( void )
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204 /* Wait until the second transmission of the last packet has completed. */
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205 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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207 if( ( xTxDescriptors.xDescriptorArray[ 1 ].status & ACT ) != 0 )
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209 /* Descriptor is still active. */
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210 vTaskDelay( emacTX_WAIT_DELAY_ms );
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218 /* Is the descriptor free after waiting for it? */
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219 if( ( xTxDescriptors.xDescriptorArray[ 1 ].status & ACT ) != 0 )
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221 /* Something has gone wrong. */
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222 prvResetEverything();
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225 /* Setup both descriptors to transmit the frame. */
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226 xTxDescriptors.xDescriptorArray[ 0 ].buf_p = ( char * ) uip_buf;
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227 xTxDescriptors.xDescriptorArray[ 0 ].bufsize = uip_len;
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228 xTxDescriptors.xDescriptorArray[ 1 ].buf_p = ( char * ) uip_buf;
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229 xTxDescriptors.xDescriptorArray[ 1 ].bufsize = uip_len;
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231 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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232 for use by the stack. */
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233 uip_buf = prvGetNextBuffer();
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235 /* Clear previous settings and go. */
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236 xTxDescriptors.xDescriptorArray[0].status &= ~( FP1 | FP0 );
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237 xTxDescriptors.xDescriptorArray[0].status |= ( FP1 | FP0 | ACT );
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238 xTxDescriptors.xDescriptorArray[1].status &= ~( FP1 | FP0 );
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239 xTxDescriptors.xDescriptorArray[1].status |= ( FP1 | FP0 | ACT );
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241 EDMAC.EDTRR.LONG = 0x00000001;
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243 /*-----------------------------------------------------------*/
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245 unsigned long ulEMACRead( void )
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247 unsigned long ulBytesReceived;
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249 ulBytesReceived = prvCheckRxFifoStatus();
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251 if( ulBytesReceived > 0 )
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253 xCurrentRxDesc->status &= ~( FP1 | FP0 );
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254 xCurrentRxDesc->status |= ACT;
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256 if( EDMAC.EDRRR.LONG == 0x00000000L )
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258 /* Restart Ethernet if it has stopped */
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259 EDMAC.EDRRR.LONG = 0x00000001L;
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262 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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263 the buffer that contains the received data. */
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264 prvReturnBuffer( uip_buf );
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266 uip_buf = ( void * ) xCurrentRxDesc->buf_p;
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268 /* Move onto the next buffer in the ring. */
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269 xCurrentRxDesc = xCurrentRxDesc->next;
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272 return ulBytesReceived;
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274 /*-----------------------------------------------------------*/
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276 long lEMACWaitForLink( void )
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280 /* Set the link status. */
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281 switch( phy_set_autonegotiate() )
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283 /* Half duplex link */
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284 case PHY_LINK_100H:
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286 ETHERC.ECMR.BIT.DM = 0;
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290 /* Full duplex link */
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291 case PHY_LINK_100F:
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293 ETHERC.ECMR.BIT.DM = 1;
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302 if( lReturn == pdPASS )
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304 /* Enable receive and transmit. */
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305 ETHERC.ECMR.BIT.RE = 1;
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306 ETHERC.ECMR.BIT.TE = 1;
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308 /* Enable EDMAC receive */
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309 EDMAC.EDRRR.LONG = 0x1;
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314 /*-----------------------------------------------------------*/
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316 static void prvInitialiseDescriptors( void )
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318 ethfifo *pxDescriptor;
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321 for( x = 0; x < emacNUM_BUFFERS; x++ )
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323 /* Ensure none of the buffers are shown as in use at the start. */
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324 ucBufferInUse[ x ] = pdFALSE;
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327 /* Initialise the Rx descriptors. */
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328 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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330 pxDescriptor = &( xRxDescriptors.xDescriptorArray[ x ] );
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331 pxDescriptor->buf_p = &( xEthernetBuffers.xDataBuffers[ x ][ 0 ] );
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333 pxDescriptor->bufsize = UIP_BUFSIZE;
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334 pxDescriptor->size = 0;
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335 pxDescriptor->status = ACT;
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336 pxDescriptor->next = &xRxDescriptors.xDescriptorArray[ x + 1 ];
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338 /* Mark this buffer as in use. */
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339 ucBufferInUse[ x ] = pdTRUE;
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342 /* The last descriptor points back to the start. */
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343 pxDescriptor->status |= DL;
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344 pxDescriptor->next = &xRxDescriptors.xDescriptorArray[ 0 ];
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346 /* Initialise the Tx descriptors. */
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347 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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349 pxDescriptor = &( xTxDescriptors.xDescriptorArray[ x ] );
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351 /* A buffer is not allocated to the Tx descriptor until a send is
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352 actually required. */
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353 pxDescriptor->buf_p = NULL;
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355 pxDescriptor->bufsize = UIP_BUFSIZE;
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356 pxDescriptor->size = 0;
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357 pxDescriptor->status = 0;
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358 pxDescriptor->next = &xTxDescriptors.xDescriptorArray[ x + 1 ];
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361 /* The last descriptor points back to the start. */
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362 pxDescriptor->status |= DL;
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363 pxDescriptor->next = &( xTxDescriptors.xDescriptorArray[ 0 ] );
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365 /* Use the first Rx descriptor to start with. */
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366 xCurrentRxDesc = &( xRxDescriptors.xDescriptorArray[ 0 ] );
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368 /*-----------------------------------------------------------*/
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370 static unsigned char *prvGetNextBuffer( void )
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373 unsigned char *pucReturn = NULL;
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374 unsigned long ulAttempts = 0;
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376 while( pucReturn == NULL )
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378 /* Look through the buffers to find one that is not in use by
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380 for( x = 0; x < emacNUM_BUFFERS; x++ )
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382 if( ucBufferInUse[ x ] == pdFALSE )
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384 ucBufferInUse[ x ] = pdTRUE;
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385 pucReturn = ( unsigned char * ) &( xEthernetBuffers.xDataBuffers[ x ][ 0 ] );
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390 /* Was a buffer found? */
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391 if( pucReturn == NULL )
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395 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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400 /* Wait then look again. */
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401 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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407 /*-----------------------------------------------------------*/
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409 static void prvReturnBuffer( unsigned char *pucBuffer )
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413 /* Return a buffer to the pool of free buffers. */
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414 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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416 if( &( xEthernetBuffers.xDataBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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418 ucBufferInUse[ ul ] = pdFALSE;
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423 /*-----------------------------------------------------------*/
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425 static void prvResetEverything( void )
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427 /* Temporary code just to see if this gets called. This function has not
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428 been implemented. */
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429 portDISABLE_INTERRUPTS();
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432 /*-----------------------------------------------------------*/
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434 static unsigned long prvCheckRxFifoStatus( void )
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436 unsigned long ulReturn = 0;
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438 if( ( xCurrentRxDesc->status & ACT ) != 0 )
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440 /* Current descriptor is still active. */
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442 else if( ( xCurrentRxDesc->status & FE ) != 0 )
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444 /* Frame error. Clear the error. */
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445 xCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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446 xCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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447 xCurrentRxDesc->status |= ACT;
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448 xCurrentRxDesc = xCurrentRxDesc->next;
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450 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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452 /* Restart Ethernet if it has stopped. */
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453 EDMAC.EDRRR.LONG = 0x00000001UL;
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458 /* The descriptor contains a frame. Because of the size of the buffers
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459 the frame should always be complete. */
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460 if( (xCurrentRxDesc->status & FP0) == FP0 )
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462 ulReturn = xCurrentRxDesc->size;
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466 /* Do not expect to get here. */
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467 prvResetEverything();
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473 /*-----------------------------------------------------------*/
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475 static void prvResetMAC( void )
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477 /* Ensure the EtherC and EDMAC are enabled. */
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478 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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479 vTaskDelay( 100 / portTICK_RATE_MS );
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481 EDMAC.EDMR.BIT.SWR = 1;
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483 /* Crude wait for reset to complete. */
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484 vTaskDelay( 500 / portTICK_RATE_MS );
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486 /*-----------------------------------------------------------*/
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488 static void prvConfigureEtherCAndEDMAC( void )
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490 /* Initialisation code taken from Renesas example project. */
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492 /* TODO: Check bit 5 */
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493 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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495 /* Set the EDMAC interrupt priority. */
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496 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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498 /* TODO: Check bit 5 */
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499 /* Enable interrupts of interest only. */
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500 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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501 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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502 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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505 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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506 EDMAC.RDLAR = ( void * ) xCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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507 EDMAC.TDLAR = &( xTxDescriptors.xDescriptorArray[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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508 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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509 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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510 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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511 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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513 /*-----------------------------------------------------------*/
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515 #pragma interrupt ( vEMAC_ISR_Handler( vect = VECT_ETHER_EINT, enable ) )
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516 void vEMAC_ISR_Handler( void )
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518 unsigned long ul = EDMAC.EESR.LONG;
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519 long lHigherPriorityTaskWoken = pdFALSE;
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520 extern xSemaphoreHandle xEMACSemaphore;
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521 static long ulTxEndInts = 0;
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523 /* Has a Tx end occurred? */
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524 if( ul & emacTX_END_INTERRUPT )
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527 if( ulTxEndInts >= 2 )
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529 /* Only return the buffer to the pool once both Txes have completed. */
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530 prvReturnBuffer( ( void * ) xTxDescriptors.xDescriptorArray[ 0 ].buf_p );
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533 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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536 /* Has an Rx end occurred? */
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537 if( ul & emacRX_END_INTERRUPT )
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539 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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540 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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541 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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542 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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