2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
5 ***************************************************************************
\r
7 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
8 * Complete, revised, and edited pdf reference manuals are also *
\r
11 * Purchasing FreeRTOS documentation will not only help you, by *
\r
12 * ensuring you get running as quickly as possible and with an *
\r
13 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
14 * the FreeRTOS project to continue with its mission of providing *
\r
15 * professional grade, cross platform, de facto standard solutions *
\r
16 * for microcontrollers - completely free of charge! *
\r
18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
20 * Thank you for using FreeRTOS, and thank you for your support! *
\r
22 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
31 distribute a combined work that includes FreeRTOS without being obliged to
\r
32 provide the source code for proprietary components outside of the FreeRTOS
\r
33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 ***************************************************************************
\r
46 * Having a problem? Start by reading the FAQ "My application does *
\r
47 * not run, what could be wrong? *
\r
49 * http://www.FreeRTOS.org/FAQHelp.html *
\r
51 ***************************************************************************
\r
54 http://www.FreeRTOS.org - Documentation, training, latest information,
\r
55 license and contact details.
\r
57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
58 including FreeRTOS+Trace - an indispensable productivity tool.
\r
60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
61 the code with commercial support, indemnification, and middleware, under
\r
62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
63 provide a safety engineered and independently SIL3 certified version under
\r
64 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
67 /* Hardware specific includes. */
\r
68 #include <iorx62n.h>
\r
69 #include "typedefine.h"
\r
70 #include "r_ether.h"
\r
73 /* FreeRTOS includes. */
\r
74 #include "FreeRTOS.h"
\r
79 #include "net/uip.h"
\r
81 /* The time to wait between attempts to obtain a free buffer. */
\r
82 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
\r
84 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
\r
85 up on attempting to obtain a free buffer all together. */
\r
86 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
\r
88 /* The number of Rx descriptors. */
\r
89 #define emacNUM_RX_DESCRIPTORS 8
\r
91 /* The number of Tx descriptors. When using uIP there is not point in having
\r
93 #define emacNUM_TX_BUFFERS 2
\r
95 /* The total number of EMAC buffers to allocate. */
\r
96 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
\r
98 /* The time to wait for the Tx descriptor to become free. */
\r
99 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
\r
101 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
\r
103 #define emacTX_WAIT_ATTEMPTS ( 50 )
\r
105 /* Only Rx end and Tx end interrupts are used by this driver. */
\r
106 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
\r
107 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
\r
109 /*-----------------------------------------------------------*/
\r
111 /* The buffers and descriptors themselves. */
\r
112 #pragma data_alignment=32
\r
113 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
\r
115 #pragma data_alignment=32
\r
116 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
\r
118 #pragma data_alignment=32
\r
119 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
\r
122 /* Used to indicate which buffers are free and which are in use. If an index
\r
123 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
\r
124 the buffer is in use or about to be used. */
\r
125 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
\r
127 /*-----------------------------------------------------------*/
\r
130 * Initialise both the Rx and Tx descriptors.
\r
132 static void prvInitialiseDescriptors( void );
\r
135 * Return a pointer to a free buffer within xEthernetBuffers.
\r
137 static unsigned char *prvGetNextBuffer( void );
\r
140 * Return a buffer to the list of free buffers.
\r
142 static void prvReturnBuffer( unsigned char *pucBuffer );
\r
145 * Examine the status of the next Rx FIFO to see if it contains new data.
\r
147 static unsigned long prvCheckRxFifoStatus( void );
\r
150 * Setup the microcontroller for communication with the PHY.
\r
152 static void prvResetMAC( void );
\r
155 * Configure the Ethernet interface peripherals.
\r
157 static void prvConfigureEtherCAndEDMAC( void );
\r
160 * Something has gone wrong with the descriptor usage. Reset all the buffers
\r
163 static void prvResetEverything( void );
\r
165 /*-----------------------------------------------------------*/
\r
167 /* Points to the Rx descriptor currently in use. */
\r
168 static volatile ethfifo *pxCurrentRxDesc = NULL;
\r
170 /* The buffer used by the uIP stack to both receive and send. This points to
\r
171 one of the Ethernet buffers when its actually in use. */
\r
172 unsigned char *uip_buf = NULL;
\r
174 /*-----------------------------------------------------------*/
\r
176 void vInitEmac( void )
\r
178 /* Software reset. */
\r
181 /* Set the Rx and Tx descriptors into their initial state. */
\r
182 prvInitialiseDescriptors();
\r
184 /* Set the MAC address into the ETHERC */
\r
185 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
\r
186 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
\r
187 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
\r
188 ( unsigned long ) configMAC_ADDR3;
\r
190 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
\r
191 ( unsigned long ) configMAC_ADDR5;
\r
193 /* Perform rest of interface hardware configuration. */
\r
194 prvConfigureEtherCAndEDMAC();
\r
196 /* Nothing received yet, so uip_buf points nowhere. */
\r
199 /* Initialize the PHY */
\r
202 /*-----------------------------------------------------------*/
\r
204 void vEMACWrite( void )
\r
208 /* Wait until the second transmission of the last packet has completed. */
\r
209 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
\r
211 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
213 /* Descriptor is still active. */
\r
214 vTaskDelay( emacTX_WAIT_DELAY_ms );
\r
222 /* Is the descriptor free after waiting for it? */
\r
223 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
225 /* Something has gone wrong. */
\r
226 prvResetEverything();
\r
229 /* Setup both descriptors to transmit the frame. */
\r
230 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
\r
231 xTxDescriptors[ 0 ].bufsize = uip_len;
\r
232 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
\r
233 xTxDescriptors[ 1 ].bufsize = uip_len;
\r
235 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
\r
236 for use by the stack. */
\r
237 uip_buf = prvGetNextBuffer();
\r
239 /* Clear previous settings and go. */
\r
240 xTxDescriptors[0].status &= ~( FP1 | FP0 );
\r
241 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
\r
242 xTxDescriptors[1].status &= ~( FP1 | FP0 );
\r
243 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
\r
245 EDMAC.EDTRR.LONG = 0x00000001;
\r
247 /*-----------------------------------------------------------*/
\r
249 unsigned long ulEMACRead( void )
\r
251 unsigned long ulBytesReceived;
\r
253 ulBytesReceived = prvCheckRxFifoStatus();
\r
255 if( ulBytesReceived > 0 )
\r
257 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
\r
258 the buffer that contains the received data. */
\r
259 prvReturnBuffer( uip_buf );
\r
261 /* Point uip_buf to the data about ot be processed. */
\r
262 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
\r
264 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
\r
266 pxCurrentRxDesc->buf_p = ( char * ) prvGetNextBuffer();
\r
268 /* Prepare the descriptor to go again. */
\r
269 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
\r
270 pxCurrentRxDesc->status |= ACT;
\r
272 /* Move onto the next buffer in the ring. */
\r
273 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
275 if( EDMAC.EDRRR.LONG == 0x00000000L )
\r
277 /* Restart Ethernet if it has stopped */
\r
278 EDMAC.EDRRR.LONG = 0x00000001L;
\r
282 return ulBytesReceived;
\r
284 /*-----------------------------------------------------------*/
\r
286 long lEMACWaitForLink( void )
\r
290 /* Set the link status. */
\r
291 switch( phy_set_autonegotiate() )
\r
293 /* Half duplex link */
\r
294 case PHY_LINK_100H:
\r
295 ETHERC.ECMR.BIT.DM = 0;
\r
296 ETHERC.ECMR.BIT.RTM = 1;
\r
301 ETHERC.ECMR.BIT.DM = 0;
\r
302 ETHERC.ECMR.BIT.RTM = 0;
\r
307 /* Full duplex link */
\r
308 case PHY_LINK_100F:
\r
309 ETHERC.ECMR.BIT.DM = 1;
\r
310 ETHERC.ECMR.BIT.RTM = 1;
\r
315 ETHERC.ECMR.BIT.DM = 1;
\r
316 ETHERC.ECMR.BIT.RTM = 0;
\r
325 if( lReturn == pdPASS )
\r
327 /* Enable receive and transmit. */
\r
328 ETHERC.ECMR.BIT.RE = 1;
\r
329 ETHERC.ECMR.BIT.TE = 1;
\r
331 /* Enable EDMAC receive */
\r
332 EDMAC.EDRRR.LONG = 0x1;
\r
337 /*-----------------------------------------------------------*/
\r
339 static void prvInitialiseDescriptors( void )
\r
341 volatile ethfifo *pxDescriptor;
\r
344 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
346 /* Ensure none of the buffers are shown as in use at the start. */
\r
347 ucBufferInUse[ x ] = pdFALSE;
\r
350 /* Initialise the Rx descriptors. */
\r
351 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
\r
353 pxDescriptor = &( xRxDescriptors[ x ] );
\r
354 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
\r
356 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
357 pxDescriptor->size = 0;
\r
358 pxDescriptor->status = ACT;
\r
359 pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ x + 1 ];
\r
361 /* Mark this buffer as in use. */
\r
362 ucBufferInUse[ x ] = pdTRUE;
\r
365 /* The last descriptor points back to the start. */
\r
366 pxDescriptor->status |= DL;
\r
367 pxDescriptor->next = ( ethfifo * ) &xRxDescriptors[ 0 ];
\r
369 /* Initialise the Tx descriptors. */
\r
370 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
\r
372 pxDescriptor = &( xTxDescriptors[ x ] );
\r
374 /* A buffer is not allocated to the Tx descriptor until a send is
\r
375 actually required. */
\r
376 pxDescriptor->buf_p = NULL;
\r
378 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
379 pxDescriptor->size = 0;
\r
380 pxDescriptor->status = 0;
\r
381 pxDescriptor->next = ( ethfifo * ) &xTxDescriptors[ x + 1 ];
\r
384 /* The last descriptor points back to the start. */
\r
385 pxDescriptor->status |= DL;
\r
386 pxDescriptor->next = ( ethfifo * ) &( xTxDescriptors[ 0 ] );
\r
388 /* Use the first Rx descriptor to start with. */
\r
389 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
\r
391 /*-----------------------------------------------------------*/
\r
393 static unsigned char *prvGetNextBuffer( void )
\r
396 unsigned char *pucReturn = NULL;
\r
397 unsigned long ulAttempts = 0;
\r
399 while( pucReturn == NULL )
\r
401 /* Look through the buffers to find one that is not in use by
\r
403 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
405 if( ucBufferInUse[ x ] == pdFALSE )
\r
407 ucBufferInUse[ x ] = pdTRUE;
\r
408 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
\r
413 /* Was a buffer found? */
\r
414 if( pucReturn == NULL )
\r
418 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
\r
423 /* Wait then look again. */
\r
424 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
\r
430 /*-----------------------------------------------------------*/
\r
432 static void prvReturnBuffer( unsigned char *pucBuffer )
\r
436 /* Return a buffer to the pool of free buffers. */
\r
437 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
\r
439 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
\r
441 ucBufferInUse[ ul ] = pdFALSE;
\r
446 /*-----------------------------------------------------------*/
\r
448 static void prvResetEverything( void )
\r
450 /* Temporary code just to see if this gets called. This function has not
\r
451 been implemented. */
\r
452 portDISABLE_INTERRUPTS();
\r
455 /*-----------------------------------------------------------*/
\r
457 static unsigned long prvCheckRxFifoStatus( void )
\r
459 unsigned long ulReturn = 0;
\r
461 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
\r
463 /* Current descriptor is still active. */
\r
465 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
\r
467 /* Frame error. Clear the error. */
\r
468 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
\r
469 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
\r
470 pxCurrentRxDesc->status |= ACT;
\r
471 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
473 if( EDMAC.EDRRR.LONG == 0x00000000UL )
\r
475 /* Restart Ethernet if it has stopped. */
\r
476 EDMAC.EDRRR.LONG = 0x00000001UL;
\r
481 /* The descriptor contains a frame. Because of the size of the buffers
\r
482 the frame should always be complete. */
\r
483 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
\r
485 ulReturn = pxCurrentRxDesc->size;
\r
489 /* Do not expect to get here. */
\r
490 prvResetEverything();
\r
496 /*-----------------------------------------------------------*/
\r
498 static void prvResetMAC( void )
\r
500 /* Ensure the EtherC and EDMAC are enabled. */
\r
501 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
\r
502 vTaskDelay( 100 / portTICK_RATE_MS );
\r
504 EDMAC.EDMR.BIT.SWR = 1;
\r
506 /* Crude wait for reset to complete. */
\r
507 vTaskDelay( 500 / portTICK_RATE_MS );
\r
509 /*-----------------------------------------------------------*/
\r
511 static void prvConfigureEtherCAndEDMAC( void )
\r
513 /* Initialisation code taken from Renesas example project. */
\r
515 /* TODO: Check bit 5 */
\r
516 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
\r
518 /* Set the EDMAC interrupt priority. */
\r
519 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
\r
521 /* TODO: Check bit 5 */
\r
522 /* Enable interrupts of interest only. */
\r
523 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
\r
524 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
\r
525 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
\r
528 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
\r
529 #if __LITTLE_ENDIAN__ == 1
\r
530 EDMAC.EDMR.BIT.DE = 1;
\r
532 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
\r
533 EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] );/* Initialaize Tx Descriptor List Address */
\r
534 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
\r
535 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
\r
536 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
\r
537 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
\r
538 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
\r
540 /* Enable the interrupt... */
\r
541 _IEN( _ETHER_EINT ) = 1;
\r
543 /*-----------------------------------------------------------*/
\r
545 #pragma vector = VECT_ETHER_EINT
\r
546 __interrupt void vEMAC_ISR_Handler( void )
\r
548 unsigned long ul = EDMAC.EESR.LONG;
\r
549 long lHigherPriorityTaskWoken = pdFALSE;
\r
550 extern xQueueHandle xEMACEventQueue;
\r
551 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
\r
553 __enable_interrupt();
\r
555 /* Has a Tx end occurred? */
\r
556 if( ul & emacTX_END_INTERRUPT )
\r
558 /* Only return the buffer to the pool once both Txes have completed. */
\r
559 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
\r
560 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
\r
563 /* Has an Rx end occurred? */
\r
564 if( ul & emacRX_END_INTERRUPT )
\r
566 /* Make sure the Ethernet task is not blocked waiting for a packet. */
\r
567 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
\r
568 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
\r
569 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
\r