git.sur5r.net Git - freertos/blob - Demo/SuperH_SH7216_Renesas/RTOSDemo/regtest.src

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  53 \r
  54         .import _pxCurrentTCB\r
  55         .import _vTaskSwitchContext\r
  56         .import _ulRegTest1CycleCount\r
  57         .import _ulRegTest2CycleCount\r
  58 \r
  59         .export _vRegTest1Task\r
  60         .export _vRegTest2Task\r
  61 \r
  62     .section    P\r
  63         \r
  64 _vRegTest1Task:\r
  65 \r
  66         mov             #3, r2\r
  67         mov             #4, r3\r
  68         mov             #5, r4\r
  69         mov             #6, r5\r
  70         mov             #7, r6\r
  71         mov             #8, r7\r
  72         mov             #9, r8\r
  73         mov             #10, r9\r
  74         mov             #11, r10\r
  75         mov             #12, r11\r
  76         mov             #13, r12\r
  77         mov             #14, r13\r
  78 \r
  79         mov             #15, r0\r
  80         lds             r0, macl\r
  81         mov             #16, r0\r
  82         lds             r0, mach\r
  83         mov             #17, r0\r
  84         ldc             r0, gbr\r
  85         \r
  86 _vRegTest1Loop:\r
  87 \r
  88         ; Reset r1 which was used in the tests.\r
  89         mov             #2, r1\r
  90         \r
  91         mov             #2, r0\r
  92         cmp/eq  r0, r1\r
  93         bf              _vRegTestError\r
  94         \r
  95         mov             #3, r0\r
  96         cmp/eq  r0, r2\r
  97         bf              _vRegTestError\r
  98 \r
  99         mov             #4, r0\r
 100         cmp/eq  r0, r3\r
 101         bf              _vRegTestError\r
 102 \r
 103         mov             #5, r0\r
 104         cmp/eq  r0, r4\r
 105         bf              _vRegTestError\r
 106 \r
 107         mov             #6, r0\r
 108         cmp/eq  r0, r5\r
 109         bf              _vRegTestError\r
 110 \r
 111         mov             #7, r0\r
 112         cmp/eq  r0, r6\r
 113         bf              _vRegTestError\r
 114 \r
 115         mov             #8, r0\r
 116         cmp/eq  r0, r7\r
 117         bf              _vRegTestError\r
 118 \r
 119         mov             #9, r0\r
 120         cmp/eq  r0, r8\r
 121         bf              _vRegTestError\r
 122 \r
 123         mov             #10, r0\r
 124         cmp/eq  r0, r9\r
 125         bf              _vRegTestError\r
 126 \r
 127         mov             #11, r0\r
 128         cmp/eq  r0, r10\r
 129         bf              _vRegTestError\r
 130 \r
 131         mov             #12, r0\r
 132         cmp/eq  r0, r11\r
 133         bf              _vRegTestError\r
 134 \r
 135         mov             #13, r0\r
 136         cmp/eq  r0, r12\r
 137         bf              _vRegTestError\r
 138 \r
 139         mov             #14, r0\r
 140         cmp/eq  r0, r13\r
 141         bf              _vRegTestError\r
 142 \r
 143         sts             macl, r0\r
 144         mov             #15, r1\r
 145         cmp/eq  r0, r1\r
 146         bf              _vRegTestError\r
 147 \r
 148         sts             mach, r0\r
 149         mov             #16, r1\r
 150         cmp/eq  r0, r1\r
 151         bf              _vRegTestError\r
 152 \r
 153         stc             gbr, r0\r
 154         mov             #17, r1\r
 155         cmp/eq  r0, r1\r
 156         bf              _vRegTestError\r
 157 \r
 158         mov.l   #_ulRegTest1CycleCount, r0\r
 159         mov.l   @r0, r1\r
 160         add             #1, r1\r
 161         mov.l   r1, @r0\r
 162 \r
 163         bra             _vRegTest1Task\r
 164         nop\r
 165 \r
 166 _vRegTest2Task:\r
 167 \r
 168         trapa   #33\r
 169         bra             _vRegTest2Task\r
 170         nop\r
 171         \r
 172 _vRegTestError:\r
 173         bra             _vRegTestError\r
 174 \r
 175         .end\r
 176                 \r