1 /***********************************************************************/
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3 /* FILE :vecttbl.c */
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4 /* DATE :Sun, Dec 27, 2009 */
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5 /* DESCRIPTION :Initialize of Vector Table */
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6 /* CPU TYPE :Other */
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8 /* This file is generated by Renesas Project Generator (Ver.4.16). */
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10 /***********************************************************************/
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16 #pragma section VECTTBL
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18 void *RESET_Vectors[] = {
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19 //;<<VECTOR DATA START (POWER ON RESET)>>
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20 //;0 Power On Reset PC
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21 (void*) PowerON_Reset_PC,
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22 //;<<VECTOR DATA END (POWER ON RESET)>>
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23 // 1 Power On Reset SP
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25 //;<<VECTOR DATA START (MANUAL RESET)>>
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26 //;2 Manual Reset PC
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27 (void*) Manual_Reset_PC,
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28 //;<<VECTOR DATA END (MANUAL RESET)>>
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29 // 3 Manual Reset SP
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33 #pragma section INTTBL
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34 void *INT_Vectors[] = {
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36 (void*) INT_Illegal_code,
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40 (void*) INT_Illegal_slot,
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45 // 9 CPU Address error
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46 (void*) INT_CPU_Address,
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47 // 10 DMAC Address error
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48 (void*) INT_DMAC_Address,
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51 // 12 User breakpoint trap
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52 (void*) INT_User_Break,
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57 // 15 Register bank over
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58 (void*) INT_Bank_Overflow,
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59 // 16 Register bank under
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60 (void*) INT_Bank_Underflow,
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62 (void*) INT_Divide_by_Zero,
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64 (void*) INT_Divide_Overflow,
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91 // 32 TRAPA (User Vecter)
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92 (void*) INT_TRAPA32,
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93 // 33 TRAPA (User Vecter)
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94 (void*) INT_TRAPA33,
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95 // 34 TRAPA (User Vecter)
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96 (void*) INT_TRAPA34,
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97 // 35 TRAPA (User Vecter)
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98 (void*) INT_TRAPA35,
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99 // 36 TRAPA (User Vecter)
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100 (void*) INT_TRAPA36,
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101 // 37 TRAPA (User Vecter)
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102 (void*) INT_TRAPA37,
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103 // 38 TRAPA (User Vecter)
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104 (void*) INT_TRAPA38,
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105 // 39 TRAPA (User Vecter)
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106 (void*) INT_TRAPA39,
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107 // 40 TRAPA (User Vecter)
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108 (void*) INT_TRAPA40,
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109 // 41 TRAPA (User Vecter)
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110 (void*) INT_TRAPA41,
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111 // 42 TRAPA (User Vecter)
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112 (void*) INT_TRAPA42,
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113 // 43 TRAPA (User Vecter)
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114 (void*) INT_TRAPA43,
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115 // 44 TRAPA (User Vecter)
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116 (void*) INT_TRAPA44,
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117 // 45 TRAPA (User Vecter)
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118 (void*) INT_TRAPA45,
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119 // 46 TRAPA (User Vecter)
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120 (void*) INT_TRAPA46,
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121 // 47 TRAPA (User Vecter)
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122 (void*) INT_TRAPA47,
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123 // 48 TRAPA (User Vecter)
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124 (void*) INT_TRAPA48,
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125 // 49 TRAPA (User Vecter)
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126 (void*) INT_TRAPA49,
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127 // 50 TRAPA (User Vecter)
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128 (void*) INT_TRAPA50,
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129 // 51 TRAPA (User Vecter)
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130 (void*) INT_TRAPA51,
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131 // 52 TRAPA (User Vecter)
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132 (void*) INT_TRAPA52,
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133 // 53 TRAPA (User Vecter)
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134 (void*) INT_TRAPA53,
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135 // 54 TRAPA (User Vecter)
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136 (void*) INT_TRAPA54,
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137 // 55 TRAPA (User Vecter)
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138 (void*) INT_TRAPA55,
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139 // 56 TRAPA (User Vecter)
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140 (void*) INT_TRAPA56,
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141 // 57 TRAPA (User Vecter)
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142 (void*) INT_TRAPA57,
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143 // 58 TRAPA (User Vecter)
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144 (void*) INT_TRAPA58,
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145 // 59 TRAPA (User Vecter)
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146 (void*) INT_TRAPA59,
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147 // 60 TRAPA (User Vecter)
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148 (void*) INT_TRAPA60,
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149 // 61 TRAPA (User Vecter)
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150 (void*) INT_TRAPA61,
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151 // 62 TRAPA (User Vecter)
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152 (void*) INT_TRAPA62,
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153 // 63 TRAPA (User Vecter)
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154 (void*) INT_TRAPA63,
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155 // 64 Interrupt IRQ0
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157 // 65 Interrupt IRQ1
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159 // 66 Interrupt IRQ2
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161 // 67 Interrupt IRQ3
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163 // 68 Interrupt IRQ4
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165 // 69 Interrupt IRQ5
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167 // 70 Interrupt IRQ6
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169 // 71 Interrupt IRQ7
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187 // 80 Interrupt PINT0
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189 // 81 Interrupt PINT1
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191 // 82 Interrupt PINT2
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193 // 83 Interrupt PINT3
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195 // 84 Interrupt PINT4
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197 // 85 Interrupt PINT5
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199 // 86 Interrupt PINT6
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201 // 87 Interrupt PINT7
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210 (void*) INT_ROM_FIFE,
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212 (void*) INT_AD_ADI0,
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220 (void*) INT_AD_ADI1,
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235 // 104 RCANET0 ERS_0
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236 (void*) INT_RCANET0_ERS_0,
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237 // 105 RCANET0 OVR_0
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238 (void*) INT_RCANET0_OVR_0,
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239 // 106 RCANET0 RM01_0
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240 (void*) INT_RCANET0_RM01_0,
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241 // 107 RCANET0 SLE_0
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242 (void*) INT_RCANET0_SLE_0,
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244 (void*) INT_DMAC0_DEI0,
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246 (void*) INT_DMAC0_HEI0,
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252 (void*) INT_DMAC1_DEI1,
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254 (void*) INT_DMAC1_HEI1,
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260 (void*) INT_DMAC2_DEI2,
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262 (void*) INT_DMAC2_HEI2,
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268 (void*) INT_DMAC3_DEI3,
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270 (void*) INT_DMAC3_HEI3,
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276 (void*) INT_DMAC4_DEI4,
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278 (void*) INT_DMAC4_HEI4,
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284 (void*) INT_DMAC5_DEI5,
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286 (void*) INT_DMAC5_HEI5,
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292 (void*) INT_DMAC6_DEI6,
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294 (void*) INT_DMAC6_HEI6,
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300 (void*) INT_DMAC7_DEI7,
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302 (void*) INT_DMAC7_HEI7,
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308 (void*) INT_CMT_CMI0,
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316 (void*) INT_CMT_CMI1,
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324 (void*) INT_BSC_CMTI,
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328 (void*) INT_USB_EP4FULL,
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329 // 151 USB EP5EMPTY
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330 (void*) INT_USB_EP5EMPTY,
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332 (void*) INT_WDT_ITI,
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333 // 153 E-DMAC EINT0
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334 (void*) INT_EDMAC_EINT0,
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336 (void*) INT_USB_EP1FULL,
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337 // 155 USB EP2EMPTY
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338 (void*) INT_USB_EP2EMPTY,
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339 // 156 MTU2 MTU0 TGI0A
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340 (void*) INT_MTU2_MTU0_TGI0A,
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341 // 157 MTU2 MTU0 TGI0B
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342 (void*) INT_MTU2_MTU0_TGI0B,
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343 // 158 MTU2 MTU0 TGI0C
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344 (void*) INT_MTU2_MTU0_TGI0C,
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345 // 159 MTU2 MTU0 TGI0D
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346 (void*) INT_MTU2_MTU0_TGI0D,
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347 // 160 MTU2 MTU0 TGI0V
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348 (void*) INT_MTU2_MTU0_TGI0V,
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349 // 161 MTU2 MTU0 TGI0E
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350 (void*) INT_MTU2_MTU0_TGI0E,
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351 // 162 MTU2 MTU0 TGI0F
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352 (void*) INT_MTU2_MTU0_TGI0F,
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355 // 164 MTU2 MTU1 TGI1A
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356 (void*) INT_MTU2_MTU1_TGI1A,
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357 // 165 MTU2 MTU1 TGI1B
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358 (void*) INT_MTU2_MTU1_TGI1B,
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363 // 168 MTU2 MTU1 TGI1V
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364 (void*) INT_MTU2_MTU1_TGI1V,
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365 // 169 MTU2 MTU1 TGI1U
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366 (void*) INT_MTU2_MTU1_TGI1U,
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371 // 172 MTU2 MTU2 TGI2A
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372 (void*) INT_MTU2_MTU2_TGI2A,
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373 // 173 MTU2 MTU2 TGI2B
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374 (void*) INT_MTU2_MTU2_TGI2B,
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379 // 176 MTU2 MTU2 TGI2V
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380 (void*) INT_MTU2_MTU2_TGI2V,
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381 // 177 MTU2 MTU2 TGI2U
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382 (void*) INT_MTU2_MTU2_TGI2U,
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387 // 180 MTU2 MTU3 TGI3A
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388 (void*) INT_MTU2_MTU3_TGI3A,
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389 // 181 MTU2 MTU3 TGI3B
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390 (void*) INT_MTU2_MTU3_TGI3B,
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391 // 182 MTU2 MTU3 TGI3C
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392 (void*) INT_MTU2_MTU3_TGI3C,
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393 // 183 MTU2 MTU3 TGI3D
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394 (void*) INT_MTU2_MTU3_TGI3D,
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395 // 184 MTU2 MTU3 TGI3V
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396 (void*) INT_MTU2_MTU3_TGI3V,
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403 // 188 MTU2 MTU4 TGI4A
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404 (void*) INT_MTU2_MTU4_TGI4A,
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405 // 189 MTU2 MTU4 TGI4B
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406 (void*) INT_MTU2_MTU4_TGI4B,
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407 // 190 MTU2 MTU4 TGI4C
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408 (void*) INT_MTU2_MTU4_TGI4C,
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409 // 191 MTU2 MTU4 TGI4D
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410 (void*) INT_MTU2_MTU4_TGI4D,
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411 // 192 MTU2 MTU4 TGI4V
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412 (void*) INT_MTU2_MTU4_TGI4V,
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419 // 196 MTU2 MTU5 TGI5U
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420 (void*) INT_MTU2_MTU5_TGI5U,
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421 // 197 MTU2 MTU5 TGI5V
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422 (void*) INT_MTU2_MTU5_TGI5V,
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423 // 198 MTU2 MTU5 TGI5W
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424 (void*) INT_MTU2_MTU5_TGI5W,
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428 (void*) INT_POE2_OEI1,
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430 (void*) INT_POE2_OEI2,
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435 // 204 MTU2S MTU3S TGI3A
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436 (void*) INT_MTU2S_MTU3S_TGI3A,
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437 // 205 MTU2S MTU3S TGI3B
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438 (void*) INT_MTU2S_MTU3S_TGI3B,
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439 // 206 MTU2S MTU3S TGI3C
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440 (void*) INT_MTU2S_MTU3S_TGI3C,
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441 // 207 MTU2S MTU3S TGI3D
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442 (void*) INT_MTU2S_MTU3S_TGI3D,
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443 // 208 MTU2S MTU3S TGI3V
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444 (void*) INT_MTU2S_MTU3S_TGI3V,
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451 // 212 MTU2S MTU4S TGI4A
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452 (void*) INT_MTU2S_MTU4S_TGI4A,
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453 // 213 MTU2S MTU4S TGI4B
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454 (void*) INT_MTU2S_MTU4S_TGI4B,
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455 // 214 MTU2S MTU4S TGI4C
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456 (void*) INT_MTU2S_MTU4S_TGI4C,
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457 // 215 MTU2S MTU4S TGI4D
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458 (void*) INT_MTU2S_MTU4S_TGI4D,
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459 // 216 MTU2S MTU4S TGI4V
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460 (void*) INT_MTU2S_MTU4S_TGI4V,
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467 // 220 MTU2S MTU5S TGI5U
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468 (void*) INT_MTU2S_MTU5S_TGI5U,
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469 // 221 MTU2S MTU5S TGI5V
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470 (void*) INT_MTU2S_MTU5S_TGI5V,
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471 // 222 MTU2S MTU5S TGI5W
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472 (void*) INT_MTU2S_MTU5S_TGI5W,
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476 (void*) INT_POE2_OEI3,
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480 (void*) INT_USB_USI0,
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482 (void*) INT_USB_USI1,
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484 (void*) INT_IIC3_STPI,
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486 (void*) INT_IIC3_NAKI,
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488 (void*) INT_IIC3_RXI,
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490 (void*) INT_IIC3_TXI,
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492 (void*) INT_IIC3_TEI,
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494 (void*) INT_RSPI_SPERI,
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496 (void*) INT_RSPI_SPRXI,
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498 (void*) INT_RSPI_SPTXI,
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499 // 236 SCI SCI4 ERI4
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500 (void*) INT_SCI_SCI4_ERI4,
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501 // 237 SCI SCI4 RXI4
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502 (void*) INT_SCI_SCI4_RXI4,
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503 // 238 SCI SCI4 TXI4
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504 (void*) INT_SCI_SCI4_TXI4,
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505 // 239 SCI SCI4 TEI4
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506 (void*) INT_SCI_SCI4_TEI4,
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507 // 240 SCI SCI0 ERI0
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508 (void*) INT_SCI_SCI0_ERI0,
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509 // 241 SCI SCI0 RXI0
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510 (void*) INT_SCI_SCI0_RXI0,
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511 // 242 SCI SCI0 TXI0
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512 (void*) INT_SCI_SCI0_TXI0,
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513 // 243 SCI SCI0 TEI0
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514 (void*) INT_SCI_SCI0_TEI0,
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515 // 244 SCI SCI1 ERI1
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516 (void*) INT_SCI_SCI1_ERI1,
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517 // 245 SCI SCI1 RXI1
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518 (void*) INT_SCI_SCI1_RXI1,
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519 // 246 SCI SCI1 TXI1
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520 (void*) INT_SCI_SCI1_TXI1,
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521 // 247 SCI SCI1 TEI1
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522 (void*) INT_SCI_SCI1_TEI1,
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523 // 248 SCI SCI2 ERI2
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524 (void*) INT_SCI_SCI2_ERI2,
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525 // 249 SCI SCI2 RXI2
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526 (void*) INT_SCI_SCI2_RXI2,
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527 // 250 SCI SCI2 TXI2
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528 (void*) INT_SCI_SCI2_TXI2,
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529 // 251 SCI SCI2 TEI2
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530 (void*) INT_SCI_SCI2_TEI2,
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531 // 252 SCIF SCIF3 BRI3
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532 (void*) INT_SCIF_SCIF3_BRI3,
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533 // 253 SCIF SCIF3 ERI3
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534 (void*) INT_SCIF_SCIF3_ERI3,
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535 // 254 SCIF SCIF3 RXI3
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536 (void*) INT_SCIF_SCIF3_RXI3,
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537 // 255 SCIF SCIF3 TXI3
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538 (void*) INT_SCIF_SCIF3_TXI3,
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