1 /***********************************************************************/
\r
3 /* FILE :vecttbl.c */
\r
4 /* DATE :Sun, Dec 27, 2009 */
\r
5 /* DESCRIPTION :Initialize of Vector Table */
\r
6 /* CPU TYPE :Other */
\r
8 /* This file is generated by Renesas Project Generator (Ver.4.16). */
\r
10 /***********************************************************************/
\r
16 extern void vPortStartFirstTask( void );
\r
17 extern void vPortYieldHandler( void );
\r
18 extern void vPortPreemptiveTick( void );
\r
20 #pragma section VECTTBL
\r
22 void *RESET_Vectors[] = {
\r
23 //;<<VECTOR DATA START (POWER ON RESET)>>
\r
24 //;0 Power On Reset PC
\r
25 (void*) PowerON_Reset_PC,
\r
26 //;<<VECTOR DATA END (POWER ON RESET)>>
\r
27 // 1 Power On Reset SP
\r
29 //;<<VECTOR DATA START (MANUAL RESET)>>
\r
30 //;2 Manual Reset PC
\r
31 (void*) Manual_Reset_PC,
\r
32 //;<<VECTOR DATA END (MANUAL RESET)>>
\r
33 // 3 Manual Reset SP
\r
37 #pragma section INTTBL
\r
38 void *INT_Vectors[] = {
\r
40 (void*) INT_Illegal_code,
\r
44 (void*) INT_Illegal_slot,
\r
49 // 9 CPU Address error
\r
50 (void*) INT_CPU_Address,
\r
51 // 10 DMAC Address error
\r
52 (void*) INT_DMAC_Address,
\r
55 // 12 User breakpoint trap
\r
56 (void*) INT_User_Break,
\r
61 // 15 Register bank over
\r
62 (void*) INT_Bank_Overflow,
\r
63 // 16 Register bank under
\r
64 (void*) INT_Bank_Underflow,
\r
66 (void*) INT_Divide_by_Zero,
\r
68 (void*) INT_Divide_Overflow,
\r
95 // 32 TRAPA (User Vecter)
\r
96 // (void*) INT_TRAPA32,
\r
97 (void*) vPortStartFirstTask,
\r
98 // 33 TRAPA (User Vecter)
\r
99 // (void*) INT_TRAPA33,
\r
100 (void*) vPortYieldHandler,
\r
101 // 34 TRAPA (User Vecter)
\r
102 (void*) INT_TRAPA34,
\r
103 // 35 TRAPA (User Vecter)
\r
104 (void*) INT_TRAPA35,
\r
105 // 36 TRAPA (User Vecter)
\r
106 (void*) INT_TRAPA36,
\r
107 // 37 TRAPA (User Vecter)
\r
108 (void*) INT_TRAPA37,
\r
109 // 38 TRAPA (User Vecter)
\r
110 (void*) INT_TRAPA38,
\r
111 // 39 TRAPA (User Vecter)
\r
112 (void*) INT_TRAPA39,
\r
113 // 40 TRAPA (User Vecter)
\r
114 (void*) INT_TRAPA40,
\r
115 // 41 TRAPA (User Vecter)
\r
116 (void*) INT_TRAPA41,
\r
117 // 42 TRAPA (User Vecter)
\r
118 (void*) INT_TRAPA42,
\r
119 // 43 TRAPA (User Vecter)
\r
120 (void*) INT_TRAPA43,
\r
121 // 44 TRAPA (User Vecter)
\r
122 (void*) INT_TRAPA44,
\r
123 // 45 TRAPA (User Vecter)
\r
124 (void*) INT_TRAPA45,
\r
125 // 46 TRAPA (User Vecter)
\r
126 (void*) INT_TRAPA46,
\r
127 // 47 TRAPA (User Vecter)
\r
128 (void*) INT_TRAPA47,
\r
129 // 48 TRAPA (User Vecter)
\r
130 (void*) INT_TRAPA48,
\r
131 // 49 TRAPA (User Vecter)
\r
132 (void*) INT_TRAPA49,
\r
133 // 50 TRAPA (User Vecter)
\r
134 (void*) INT_TRAPA50,
\r
135 // 51 TRAPA (User Vecter)
\r
136 (void*) INT_TRAPA51,
\r
137 // 52 TRAPA (User Vecter)
\r
138 (void*) INT_TRAPA52,
\r
139 // 53 TRAPA (User Vecter)
\r
140 (void*) INT_TRAPA53,
\r
141 // 54 TRAPA (User Vecter)
\r
142 (void*) INT_TRAPA54,
\r
143 // 55 TRAPA (User Vecter)
\r
144 (void*) INT_TRAPA55,
\r
145 // 56 TRAPA (User Vecter)
\r
146 (void*) INT_TRAPA56,
\r
147 // 57 TRAPA (User Vecter)
\r
148 (void*) INT_TRAPA57,
\r
149 // 58 TRAPA (User Vecter)
\r
150 (void*) INT_TRAPA58,
\r
151 // 59 TRAPA (User Vecter)
\r
152 (void*) INT_TRAPA59,
\r
153 // 60 TRAPA (User Vecter)
\r
154 (void*) INT_TRAPA60,
\r
155 // 61 TRAPA (User Vecter)
\r
156 (void*) INT_TRAPA61,
\r
157 // 62 TRAPA (User Vecter)
\r
158 (void*) INT_TRAPA62,
\r
159 // 63 TRAPA (User Vecter)
\r
160 (void*) INT_TRAPA63,
\r
161 // 64 Interrupt IRQ0
\r
163 // 65 Interrupt IRQ1
\r
165 // 66 Interrupt IRQ2
\r
167 // 67 Interrupt IRQ3
\r
169 // 68 Interrupt IRQ4
\r
171 // 69 Interrupt IRQ5
\r
173 // 70 Interrupt IRQ6
\r
175 // 71 Interrupt IRQ7
\r
193 // 80 Interrupt PINT0
\r
195 // 81 Interrupt PINT1
\r
197 // 82 Interrupt PINT2
\r
199 // 83 Interrupt PINT3
\r
201 // 84 Interrupt PINT4
\r
203 // 85 Interrupt PINT5
\r
205 // 86 Interrupt PINT6
\r
207 // 87 Interrupt PINT7
\r
216 (void*) INT_ROM_FIFE,
\r
218 (void*) INT_AD_ADI0,
\r
226 (void*) INT_AD_ADI1,
\r
241 // 104 RCANET0 ERS_0
\r
242 (void*) INT_RCANET0_ERS_0,
\r
243 // 105 RCANET0 OVR_0
\r
244 (void*) INT_RCANET0_OVR_0,
\r
245 // 106 RCANET0 RM01_0
\r
246 (void*) INT_RCANET0_RM01_0,
\r
247 // 107 RCANET0 SLE_0
\r
248 (void*) INT_RCANET0_SLE_0,
\r
250 (void*) INT_DMAC0_DEI0,
\r
252 (void*) INT_DMAC0_HEI0,
\r
258 (void*) INT_DMAC1_DEI1,
\r
260 (void*) INT_DMAC1_HEI1,
\r
266 (void*) INT_DMAC2_DEI2,
\r
268 (void*) INT_DMAC2_HEI2,
\r
274 (void*) INT_DMAC3_DEI3,
\r
276 (void*) INT_DMAC3_HEI3,
\r
282 (void*) INT_DMAC4_DEI4,
\r
284 (void*) INT_DMAC4_HEI4,
\r
290 (void*) INT_DMAC5_DEI5,
\r
292 (void*) INT_DMAC5_HEI5,
\r
298 (void*) INT_DMAC6_DEI6,
\r
300 (void*) INT_DMAC6_HEI6,
\r
306 (void*) INT_DMAC7_DEI7,
\r
308 (void*) INT_DMAC7_HEI7,
\r
314 // (void*) INT_CMT_CMI0,
\r
315 (void*) vPortPreemptiveTick,
\r
323 (void*) INT_CMT_CMI1,
\r
331 (void*) INT_BSC_CMTI,
\r
335 (void*) INT_USB_EP4FULL,
\r
336 // 151 USB EP5EMPTY
\r
337 (void*) INT_USB_EP5EMPTY,
\r
339 (void*) INT_WDT_ITI,
\r
340 // 153 E-DMAC EINT0
\r
341 (void*) INT_EDMAC_EINT0,
\r
343 (void*) INT_USB_EP1FULL,
\r
344 // 155 USB EP2EMPTY
\r
345 (void*) INT_USB_EP2EMPTY,
\r
346 // 156 MTU2 MTU0 TGI0A
\r
347 (void*) INT_MTU2_MTU0_TGI0A,
\r
348 // 157 MTU2 MTU0 TGI0B
\r
349 (void*) INT_MTU2_MTU0_TGI0B,
\r
350 // 158 MTU2 MTU0 TGI0C
\r
351 (void*) INT_MTU2_MTU0_TGI0C,
\r
352 // 159 MTU2 MTU0 TGI0D
\r
353 (void*) INT_MTU2_MTU0_TGI0D,
\r
354 // 160 MTU2 MTU0 TGI0V
\r
355 (void*) INT_MTU2_MTU0_TGI0V,
\r
356 // 161 MTU2 MTU0 TGI0E
\r
357 (void*) INT_MTU2_MTU0_TGI0E,
\r
358 // 162 MTU2 MTU0 TGI0F
\r
359 (void*) INT_MTU2_MTU0_TGI0F,
\r
362 // 164 MTU2 MTU1 TGI1A
\r
363 (void*) INT_MTU2_MTU1_TGI1A,
\r
364 // 165 MTU2 MTU1 TGI1B
\r
365 (void*) INT_MTU2_MTU1_TGI1B,
\r
370 // 168 MTU2 MTU1 TGI1V
\r
371 (void*) INT_MTU2_MTU1_TGI1V,
\r
372 // 169 MTU2 MTU1 TGI1U
\r
373 (void*) INT_MTU2_MTU1_TGI1U,
\r
378 // 172 MTU2 MTU2 TGI2A
\r
379 (void*) INT_MTU2_MTU2_TGI2A,
\r
380 // 173 MTU2 MTU2 TGI2B
\r
381 (void*) INT_MTU2_MTU2_TGI2B,
\r
386 // 176 MTU2 MTU2 TGI2V
\r
387 (void*) INT_MTU2_MTU2_TGI2V,
\r
388 // 177 MTU2 MTU2 TGI2U
\r
389 (void*) INT_MTU2_MTU2_TGI2U,
\r
394 // 180 MTU2 MTU3 TGI3A
\r
395 (void*) INT_MTU2_MTU3_TGI3A,
\r
396 // 181 MTU2 MTU3 TGI3B
\r
397 (void*) INT_MTU2_MTU3_TGI3B,
\r
398 // 182 MTU2 MTU3 TGI3C
\r
399 (void*) INT_MTU2_MTU3_TGI3C,
\r
400 // 183 MTU2 MTU3 TGI3D
\r
401 (void*) INT_MTU2_MTU3_TGI3D,
\r
402 // 184 MTU2 MTU3 TGI3V
\r
403 (void*) INT_MTU2_MTU3_TGI3V,
\r
410 // 188 MTU2 MTU4 TGI4A
\r
411 (void*) INT_MTU2_MTU4_TGI4A,
\r
412 // 189 MTU2 MTU4 TGI4B
\r
413 (void*) INT_MTU2_MTU4_TGI4B,
\r
414 // 190 MTU2 MTU4 TGI4C
\r
415 (void*) INT_MTU2_MTU4_TGI4C,
\r
416 // 191 MTU2 MTU4 TGI4D
\r
417 (void*) INT_MTU2_MTU4_TGI4D,
\r
418 // 192 MTU2 MTU4 TGI4V
\r
419 (void*) INT_MTU2_MTU4_TGI4V,
\r
426 // 196 MTU2 MTU5 TGI5U
\r
427 (void*) INT_MTU2_MTU5_TGI5U,
\r
428 // 197 MTU2 MTU5 TGI5V
\r
429 (void*) INT_MTU2_MTU5_TGI5V,
\r
430 // 198 MTU2 MTU5 TGI5W
\r
431 (void*) INT_MTU2_MTU5_TGI5W,
\r
435 (void*) INT_POE2_OEI1,
\r
437 (void*) INT_POE2_OEI2,
\r
442 // 204 MTU2S MTU3S TGI3A
\r
443 (void*) INT_MTU2S_MTU3S_TGI3A,
\r
444 // 205 MTU2S MTU3S TGI3B
\r
445 (void*) INT_MTU2S_MTU3S_TGI3B,
\r
446 // 206 MTU2S MTU3S TGI3C
\r
447 (void*) INT_MTU2S_MTU3S_TGI3C,
\r
448 // 207 MTU2S MTU3S TGI3D
\r
449 (void*) INT_MTU2S_MTU3S_TGI3D,
\r
450 // 208 MTU2S MTU3S TGI3V
\r
451 (void*) INT_MTU2S_MTU3S_TGI3V,
\r
458 // 212 MTU2S MTU4S TGI4A
\r
459 (void*) INT_MTU2S_MTU4S_TGI4A,
\r
460 // 213 MTU2S MTU4S TGI4B
\r
461 (void*) INT_MTU2S_MTU4S_TGI4B,
\r
462 // 214 MTU2S MTU4S TGI4C
\r
463 (void*) INT_MTU2S_MTU4S_TGI4C,
\r
464 // 215 MTU2S MTU4S TGI4D
\r
465 (void*) INT_MTU2S_MTU4S_TGI4D,
\r
466 // 216 MTU2S MTU4S TGI4V
\r
467 (void*) INT_MTU2S_MTU4S_TGI4V,
\r
474 // 220 MTU2S MTU5S TGI5U
\r
475 (void*) INT_MTU2S_MTU5S_TGI5U,
\r
476 // 221 MTU2S MTU5S TGI5V
\r
477 (void*) INT_MTU2S_MTU5S_TGI5V,
\r
478 // 222 MTU2S MTU5S TGI5W
\r
479 (void*) INT_MTU2S_MTU5S_TGI5W,
\r
483 (void*) INT_POE2_OEI3,
\r
487 (void*) INT_USB_USI0,
\r
489 (void*) INT_USB_USI1,
\r
491 (void*) INT_IIC3_STPI,
\r
493 (void*) INT_IIC3_NAKI,
\r
495 (void*) INT_IIC3_RXI,
\r
497 (void*) INT_IIC3_TXI,
\r
499 (void*) INT_IIC3_TEI,
\r
501 (void*) INT_RSPI_SPERI,
\r
503 (void*) INT_RSPI_SPRXI,
\r
505 (void*) INT_RSPI_SPTXI,
\r
506 // 236 SCI SCI4 ERI4
\r
507 (void*) INT_SCI_SCI4_ERI4,
\r
508 // 237 SCI SCI4 RXI4
\r
509 (void*) INT_SCI_SCI4_RXI4,
\r
510 // 238 SCI SCI4 TXI4
\r
511 (void*) INT_SCI_SCI4_TXI4,
\r
512 // 239 SCI SCI4 TEI4
\r
513 (void*) INT_SCI_SCI4_TEI4,
\r
514 // 240 SCI SCI0 ERI0
\r
515 (void*) INT_SCI_SCI0_ERI0,
\r
516 // 241 SCI SCI0 RXI0
\r
517 (void*) INT_SCI_SCI0_RXI0,
\r
518 // 242 SCI SCI0 TXI0
\r
519 (void*) INT_SCI_SCI0_TXI0,
\r
520 // 243 SCI SCI0 TEI0
\r
521 (void*) INT_SCI_SCI0_TEI0,
\r
522 // 244 SCI SCI1 ERI1
\r
523 (void*) INT_SCI_SCI1_ERI1,
\r
524 // 245 SCI SCI1 RXI1
\r
525 (void*) INT_SCI_SCI1_RXI1,
\r
526 // 246 SCI SCI1 TXI1
\r
527 (void*) INT_SCI_SCI1_TXI1,
\r
528 // 247 SCI SCI1 TEI1
\r
529 (void*) INT_SCI_SCI1_TEI1,
\r
530 // 248 SCI SCI2 ERI2
\r
531 (void*) INT_SCI_SCI2_ERI2,
\r
532 // 249 SCI SCI2 RXI2
\r
533 (void*) INT_SCI_SCI2_RXI2,
\r
534 // 250 SCI SCI2 TXI2
\r
535 (void*) INT_SCI_SCI2_TXI2,
\r
536 // 251 SCI SCI2 TEI2
\r
537 (void*) INT_SCI_SCI2_TEI2,
\r
538 // 252 SCIF SCIF3 BRI3
\r
539 (void*) INT_SCIF_SCIF3_BRI3,
\r
540 // 253 SCIF SCIF3 ERI3
\r
541 (void*) INT_SCIF_SCIF3_ERI3,
\r
542 // 254 SCIF SCIF3 RXI3
\r
543 (void*) INT_SCIF_SCIF3_RXI3,
\r
544 // 255 SCIF SCIF3 TXI3
\r
545 (void*) INT_SCIF_SCIF3_TXI3,
\r
projects / freertos / blob