2 FreeRTOS V6.0.2 - Copyright (C) 2010 Real Time Engineers Ltd.
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4 ***************************************************************************
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8 * + New to FreeRTOS, *
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13 * then take a look at the FreeRTOS eBook *
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15 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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16 * http://www.FreeRTOS.org/Documentation *
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19 * to your inbox within 20 minutes to two hours when purchased between 8am *
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20 * and 8pm GMT (although please allow up to 24 hours in case of *
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21 * exceptional circumstances). Thank you for your support! *
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23 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 ***NOTE*** The exception to the GPL is included to allow you to distribute
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31 a combined work that includes FreeRTOS without being obliged to provide the
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32 source code for proprietary components outside of the FreeRTOS kernel.
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33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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54 /* Hardware specific includes. */
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55 #include "iodefine.h"
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56 #include "typedefine.h"
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57 #include "hwEthernet.h"
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58 #include "hwEthernetPhy.h"
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60 /* FreeRTOS includes. */
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61 #include "FreeRTOS.h"
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66 #include "net/uip.h"
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68 /* The time to wait between attempts to obtain a free buffer. */
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69 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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71 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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72 up on attempting to obtain a free buffer all together. */
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73 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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75 /* The number of Rx descriptors. */
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76 #define emacNUM_RX_DESCRIPTORS 3
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78 /* The number of Tx descriptors. When using uIP there is not point in having
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80 #define emacNUM_TX_BUFFERS 2
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82 /* The total number of EMAC buffers to allocate. */
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83 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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85 /* The time to wait for the Tx descriptor to become free. */
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86 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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88 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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90 #define emacTX_WAIT_ATTEMPTS ( 5 )
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92 /* Only Rx end and Tx end interrupts are used by this driver. */
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93 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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94 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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96 /*-----------------------------------------------------------*/
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98 /* The buffers and descriptors themselves. */
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99 #pragma section RX_DESCR
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100 ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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101 #pragma section TX_DESCR
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102 ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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103 #pragma section _ETHERNET_BUFFERS
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104 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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107 /* Used to indicate which buffers are free and which are in use. If an index
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108 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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109 the buffer is in use or about to be used. */
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110 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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112 /*-----------------------------------------------------------*/
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115 * Initialise both the Rx and Tx descriptors.
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117 static void prvInitialiseDescriptors( void );
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120 * Return a pointer to a free buffer within xEthernetBuffers.
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122 static unsigned char *prvGetNextBuffer( void );
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125 * Return a buffer to the list of free buffers.
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127 static void prvReturnBuffer( unsigned char *pucBuffer );
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130 * Examine the status of the next Rx FIFO to see if it contains new data.
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132 static unsigned long prvCheckRxFifoStatus( void );
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135 * Setup the microcontroller for communication with the PHY.
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137 static void prvSetupPortPinsAndReset( void );
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140 * Configure the Ethernet interface peripherals.
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142 static void prvConfigureEtherCAndEDMAC( void );
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145 * Something has gone wrong with the descriptor usage. Reset all the buffers
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148 static void prvResetEverything( void );
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150 /*-----------------------------------------------------------*/
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152 /* Points to the Rx descriptor currently in use. */
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153 static ethfifo *xCurrentRxDesc = NULL;
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155 /* The buffer used by the uIP stack to both receive and send. This points to
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156 one of the Ethernet buffers when its actually in use. */
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157 unsigned char *uip_buf = NULL;
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159 /*-----------------------------------------------------------*/
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161 void vInitEmac( void )
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163 /* Setup the SH hardware for MII communications. */
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164 prvSetupPortPinsAndReset();
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166 /* Set the Rx and Tx descriptors into their initial state. */
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167 prvInitialiseDescriptors();
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169 /* Set the MAC address into the ETHERC */
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170 EtherC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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171 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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172 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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173 ( unsigned long ) configMAC_ADDR3;
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175 EtherC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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176 ( unsigned long ) configMAC_ADDR5;
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178 /* Perform rest of interface hardware configuration. */
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179 prvConfigureEtherCAndEDMAC();
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181 /* Nothing received yet, so uip_buf points nowhere. */
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184 /* Initialize the PHY */
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187 /*-----------------------------------------------------------*/
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189 void vEMACWrite( void )
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193 /* Wait until the second transmission of the last packet has completed. */
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194 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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196 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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198 /* Descriptor is still active. */
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199 vTaskDelay( emacTX_WAIT_DELAY_ms );
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207 /* Is the descriptor free after waiting for it? */
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208 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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210 /* Something has gone wrong. */
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211 prvResetEverything();
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214 /* Setup both descriptors to transmit the frame. */
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215 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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216 xTxDescriptors[ 0 ].bufsize = uip_len;
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217 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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218 xTxDescriptors[ 1 ].bufsize = uip_len;
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220 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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221 for use by the stack. */
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222 uip_buf = prvGetNextBuffer();
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224 /* Clear previous settings and go. */
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225 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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226 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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227 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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228 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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230 EDMAC.EDTRR.LONG = 0x00000001;
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232 /*-----------------------------------------------------------*/
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234 unsigned long ulEMACRead( void )
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236 unsigned long ulBytesReceived;
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238 ulBytesReceived = prvCheckRxFifoStatus();
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240 if( ulBytesReceived > 0 )
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242 xCurrentRxDesc->status &= ~( FP1 | FP0 );
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243 xCurrentRxDesc->status |= ACT;
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245 if( EDMAC.EDRRR.LONG == 0x00000000L )
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247 /* Restart Ethernet if it has stopped */
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248 EDMAC.EDRRR.LONG = 0x00000001L;
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251 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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252 the buffer that contains the received data. */
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253 prvReturnBuffer( uip_buf );
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255 uip_buf = ( void * ) xCurrentRxDesc->buf_p;
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257 /* Move onto the next buffer in the ring. */
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258 xCurrentRxDesc = xCurrentRxDesc->next;
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261 return ulBytesReceived;
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263 /*-----------------------------------------------------------*/
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265 long lEMACWaitForLink( void )
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269 /* Set the link status. */
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270 switch( phyStatus() )
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272 /* Half duplex link */
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273 case PHY_LINK_100H:
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275 EtherC.ECMR.BIT.DM = 0;
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279 /* Full duplex link */
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280 case PHY_LINK_100F:
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282 EtherC.ECMR.BIT.DM = 1;
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291 if( lReturn == pdPASS )
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293 /* Enable receive and transmit. */
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294 EtherC.ECMR.BIT.RE = 1;
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295 EtherC.ECMR.BIT.TE = 1;
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297 /* Enable EDMAC receive */
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298 EDMAC.EDRRR.LONG = 0x1;
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303 /*-----------------------------------------------------------*/
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305 static void prvInitialiseDescriptors( void )
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307 ethfifo *pxDescriptor;
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310 for( x = 0; x < emacNUM_BUFFERS; x++ )
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312 /* Ensure none of the buffers are shown as in use at the start. */
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313 ucBufferInUse[ x ] = pdFALSE;
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316 /* Initialise the Rx descriptors. */
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317 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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319 pxDescriptor = &( xRxDescriptors[ x ] );
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320 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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322 pxDescriptor->bufsize = UIP_BUFSIZE;
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323 pxDescriptor->size = 0;
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324 pxDescriptor->status = ACT;
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325 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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327 /* Mark this buffer as in use. */
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328 ucBufferInUse[ x ] = pdTRUE;
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331 /* The last descriptor points back to the start. */
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332 pxDescriptor->status |= DL;
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333 pxDescriptor->next = &xRxDescriptors[ 0 ];
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335 /* Initialise the Tx descriptors. */
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336 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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338 pxDescriptor = &( xTxDescriptors[ x ] );
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340 /* A buffer is not allocated to the Tx descriptor until a send is
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341 actually required. */
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342 pxDescriptor->buf_p = NULL;
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344 pxDescriptor->bufsize = UIP_BUFSIZE;
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345 pxDescriptor->size = 0;
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346 pxDescriptor->status = 0;
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347 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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350 /* The last descriptor points back to the start. */
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351 pxDescriptor->status |= DL;
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352 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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354 /* Use the first Rx descriptor to start with. */
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355 xCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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357 /*-----------------------------------------------------------*/
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359 static unsigned char *prvGetNextBuffer( void )
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362 unsigned char *pucReturn = NULL;
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363 unsigned long ulAttempts = 0;
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365 while( pucReturn == NULL )
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367 /* Look through the buffers to find one that is not in use by
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369 for( x = 0; x < emacNUM_BUFFERS; x++ )
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371 if( ucBufferInUse[ x ] == pdFALSE )
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373 ucBufferInUse[ x ] = pdTRUE;
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374 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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379 /* Was a buffer found? */
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380 if( pucReturn == NULL )
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384 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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389 /* Wait then look again. */
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390 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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396 /*-----------------------------------------------------------*/
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398 static void prvReturnBuffer( unsigned char *pucBuffer )
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402 /* Return a buffer to the pool of free buffers. */
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403 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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405 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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407 ucBufferInUse[ ul ] = pdFALSE;
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412 /*-----------------------------------------------------------*/
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414 static void prvResetEverything( void )
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416 /* Temporary code just to see if this gets called. This function has not
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417 been implemented. */
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418 portDISABLE_INTERRUPTS();
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421 /*-----------------------------------------------------------*/
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423 static unsigned long prvCheckRxFifoStatus( void )
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425 unsigned long ulReturn = 0;
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427 if( ( xCurrentRxDesc->status & ACT ) != 0 )
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429 /* Current descriptor is still active. */
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431 else if( ( xCurrentRxDesc->status & FE ) != 0 )
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433 /* Frame error. Clear the error. */
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434 xCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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435 xCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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436 xCurrentRxDesc->status |= ACT;
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437 xCurrentRxDesc = xCurrentRxDesc->next;
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439 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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441 /* Restart Ethernet if it has stopped. */
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442 EDMAC.EDRRR.LONG = 0x00000001UL;
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447 /* The descriptor contains a frame. Because of the size of the buffers
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448 the frame should always be complete. */
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449 if( (xCurrentRxDesc->status & FP0) == FP0 )
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451 ulReturn = xCurrentRxDesc->size;
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455 /* Do not expect to get here. */
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456 prvResetEverything();
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462 /*-----------------------------------------------------------*/
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464 static void prvSetupPortPinsAndReset( void )
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466 /* Initialisation code taken from Renesas example project. */
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468 PFC.PACRL4.BIT.PA12MD = 0x7; /* Set TX_CLK input (EtherC) */
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469 PFC.PACRL3.BIT.PA11MD = 0x7; /* Set TX_EN output (EtherC) */
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470 PFC.PACRL3.BIT.PA10MD = 0x7; /* Set MII_TXD0 output (EtherC) */
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471 PFC.PACRL3.BIT.PA9MD = 0x7; /* Set MII_TXD1 output (EtherC) */
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472 PFC.PACRL3.BIT.PA8MD = 0x7; /* Set MII_TXD2 output (EtherC) */
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473 PFC.PACRL2.BIT.PA7MD = 0x7; /* Set MII_TXD3 output (EtherC) */
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474 PFC.PACRL2.BIT.PA6MD = 0x7; /* Set TX_ER output (EtherC) */
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475 PFC.PDCRH4.BIT.PD31MD = 0x7; /* Set RX_DV input (EtherC) */
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476 PFC.PDCRH4.BIT.PD30MD = 0x7; /* Set RX_ER input (EtherC) */
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477 PFC.PDCRH4.BIT.PD29MD = 0x7; /* Set MII_RXD3 input (EtherC) */
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478 PFC.PDCRH4.BIT.PD28MD = 0x7; /* Set MII_RXD2 input (EtherC) */
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479 PFC.PDCRH3.BIT.PD27MD = 0x7; /* Set MII_RXD1 input (EtherC) */
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480 PFC.PDCRH3.BIT.PD26MD = 0x7; /* Set MII_RXD0 input (EtherC) */
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481 PFC.PDCRH3.BIT.PD25MD = 0x7; /* Set RX_CLK input (EtherC) */
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482 PFC.PDCRH3.BIT.PD24MD = 0x7; /* Set CRS input (EtherC) */
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483 PFC.PDCRH2.BIT.PD23MD = 0x7; /* Set COL input (EtherC) */
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484 PFC.PDCRH2.BIT.PD22MD = 0x7; /* Set WOL output (EtherC) */
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485 PFC.PDCRH2.BIT.PD21MD = 0x7; /* Set EXOUT output (EtherC) */
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486 PFC.PDCRH2.BIT.PD20MD = 0x7; /* Set MDC output (EtherC) */
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487 PFC.PDCRH1.BIT.PD19MD = 0x7; /* Set LINKSTA input (EtherC) */
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488 PFC.PDCRH1.BIT.PD18MD = 0x7; /* Set MDIO input/output (EtherC) */
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490 STB.CR4.BIT._ETHER = 0x0;
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491 EDMAC.EDMR.BIT.SWR = 1;
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493 /* Crude wait for reset to complete. */
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494 vTaskDelay( 500 / portTICK_RATE_MS );
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496 /*-----------------------------------------------------------*/
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498 static void prvConfigureEtherCAndEDMAC( void )
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500 /* Initialisation code taken from Renesas example project. */
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502 /* TODO: Check bit 5 */
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503 EtherC.ECSR.LONG = 0x00000037; /* Clear all EtherC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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505 /* TODO: Check bit 5 */
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506 EtherC.ECSIPR.LONG = 0x00000020; /* Disable EtherC status change interrupt */
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507 EtherC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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508 EtherC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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511 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all EtherC and EDMAC status bits */
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512 EDMAC.RDLAR = ( void * ) xCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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513 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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514 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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515 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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516 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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517 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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519 /* Set the EDMAC interrupt priority - the interrupt priority must be
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520 configKERNEL_INTERRUPT_PRIORITY no matter which peripheral is used to
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521 generate the tick interrupt. */
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522 INTC.IPR19.BIT._EDMAC = portKERNEL_INTERRUPT_PRIORITY;
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523 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT; /* Enable Rx and Tx end interrupts. */
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525 /* Clear the interrupt flag. */
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526 CMT0.CMCSR.BIT.CMF = 0;
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528 /*-----------------------------------------------------------*/
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530 void vEMAC_ISR_Handler( void )
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532 unsigned long ul = EDMAC.EESR.LONG;
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533 long lHigherPriorityTaskWoken = pdFALSE;
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534 extern xSemaphoreHandle xEMACSemaphore;
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535 static long ulTxEndInts = 0;
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537 /* Has a Tx end occurred? */
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538 if( ul & emacTX_END_INTERRUPT )
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541 if( ulTxEndInts >= 2 )
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543 /* Only return the buffer to the pool once both Txes have completed. */
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544 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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547 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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550 /* Has an Rx end occurred? */
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551 if( ul & emacRX_END_INTERRUPT )
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553 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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554 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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555 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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556 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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