2 FreeRTOS.org V4.0.5 - copyright (C) 2003-2006 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 See http://www.FreeRTOS.org for documentation, latest information, license
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28 and contact details. Please ensure to read the configuration and relevant
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29 port sections of the online documentation.
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30 ***************************************************************************
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36 + Modified char* types to compile without warning when using GCC V4.0.1.
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37 + Corrected the address to which the MAC address is written. Thanks to
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38 Bill Knight for this correction.
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42 + Changed the default MAC address to something more realistic.
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46 /* Standard includes. */
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50 /* Scheduler include files. */
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51 #include "FreeRTOS.h"
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57 /* Application includes. */
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59 #include "html_pages.h"
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61 /*-----------------------------------------------------------*/
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63 /* Hardwired i2c address of the WIZNet device. */
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64 #define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 )
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66 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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68 #define tcp8K_RX ( ( unsigned portCHAR ) 0x03 )
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69 #define tcp8K_TX ( ( unsigned portCHAR ) 0x03 )
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71 /* Constants used to generate the WIZnet internal buffer addresses. */
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72 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff )
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73 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 )
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75 /* Bit definitions of the commands that can be sent to the command register. */
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76 #define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 )
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77 #define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 )
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78 #define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 )
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79 #define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 )
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80 #define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 )
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81 #define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 )
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82 #define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 )
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83 #define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 )
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85 /* Constants required to handle the interrupts. */
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86 #define tcpCLEAR_EINT0 ( 1 )
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87 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff )
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88 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 )
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89 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 )
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90 #define tcpWAKE_ON_EINT0 ( 1 )
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91 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 )
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92 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 )
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93 #define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 )
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94 #define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
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96 /* Various delays used in the driver. */
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97 #define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )
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98 #define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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99 #define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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100 #define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS )
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101 #define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS )
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102 #define tcpNO_DELAY ( ( portTickType ) 0 )
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104 /* Length of the data to read for various register reads. */
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105 #define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 )
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106 #define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 )
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108 /* Register addresses within the WIZnet device. */
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109 #define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 )
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110 #define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 )
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111 #define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 )
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112 #define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 )
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113 #define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E )
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114 #define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 )
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115 #define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE )
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116 #define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 )
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117 #define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 )
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118 #define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 )
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119 #define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 )
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120 #define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 )
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121 #define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 )
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122 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 )
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123 #define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 )
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124 #define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 )
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125 #define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 )
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126 #define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 )
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128 /* Constants required for hardware setup. */
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129 #define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 )
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130 #define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 )
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132 /* Constants defining the source of the WIZnet ISR. */
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133 #define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 )
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134 #define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 )
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135 #define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 )
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136 #define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 )
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137 #define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 )
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138 #define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 )
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139 #define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 )
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141 /* Constants defining the socket status bits. */
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142 #define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 )
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143 #define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 )
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145 /* Misc constants. */
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146 #define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 )
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147 #define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 )
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148 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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149 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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150 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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151 #define tcpBUFFER_LEN ( 4 * 1024 )
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152 #define tcpMAX_REGISTER_LEN ( 4 )
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153 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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154 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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156 /* Message definitions. The IP address, MAC address, gateway address, etc.
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158 const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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159 const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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160 const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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161 const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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163 /* Other fixed messages. */
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164 const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD };
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165 const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD };
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166 const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM };
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167 const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC };
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168 const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT };
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169 const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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170 const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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171 const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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172 const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD };
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173 const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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174 const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX };
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175 const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX };
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176 const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD };
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177 const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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178 const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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179 const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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180 const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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182 static xSemaphoreHandle xMessageComplete = NULL;
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183 xQueueHandle xTCPISRQueue = NULL;
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185 /* Dynamically generate and send an html page. */
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186 static void prvSendSamplePage( void );
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188 /* Read a register from the WIZnet device via the i2c interface. */
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189 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength );
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191 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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192 static void prvFlushBuffer( unsigned portLONG ulTxAddress );
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194 /* Write a string to the WIZnet Tx buffer. */
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195 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress );
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197 /* Convert a number to a string. */
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198 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore );
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200 /*-----------------------------------------------------------*/
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202 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore )
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204 unsigned portLONG lNibble;
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207 /* Simple routine to convert an unsigned long value into a string in hex
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210 /* For each nibble in the number we are converting. */
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211 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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213 /* Take the top four bits of the number. */
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214 lNibble = ( ulVal >> 28 );
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216 /* We are converting it to a hex string, so is the number in the range
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220 pcBuffer[ lIndex ] = '0' + lNibble;
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225 pcBuffer[ lIndex ] = 'A' + lNibble;
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228 /* Shift off the top nibble so we use the next nibble next time around. */
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232 /* Mark the end of the string with a null terminator. */
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233 pcBuffer[ lIndex ] = 0x00;
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235 /*-----------------------------------------------------------*/
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237 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength )
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239 unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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241 /* Read a register value from the WIZnet device. */
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243 /* First write out the address of the register we want to read. */
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244 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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246 /* Then read back from that address. */
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247 i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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249 /* I2C messages are queued so use the semaphore to wait for the read to
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250 complete - otherwise we will leave this function before the I2C
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251 transactions have completed. */
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252 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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254 /*-----------------------------------------------------------*/
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256 void vTCPHardReset( void )
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258 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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259 WIZnet reset lines active for a few milliseconds. */
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261 /* Make sure the interrupt from the WIZnet is disabled. */
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262 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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264 /* If xMessageComplete is NULL then this is the first time that this
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265 function has been called and the queue and semaphore used in this file
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266 have not yet been created. */
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267 if( xMessageComplete == NULL )
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269 /* Create and obtain the semaphore used when we want to wait for an i2c
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270 message to be completed. */
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271 vSemaphoreCreateBinary( xMessageComplete );
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272 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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274 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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275 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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278 /* Use the GPIO to reset the network hardware. */
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279 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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280 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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282 /* Delay with the network hardware in reset for a short while. */
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283 vTaskDelay( tcpRESET_DELAY );
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285 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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286 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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288 vTaskDelay( tcpINIT_DELAY );
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290 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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291 First enable the EINT0 function of the pin. */
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292 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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294 /* We want the TCP comms to wake us from power save. */
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295 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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297 /* Install the ISR into the VIC - but don't enable it yet! */
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298 portENTER_CRITICAL();
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300 extern void ( vEINT0_ISR )( void );
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302 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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303 VICVectAddr3 = ( portLONG ) vEINT0_ISR;
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305 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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307 portEXIT_CRITICAL();
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309 /* Enable interrupts in the WIZnet itself. */
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310 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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312 vTaskDelay( tcpLONG_DELAY );
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314 /*-----------------------------------------------------------*/
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316 portLONG lTCPSoftReset( void )
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318 unsigned portCHAR ucStatus;
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319 extern volatile portLONG lTransactionCompleted;
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321 /* Send a message to the WIZnet device to tell it set all it's registers
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322 back to their default states. Then setup the WIZnet device as required. */
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324 /* Reset the internal WIZnet registers. */
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325 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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327 /* Now we can configure the protocol. Here the MAC address, gateway
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328 address, subnet mask and IP address are configured. */
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329 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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330 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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331 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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332 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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334 /* Next the memory buffers are configured to give all the WIZnet internal
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335 memory over to a single socket. This gives the socket the maximum internal
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336 Tx and Rx buffer space. */
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337 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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338 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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340 /* Send the sys init command so the above parameters take effect. */
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341 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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343 /* Seems to like a little wait here. */
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344 vTaskDelay( tcpINIT_DELAY );
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346 /* Read back the status to ensure the system initialised ok. */
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347 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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349 /* We should find that the sys init was successful. */
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350 if( ucStatus != tcpISR_SYS_INIT )
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352 return ( portLONG ) pdFAIL;
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355 /* No i2c errors yet. */
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356 portENTER_CRITICAL();
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357 lTransactionCompleted = pdTRUE;
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358 portEXIT_CRITICAL();
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360 return ( portLONG ) pdPASS;
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362 /*-----------------------------------------------------------*/
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364 portLONG lTCPCreateSocket( void )
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366 unsigned portCHAR ucStatus;
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368 /* Create and configure a socket. */
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370 /* Setup and init the socket. Here the port number is set and the socket
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372 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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373 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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374 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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376 /* Wait for the Init command to be sent. */
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377 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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379 /* For some reason the message was not transmitted within our block
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381 return ( portLONG ) pdFAIL;
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384 /* Allow the socket to initialise. */
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385 vTaskDelay( tcpINIT_DELAY );
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387 /* Read back the status to ensure the socket initialised ok. */
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388 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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390 /* We should find that the socket init was successful. */
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391 if( ucStatus != tcpISR_SOCKET_INIT )
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393 return ( portLONG ) pdFAIL;
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397 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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398 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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399 vTaskDelay( tcpSHORT_DELAY );
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400 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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401 vTaskDelay( tcpSHORT_DELAY );
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402 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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403 vTaskDelay( tcpSHORT_DELAY );
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405 return ( portLONG ) pdPASS;
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407 /*-----------------------------------------------------------*/
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409 void vTCPListen( void )
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411 unsigned portCHAR ucISR;
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413 /* Start a passive listen on the socket. */
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415 /* Enable interrupts in the WizNet device after ensuring none are
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416 currently pending. */
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417 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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419 /* The WIZnet device is still asserting and interrupt so tell it to
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421 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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422 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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425 SCB_EXTINT = tcpCLEAR_EINT0;
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428 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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430 /* Just clearing the queue used by the ISR routine to tell this task
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431 that the WIZnet device needs attention. */
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434 /* Now all the pending interrupts have been cleared we can enable the
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435 processor interrupts. */
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436 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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438 /* Then start listening for incoming connections. */
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439 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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441 /*-----------------------------------------------------------*/
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443 portLONG lProcessConnection( void )
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445 unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow;
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446 extern volatile portLONG lTransactionCompleted;
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447 portLONG lSameStateCount = 0, lDataSent = pdFALSE;
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448 unsigned portLONG ulWritePointer, ulAckPointer;
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450 /* No I2C errors can yet have occurred. */
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451 portENTER_CRITICAL();
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452 lTransactionCompleted = pdTRUE;
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453 portEXIT_CRITICAL();
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455 /* Keep looping - processing interrupts, until we have completed a
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456 transaction. This uses the WIZnet in it's simplest form. The socket
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457 accepts a connection - we process the connection - then close the socket.
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458 We then go back to reinitialise everything and start again. */
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459 while( lTransactionCompleted == pdTRUE )
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461 /* Wait for a message on the queue from the WIZnet ISR. When the
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462 WIZnet device asserts an interrupt the ISR simply posts a message
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463 onto this queue to wake this task. */
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464 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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466 /* The ISR posted a message on this queue to tell us that the
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467 WIZnet device asserted an interrupt. The ISR cannot process
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468 an I2C message so cannot tell us what caused the interrupt so
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469 we have to query the device here. This task is the highest
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470 priority in the system so will run immediately following the ISR. */
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471 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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473 /* Once we have read what caused the ISR we can clear the interrupt
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475 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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477 /* Now we can clear the processor interrupt and re-enable ready for
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479 SCB_EXTINT = tcpCLEAR_EINT0;
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480 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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482 /* Process the interrupt ... */
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484 if( ucISR & tcpISR_ESTABLISHED )
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486 /* A connection has been established - respond by sending
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487 a receive command. */
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488 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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491 if( ucISR & tcpISR_RX_COMPLETE )
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493 /* We message has been received. This will be an HTTP get
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494 command. We only have one page to send so just send it without
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495 regard to what the actual requested page was. */
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496 prvSendSamplePage();
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499 if( ucISR & tcpISR_TX_COMPLETE )
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501 /* We have a TX complete interrupt - which oddly does not
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502 indicate that the message being sent is complete so we cannot
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503 yet close the socket. Instead we read the position of the Tx
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504 pointer within the WIZnet device so we know how much data it
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505 has to send. Later we will read the ack pointer and compare
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506 this to the Tx pointer to ascertain whether the transmission
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509 /* First read the shadow register. */
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510 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
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512 /* Now a short delay is required. */
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513 vTaskDelay( tcpSHORT_DELAY );
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515 /* Then we can read the real register. */
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516 prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
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518 /* We cannot do anything more here but need to remember that
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519 this interrupt has occurred. */
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520 lDataSent = pdTRUE;
\r
523 if( ucISR & tcpISR_CLOSED )
\r
525 /* The socket has been closed so we can leave this function. */
\r
526 lTransactionCompleted = pdFALSE;
\r
531 /* We have not received an interrupt from the WIZnet device for a
\r
532 while. Read the socket status and check that everything is as
\r
534 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
536 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
538 /* The socket is established and we have already received a Tx
\r
539 end interrupt. We must therefore be waiting for the Tx buffer
\r
540 inside the WIZnet device to be empty before we can close the
\r
543 Read the Ack pointer register to see if it has caught up with
\r
544 the Tx pointer register. First we have to read the shadow
\r
546 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
547 vTaskDelay( tcpSHORT_DELAY );
\r
548 prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
550 if( ulAckPointer == ulWritePointer )
\r
552 /* The Ack and write pointer are now equal and we can
\r
553 safely close the socket. */
\r
554 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
558 /* Keep a count of how many times we encounter the Tx
\r
559 buffer still containing data. */
\r
561 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
563 /* Assume we cannot complete sending the data and
\r
564 therefore cannot safely close the socket. Start over. */
\r
566 lTransactionCompleted = pdFALSE;
\r
570 else if( ucState != tcpSTATUS_LISTEN )
\r
572 /* If we have not yet received a Tx end interrupt we would only
\r
573 ever expect to find the socket still listening for any
\r
574 sustained period. */
\r
575 if( ucState == ucLastState )
\r
578 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
580 /* We are persistently in an unexpected state. Assume
\r
581 we cannot safely close the socket and start over. */
\r
583 lTransactionCompleted = pdFALSE;
\r
589 /* We are in the listen state so are happy that everything
\r
591 lSameStateCount = 0;
\r
594 /* Remember what state we are in this time around so we can check
\r
595 for a persistence on an unexpected state. */
\r
596 ucLastState = ucState;
\r
600 /* We are going to reinitialise the WIZnet device so do not want our
\r
601 interrupts from the WIZnet to be processed. */
\r
602 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
603 return lTransactionCompleted;
\r
605 /*-----------------------------------------------------------*/
\r
607 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress )
\r
609 unsigned portLONG ulSendAddress;
\r
611 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
613 /* Calculate the address to which we are going to write in the buffer. */
\r
614 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
616 /* Send the buffer to the calculated address. Use the semaphore so we
\r
617 can wait until the entire message has been transferred. */
\r
618 i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
620 /* Wait until the semaphore indicates that the message has been transferred. */
\r
621 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
626 /* Return the new address of the end of the buffer (within the WIZnet
\r
628 *pulTxAddress += ( unsigned portLONG ) lTxLen;
\r
630 /*-----------------------------------------------------------*/
\r
632 static void prvFlushBuffer( unsigned portLONG ulTxAddress )
\r
634 unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
636 /* We have written some data to the Tx buffer internal to the WIZnet
\r
637 device. Now we update the Tx pointer inside the WIZnet then send a
\r
638 Send command - which causes the data up to the new Tx pointer to be
\r
641 /* Make sure endieness is correct for transmission. */
\r
642 ulTxAddress = htonl( ulTxAddress );
\r
644 /* Place the new Tx pointer in the string to be transmitted. */
\r
645 ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
647 ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
649 ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
651 ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
654 /* And send it to the WIZnet device. */
\r
655 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
657 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
662 vTaskDelay( tcpSHORT_DELAY );
\r
665 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
667 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
672 /*-----------------------------------------------------------*/
\r
674 static void prvSendSamplePage( void )
\r
676 extern portLONG lErrorInTask;
\r
677 unsigned portLONG ulTxAddress;
\r
678 unsigned portCHAR ucShadow;
\r
680 static unsigned portLONG ulRefreshCount = 0x00;
\r
681 static portCHAR cPageBuffer[ tcpBUFFER_LEN ];
\r
684 /* This function just generates a sample page of HTML which gets
\r
685 sent each time a client attaches to the socket. The page is created
\r
686 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
687 with a bit of dynamically generated data in the middle. */
\r
689 /* We need to know the address to which the html string should be sent
\r
690 in the WIZnet Tx buffer. First read the shadow register. */
\r
691 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
693 /* Now a short delay is required. */
\r
694 vTaskDelay( tcpSHORT_DELAY );
\r
696 /* Now we can read the real pointer value. */
\r
697 prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
699 /* Make sure endieness is correct. */
\r
700 ulTxAddress = htonl( ulTxAddress );
\r
702 /* Send the start of the page. */
\r
703 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
705 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
707 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
708 lIndex = strlen( cPageBuffer );
\r
709 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
710 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
711 lIndex = strlen( cPageBuffer );
\r
712 ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
713 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
714 lIndex = strlen( cPageBuffer );
\r
715 ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
716 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
717 lIndex = strlen( cPageBuffer );
\r
718 ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
722 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
726 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
731 /* Send the dynamically generated string. */
\r
732 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
734 /* Finish the page. */
\r
735 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
737 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
738 prvFlushBuffer( ulTxAddress );
\r