2 FreeRTOS.org V4.5.0 - Copyright (C) 2003-2007 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 See http://www.FreeRTOS.org for documentation, latest information, license
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28 and contact details. Please ensure to read the configuration and relevant
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29 port sections of the online documentation.
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31 Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
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32 with commercial development and support options.
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33 ***************************************************************************
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39 + Modified char* types to compile without warning when using GCC V4.0.1.
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40 + Corrected the address to which the MAC address is written. Thanks to
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41 Bill Knight for this correction.
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45 + Changed the default MAC address to something more realistic.
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49 /* Standard includes. */
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53 /* Scheduler include files. */
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54 #include "FreeRTOS.h"
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60 /* Application includes. */
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62 #include "html_pages.h"
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64 /*-----------------------------------------------------------*/
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66 /* Hardwired i2c address of the WIZNet device. */
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67 #define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 )
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69 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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71 #define tcp8K_RX ( ( unsigned portCHAR ) 0x03 )
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72 #define tcp8K_TX ( ( unsigned portCHAR ) 0x03 )
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74 /* Constants used to generate the WIZnet internal buffer addresses. */
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75 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff )
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76 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 )
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78 /* Bit definitions of the commands that can be sent to the command register. */
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79 #define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 )
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80 #define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 )
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81 #define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 )
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82 #define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 )
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83 #define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 )
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84 #define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 )
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85 #define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 )
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86 #define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 )
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88 /* Constants required to handle the interrupts. */
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89 #define tcpCLEAR_EINT0 ( 1 )
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90 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff )
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91 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 )
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92 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 )
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93 #define tcpWAKE_ON_EINT0 ( 1 )
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94 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 )
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95 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 )
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96 #define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 )
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97 #define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
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99 /* Various delays used in the driver. */
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100 #define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )
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101 #define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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102 #define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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103 #define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS )
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104 #define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS )
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105 #define tcpNO_DELAY ( ( portTickType ) 0 )
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107 /* Length of the data to read for various register reads. */
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108 #define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 )
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109 #define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 )
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111 /* Register addresses within the WIZnet device. */
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112 #define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 )
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113 #define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 )
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114 #define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 )
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115 #define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 )
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116 #define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E )
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117 #define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 )
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118 #define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE )
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119 #define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 )
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120 #define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 )
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121 #define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 )
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122 #define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 )
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123 #define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 )
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124 #define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 )
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125 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 )
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126 #define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 )
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127 #define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 )
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128 #define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 )
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129 #define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 )
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131 /* Constants required for hardware setup. */
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132 #define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 )
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133 #define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 )
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135 /* Constants defining the source of the WIZnet ISR. */
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136 #define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 )
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137 #define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 )
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138 #define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 )
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139 #define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 )
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140 #define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 )
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141 #define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 )
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142 #define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 )
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144 /* Constants defining the socket status bits. */
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145 #define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 )
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146 #define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 )
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148 /* Misc constants. */
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149 #define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 )
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150 #define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 )
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151 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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152 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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153 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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154 #define tcpBUFFER_LEN ( 4 * 1024 )
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155 #define tcpMAX_REGISTER_LEN ( 4 )
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156 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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157 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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159 /* Message definitions. The IP address, MAC address, gateway address, etc.
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161 const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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162 const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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163 const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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164 const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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166 /* Other fixed messages. */
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167 const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD };
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168 const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD };
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169 const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM };
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170 const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC };
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171 const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT };
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172 const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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173 const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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174 const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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175 const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD };
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176 const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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177 const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX };
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178 const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX };
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179 const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD };
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180 const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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181 const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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182 const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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183 const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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185 static xSemaphoreHandle xMessageComplete = NULL;
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186 xQueueHandle xTCPISRQueue = NULL;
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188 /* Dynamically generate and send an html page. */
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189 static void prvSendSamplePage( void );
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191 /* Read a register from the WIZnet device via the i2c interface. */
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192 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength );
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194 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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195 static void prvFlushBuffer( unsigned portLONG ulTxAddress );
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197 /* Write a string to the WIZnet Tx buffer. */
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198 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress );
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200 /* Convert a number to a string. */
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201 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore );
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203 /*-----------------------------------------------------------*/
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205 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore )
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207 unsigned portLONG lNibble;
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210 /* Simple routine to convert an unsigned long value into a string in hex
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213 /* For each nibble in the number we are converting. */
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214 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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216 /* Take the top four bits of the number. */
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217 lNibble = ( ulVal >> 28 );
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219 /* We are converting it to a hex string, so is the number in the range
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223 pcBuffer[ lIndex ] = '0' + lNibble;
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228 pcBuffer[ lIndex ] = 'A' + lNibble;
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231 /* Shift off the top nibble so we use the next nibble next time around. */
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235 /* Mark the end of the string with a null terminator. */
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236 pcBuffer[ lIndex ] = 0x00;
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238 /*-----------------------------------------------------------*/
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240 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength )
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242 unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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244 /* Read a register value from the WIZnet device. */
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246 /* First write out the address of the register we want to read. */
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247 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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249 /* Then read back from that address. */
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250 i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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252 /* I2C messages are queued so use the semaphore to wait for the read to
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253 complete - otherwise we will leave this function before the I2C
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254 transactions have completed. */
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255 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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257 /*-----------------------------------------------------------*/
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259 void vTCPHardReset( void )
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261 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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262 WIZnet reset lines active for a few milliseconds. */
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264 /* Make sure the interrupt from the WIZnet is disabled. */
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265 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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267 /* If xMessageComplete is NULL then this is the first time that this
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268 function has been called and the queue and semaphore used in this file
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269 have not yet been created. */
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270 if( xMessageComplete == NULL )
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272 /* Create and obtain the semaphore used when we want to wait for an i2c
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273 message to be completed. */
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274 vSemaphoreCreateBinary( xMessageComplete );
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275 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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277 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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278 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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281 /* Use the GPIO to reset the network hardware. */
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282 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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283 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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285 /* Delay with the network hardware in reset for a short while. */
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286 vTaskDelay( tcpRESET_DELAY );
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288 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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289 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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291 vTaskDelay( tcpINIT_DELAY );
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293 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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294 First enable the EINT0 function of the pin. */
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295 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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297 /* We want the TCP comms to wake us from power save. */
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298 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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300 /* Install the ISR into the VIC - but don't enable it yet! */
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301 portENTER_CRITICAL();
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303 extern void ( vEINT0_ISR_Wrapper )( void );
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305 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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306 VICVectAddr3 = ( portLONG ) vEINT0_ISR_Wrapper;
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308 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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310 portEXIT_CRITICAL();
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312 /* Enable interrupts in the WIZnet itself. */
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313 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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315 vTaskDelay( tcpLONG_DELAY );
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317 /*-----------------------------------------------------------*/
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319 portLONG lTCPSoftReset( void )
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321 unsigned portCHAR ucStatus;
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322 extern volatile portLONG lTransactionCompleted;
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324 /* Send a message to the WIZnet device to tell it set all it's registers
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325 back to their default states. Then setup the WIZnet device as required. */
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327 /* Reset the internal WIZnet registers. */
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328 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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330 /* Now we can configure the protocol. Here the MAC address, gateway
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331 address, subnet mask and IP address are configured. */
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332 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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333 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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334 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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335 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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337 /* Next the memory buffers are configured to give all the WIZnet internal
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338 memory over to a single socket. This gives the socket the maximum internal
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339 Tx and Rx buffer space. */
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340 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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341 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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343 /* Send the sys init command so the above parameters take effect. */
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344 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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346 /* Seems to like a little wait here. */
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347 vTaskDelay( tcpINIT_DELAY );
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349 /* Read back the status to ensure the system initialised ok. */
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350 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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352 /* We should find that the sys init was successful. */
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353 if( ucStatus != tcpISR_SYS_INIT )
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355 return ( portLONG ) pdFAIL;
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358 /* No i2c errors yet. */
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359 portENTER_CRITICAL();
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360 lTransactionCompleted = pdTRUE;
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361 portEXIT_CRITICAL();
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363 return ( portLONG ) pdPASS;
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365 /*-----------------------------------------------------------*/
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367 portLONG lTCPCreateSocket( void )
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369 unsigned portCHAR ucStatus;
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371 /* Create and configure a socket. */
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373 /* Setup and init the socket. Here the port number is set and the socket
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375 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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376 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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377 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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379 /* Wait for the Init command to be sent. */
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380 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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382 /* For some reason the message was not transmitted within our block
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384 return ( portLONG ) pdFAIL;
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387 /* Allow the socket to initialise. */
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388 vTaskDelay( tcpINIT_DELAY );
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390 /* Read back the status to ensure the socket initialised ok. */
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391 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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393 /* We should find that the socket init was successful. */
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394 if( ucStatus != tcpISR_SOCKET_INIT )
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396 return ( portLONG ) pdFAIL;
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400 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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401 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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402 vTaskDelay( tcpSHORT_DELAY );
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403 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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404 vTaskDelay( tcpSHORT_DELAY );
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405 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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406 vTaskDelay( tcpSHORT_DELAY );
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408 return ( portLONG ) pdPASS;
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410 /*-----------------------------------------------------------*/
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412 void vTCPListen( void )
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414 unsigned portCHAR ucISR;
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416 /* Start a passive listen on the socket. */
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418 /* Enable interrupts in the WizNet device after ensuring none are
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419 currently pending. */
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420 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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422 /* The WIZnet device is still asserting and interrupt so tell it to
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424 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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425 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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428 SCB_EXTINT = tcpCLEAR_EINT0;
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431 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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433 /* Just clearing the queue used by the ISR routine to tell this task
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434 that the WIZnet device needs attention. */
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437 /* Now all the pending interrupts have been cleared we can enable the
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438 processor interrupts. */
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439 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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441 /* Then start listening for incoming connections. */
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442 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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444 /*-----------------------------------------------------------*/
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446 portLONG lProcessConnection( void )
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448 unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow;
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449 extern volatile portLONG lTransactionCompleted;
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450 portLONG lSameStateCount = 0, lDataSent = pdFALSE;
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451 unsigned portLONG ulWritePointer, ulAckPointer;
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453 /* No I2C errors can yet have occurred. */
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454 portENTER_CRITICAL();
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455 lTransactionCompleted = pdTRUE;
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456 portEXIT_CRITICAL();
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458 /* Keep looping - processing interrupts, until we have completed a
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459 transaction. This uses the WIZnet in it's simplest form. The socket
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460 accepts a connection - we process the connection - then close the socket.
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461 We then go back to reinitialise everything and start again. */
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462 while( lTransactionCompleted == pdTRUE )
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464 /* Wait for a message on the queue from the WIZnet ISR. When the
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465 WIZnet device asserts an interrupt the ISR simply posts a message
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466 onto this queue to wake this task. */
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467 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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469 /* The ISR posted a message on this queue to tell us that the
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470 WIZnet device asserted an interrupt. The ISR cannot process
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471 an I2C message so cannot tell us what caused the interrupt so
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472 we have to query the device here. This task is the highest
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473 priority in the system so will run immediately following the ISR. */
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474 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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476 /* Once we have read what caused the ISR we can clear the interrupt
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478 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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480 /* Now we can clear the processor interrupt and re-enable ready for
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482 SCB_EXTINT = tcpCLEAR_EINT0;
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483 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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485 /* Process the interrupt ... */
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487 if( ucISR & tcpISR_ESTABLISHED )
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489 /* A connection has been established - respond by sending
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490 a receive command. */
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491 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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494 if( ucISR & tcpISR_RX_COMPLETE )
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496 /* We message has been received. This will be an HTTP get
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497 command. We only have one page to send so just send it without
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498 regard to what the actual requested page was. */
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499 prvSendSamplePage();
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502 if( ucISR & tcpISR_TX_COMPLETE )
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504 /* We have a TX complete interrupt - which oddly does not
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505 indicate that the message being sent is complete so we cannot
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506 yet close the socket. Instead we read the position of the Tx
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507 pointer within the WIZnet device so we know how much data it
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508 has to send. Later we will read the ack pointer and compare
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509 this to the Tx pointer to ascertain whether the transmission
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512 /* First read the shadow register. */
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513 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
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515 /* Now a short delay is required. */
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516 vTaskDelay( tcpSHORT_DELAY );
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518 /* Then we can read the real register. */
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519 prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
\r
521 /* We cannot do anything more here but need to remember that
\r
522 this interrupt has occurred. */
\r
523 lDataSent = pdTRUE;
\r
526 if( ucISR & tcpISR_CLOSED )
\r
528 /* The socket has been closed so we can leave this function. */
\r
529 lTransactionCompleted = pdFALSE;
\r
534 /* We have not received an interrupt from the WIZnet device for a
\r
535 while. Read the socket status and check that everything is as
\r
537 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
539 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
541 /* The socket is established and we have already received a Tx
\r
542 end interrupt. We must therefore be waiting for the Tx buffer
\r
543 inside the WIZnet device to be empty before we can close the
\r
546 Read the Ack pointer register to see if it has caught up with
\r
547 the Tx pointer register. First we have to read the shadow
\r
549 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
550 vTaskDelay( tcpSHORT_DELAY );
\r
551 prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
553 if( ulAckPointer == ulWritePointer )
\r
555 /* The Ack and write pointer are now equal and we can
\r
556 safely close the socket. */
\r
557 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
561 /* Keep a count of how many times we encounter the Tx
\r
562 buffer still containing data. */
\r
564 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
566 /* Assume we cannot complete sending the data and
\r
567 therefore cannot safely close the socket. Start over. */
\r
569 lTransactionCompleted = pdFALSE;
\r
573 else if( ucState != tcpSTATUS_LISTEN )
\r
575 /* If we have not yet received a Tx end interrupt we would only
\r
576 ever expect to find the socket still listening for any
\r
577 sustained period. */
\r
578 if( ucState == ucLastState )
\r
581 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
583 /* We are persistently in an unexpected state. Assume
\r
584 we cannot safely close the socket and start over. */
\r
586 lTransactionCompleted = pdFALSE;
\r
592 /* We are in the listen state so are happy that everything
\r
594 lSameStateCount = 0;
\r
597 /* Remember what state we are in this time around so we can check
\r
598 for a persistence on an unexpected state. */
\r
599 ucLastState = ucState;
\r
603 /* We are going to reinitialise the WIZnet device so do not want our
\r
604 interrupts from the WIZnet to be processed. */
\r
605 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
606 return lTransactionCompleted;
\r
608 /*-----------------------------------------------------------*/
\r
610 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress )
\r
612 unsigned portLONG ulSendAddress;
\r
614 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
616 /* Calculate the address to which we are going to write in the buffer. */
\r
617 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
619 /* Send the buffer to the calculated address. Use the semaphore so we
\r
620 can wait until the entire message has been transferred. */
\r
621 i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
623 /* Wait until the semaphore indicates that the message has been transferred. */
\r
624 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
629 /* Return the new address of the end of the buffer (within the WIZnet
\r
631 *pulTxAddress += ( unsigned portLONG ) lTxLen;
\r
633 /*-----------------------------------------------------------*/
\r
635 static void prvFlushBuffer( unsigned portLONG ulTxAddress )
\r
637 unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
639 /* We have written some data to the Tx buffer internal to the WIZnet
\r
640 device. Now we update the Tx pointer inside the WIZnet then send a
\r
641 Send command - which causes the data up to the new Tx pointer to be
\r
644 /* Make sure endieness is correct for transmission. */
\r
645 ulTxAddress = htonl( ulTxAddress );
\r
647 /* Place the new Tx pointer in the string to be transmitted. */
\r
648 ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
650 ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
652 ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
654 ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
657 /* And send it to the WIZnet device. */
\r
658 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
660 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
665 vTaskDelay( tcpSHORT_DELAY );
\r
668 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
670 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
675 /*-----------------------------------------------------------*/
\r
677 static void prvSendSamplePage( void )
\r
679 extern portLONG lErrorInTask;
\r
680 unsigned portLONG ulTxAddress;
\r
681 unsigned portCHAR ucShadow;
\r
683 static unsigned portLONG ulRefreshCount = 0x00;
\r
684 static portCHAR cPageBuffer[ tcpBUFFER_LEN ];
\r
687 /* This function just generates a sample page of HTML which gets
\r
688 sent each time a client attaches to the socket. The page is created
\r
689 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
690 with a bit of dynamically generated data in the middle. */
\r
692 /* We need to know the address to which the html string should be sent
\r
693 in the WIZnet Tx buffer. First read the shadow register. */
\r
694 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
696 /* Now a short delay is required. */
\r
697 vTaskDelay( tcpSHORT_DELAY );
\r
699 /* Now we can read the real pointer value. */
\r
700 prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
702 /* Make sure endieness is correct. */
\r
703 ulTxAddress = htonl( ulTxAddress );
\r
705 /* Send the start of the page. */
\r
706 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
708 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
710 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
711 lIndex = strlen( cPageBuffer );
\r
712 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
713 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
714 lIndex = strlen( cPageBuffer );
\r
715 ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
716 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
717 lIndex = strlen( cPageBuffer );
\r
718 ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
719 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
720 lIndex = strlen( cPageBuffer );
\r
721 ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
725 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
729 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
734 /* Send the dynamically generated string. */
\r
735 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
737 /* Finish the page. */
\r
738 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
740 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
741 prvFlushBuffer( ulTxAddress );
\r