2 FreeRTOS.org V5.1.1 - Copyright (C) 2003-2008 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 ***************************************************************************
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29 * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
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30 * and even write all or part of your application on your behalf. *
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31 * See http://www.OpenRTOS.com for details of the services we provide to *
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32 * expedite your project. *
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34 ***************************************************************************
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35 ***************************************************************************
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37 Please ensure to read the configuration and relevant port sections of the
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38 online documentation.
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40 http://www.FreeRTOS.org - Documentation, latest information, license and
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43 http://www.SafeRTOS.com - A version that is certified for use in safety
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46 http://www.OpenRTOS.com - Commercial support, development, porting,
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47 licensing and training services.
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53 + Modified char* types to compile without warning when using GCC V4.0.1.
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54 + Corrected the address to which the MAC address is written. Thanks to
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55 Bill Knight for this correction.
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59 + Changed the default MAC address to something more realistic.
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63 /* Standard includes. */
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67 /* Scheduler include files. */
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68 #include "FreeRTOS.h"
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74 /* Application includes. */
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76 #include "html_pages.h"
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78 /*-----------------------------------------------------------*/
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80 /* Hardwired i2c address of the WIZNet device. */
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81 #define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 )
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83 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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85 #define tcp8K_RX ( ( unsigned portCHAR ) 0x03 )
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86 #define tcp8K_TX ( ( unsigned portCHAR ) 0x03 )
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88 /* Constants used to generate the WIZnet internal buffer addresses. */
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89 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff )
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90 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 )
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92 /* Bit definitions of the commands that can be sent to the command register. */
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93 #define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 )
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94 #define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 )
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95 #define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 )
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96 #define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 )
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97 #define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 )
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98 #define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 )
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99 #define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 )
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100 #define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 )
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102 /* Constants required to handle the interrupts. */
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103 #define tcpCLEAR_EINT0 ( 1 )
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104 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff )
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105 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 )
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106 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 )
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107 #define tcpWAKE_ON_EINT0 ( 1 )
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108 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 )
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109 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 )
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110 #define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 )
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111 #define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
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113 /* Various delays used in the driver. */
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114 #define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )
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115 #define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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116 #define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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117 #define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS )
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118 #define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS )
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119 #define tcpNO_DELAY ( ( portTickType ) 0 )
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121 /* Length of the data to read for various register reads. */
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122 #define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 )
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123 #define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 )
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125 /* Register addresses within the WIZnet device. */
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126 #define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 )
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127 #define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 )
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128 #define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 )
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129 #define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 )
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130 #define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E )
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131 #define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 )
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132 #define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE )
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133 #define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 )
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134 #define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 )
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135 #define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 )
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136 #define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 )
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137 #define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 )
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138 #define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 )
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139 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 )
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140 #define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 )
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141 #define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 )
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142 #define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 )
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143 #define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 )
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145 /* Constants required for hardware setup. */
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146 #define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 )
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147 #define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 )
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149 /* Constants defining the source of the WIZnet ISR. */
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150 #define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 )
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151 #define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 )
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152 #define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 )
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153 #define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 )
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154 #define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 )
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155 #define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 )
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156 #define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 )
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158 /* Constants defining the socket status bits. */
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159 #define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 )
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160 #define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 )
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162 /* Misc constants. */
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163 #define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 )
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164 #define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 )
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165 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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166 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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167 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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168 #define tcpBUFFER_LEN ( 4 * 1024 )
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169 #define tcpMAX_REGISTER_LEN ( 4 )
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170 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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171 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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173 /* Message definitions. The IP address, MAC address, gateway address, etc.
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175 const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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176 const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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177 const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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178 const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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180 /* Other fixed messages. */
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181 const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD };
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182 const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD };
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183 const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM };
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184 const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC };
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185 const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT };
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186 const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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187 const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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188 const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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189 const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD };
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190 const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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191 const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX };
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192 const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX };
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193 const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD };
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194 const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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195 const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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196 const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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197 const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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199 static xSemaphoreHandle xMessageComplete = NULL;
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200 xQueueHandle xTCPISRQueue = NULL;
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202 /* Dynamically generate and send an html page. */
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203 static void prvSendSamplePage( void );
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205 /* Read a register from the WIZnet device via the i2c interface. */
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206 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength );
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208 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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209 static void prvFlushBuffer( unsigned portLONG ulTxAddress );
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211 /* Write a string to the WIZnet Tx buffer. */
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212 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress );
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214 /* Convert a number to a string. */
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215 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore );
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217 /*-----------------------------------------------------------*/
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219 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore )
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221 unsigned portLONG lNibble;
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224 /* Simple routine to convert an unsigned long value into a string in hex
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227 /* For each nibble in the number we are converting. */
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228 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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230 /* Take the top four bits of the number. */
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231 lNibble = ( ulVal >> 28 );
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233 /* We are converting it to a hex string, so is the number in the range
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237 pcBuffer[ lIndex ] = '0' + lNibble;
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242 pcBuffer[ lIndex ] = 'A' + lNibble;
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245 /* Shift off the top nibble so we use the next nibble next time around. */
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249 /* Mark the end of the string with a null terminator. */
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250 pcBuffer[ lIndex ] = 0x00;
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252 /*-----------------------------------------------------------*/
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254 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength )
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256 unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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258 /* Read a register value from the WIZnet device. */
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260 /* First write out the address of the register we want to read. */
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261 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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263 /* Then read back from that address. */
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264 i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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266 /* I2C messages are queued so use the semaphore to wait for the read to
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267 complete - otherwise we will leave this function before the I2C
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268 transactions have completed. */
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269 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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271 /*-----------------------------------------------------------*/
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273 void vTCPHardReset( void )
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275 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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276 WIZnet reset lines active for a few milliseconds. */
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278 /* Make sure the interrupt from the WIZnet is disabled. */
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279 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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281 /* If xMessageComplete is NULL then this is the first time that this
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282 function has been called and the queue and semaphore used in this file
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283 have not yet been created. */
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284 if( xMessageComplete == NULL )
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286 /* Create and obtain the semaphore used when we want to wait for an i2c
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287 message to be completed. */
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288 vSemaphoreCreateBinary( xMessageComplete );
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289 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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291 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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292 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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295 /* Use the GPIO to reset the network hardware. */
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296 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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297 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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299 /* Delay with the network hardware in reset for a short while. */
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300 vTaskDelay( tcpRESET_DELAY );
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302 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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303 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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305 vTaskDelay( tcpINIT_DELAY );
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307 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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308 First enable the EINT0 function of the pin. */
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309 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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311 /* We want the TCP comms to wake us from power save. */
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312 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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314 /* Install the ISR into the VIC - but don't enable it yet! */
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315 portENTER_CRITICAL();
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317 extern void ( vEINT0_ISR_Wrapper )( void );
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319 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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320 VICVectAddr3 = ( portLONG ) vEINT0_ISR_Wrapper;
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322 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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324 portEXIT_CRITICAL();
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326 /* Enable interrupts in the WIZnet itself. */
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327 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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329 vTaskDelay( tcpLONG_DELAY );
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331 /*-----------------------------------------------------------*/
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333 portLONG lTCPSoftReset( void )
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335 unsigned portCHAR ucStatus;
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336 extern volatile portLONG lTransactionCompleted;
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338 /* Send a message to the WIZnet device to tell it set all it's registers
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339 back to their default states. Then setup the WIZnet device as required. */
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341 /* Reset the internal WIZnet registers. */
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342 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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344 /* Now we can configure the protocol. Here the MAC address, gateway
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345 address, subnet mask and IP address are configured. */
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346 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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347 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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348 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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349 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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351 /* Next the memory buffers are configured to give all the WIZnet internal
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352 memory over to a single socket. This gives the socket the maximum internal
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353 Tx and Rx buffer space. */
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354 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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355 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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357 /* Send the sys init command so the above parameters take effect. */
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358 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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360 /* Seems to like a little wait here. */
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361 vTaskDelay( tcpINIT_DELAY );
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363 /* Read back the status to ensure the system initialised ok. */
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364 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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366 /* We should find that the sys init was successful. */
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367 if( ucStatus != tcpISR_SYS_INIT )
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369 return ( portLONG ) pdFAIL;
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372 /* No i2c errors yet. */
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373 portENTER_CRITICAL();
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374 lTransactionCompleted = pdTRUE;
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375 portEXIT_CRITICAL();
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377 return ( portLONG ) pdPASS;
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379 /*-----------------------------------------------------------*/
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381 portLONG lTCPCreateSocket( void )
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383 unsigned portCHAR ucStatus;
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385 /* Create and configure a socket. */
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387 /* Setup and init the socket. Here the port number is set and the socket
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389 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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390 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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391 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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393 /* Wait for the Init command to be sent. */
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394 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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396 /* For some reason the message was not transmitted within our block
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398 return ( portLONG ) pdFAIL;
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401 /* Allow the socket to initialise. */
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402 vTaskDelay( tcpINIT_DELAY );
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404 /* Read back the status to ensure the socket initialised ok. */
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405 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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407 /* We should find that the socket init was successful. */
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408 if( ucStatus != tcpISR_SOCKET_INIT )
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410 return ( portLONG ) pdFAIL;
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414 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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415 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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416 vTaskDelay( tcpSHORT_DELAY );
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417 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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418 vTaskDelay( tcpSHORT_DELAY );
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419 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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420 vTaskDelay( tcpSHORT_DELAY );
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422 return ( portLONG ) pdPASS;
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424 /*-----------------------------------------------------------*/
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426 void vTCPListen( void )
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428 unsigned portCHAR ucISR;
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430 /* Start a passive listen on the socket. */
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432 /* Enable interrupts in the WizNet device after ensuring none are
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433 currently pending. */
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434 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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436 /* The WIZnet device is still asserting and interrupt so tell it to
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438 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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439 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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442 SCB_EXTINT = tcpCLEAR_EINT0;
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445 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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447 /* Just clearing the queue used by the ISR routine to tell this task
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448 that the WIZnet device needs attention. */
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451 /* Now all the pending interrupts have been cleared we can enable the
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452 processor interrupts. */
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453 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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455 /* Then start listening for incoming connections. */
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456 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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458 /*-----------------------------------------------------------*/
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460 portLONG lProcessConnection( void )
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462 unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow;
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463 extern volatile portLONG lTransactionCompleted;
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464 portLONG lSameStateCount = 0, lDataSent = pdFALSE;
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465 unsigned portLONG ulWritePointer, ulAckPointer;
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467 /* No I2C errors can yet have occurred. */
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468 portENTER_CRITICAL();
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469 lTransactionCompleted = pdTRUE;
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470 portEXIT_CRITICAL();
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472 /* Keep looping - processing interrupts, until we have completed a
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473 transaction. This uses the WIZnet in it's simplest form. The socket
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474 accepts a connection - we process the connection - then close the socket.
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475 We then go back to reinitialise everything and start again. */
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476 while( lTransactionCompleted == pdTRUE )
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478 /* Wait for a message on the queue from the WIZnet ISR. When the
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479 WIZnet device asserts an interrupt the ISR simply posts a message
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480 onto this queue to wake this task. */
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481 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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483 /* The ISR posted a message on this queue to tell us that the
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484 WIZnet device asserted an interrupt. The ISR cannot process
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485 an I2C message so cannot tell us what caused the interrupt so
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486 we have to query the device here. This task is the highest
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487 priority in the system so will run immediately following the ISR. */
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488 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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490 /* Once we have read what caused the ISR we can clear the interrupt
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492 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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494 /* Now we can clear the processor interrupt and re-enable ready for
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496 SCB_EXTINT = tcpCLEAR_EINT0;
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497 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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499 /* Process the interrupt ... */
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501 if( ucISR & tcpISR_ESTABLISHED )
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503 /* A connection has been established - respond by sending
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504 a receive command. */
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505 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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508 if( ucISR & tcpISR_RX_COMPLETE )
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510 /* We message has been received. This will be an HTTP get
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511 command. We only have one page to send so just send it without
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512 regard to what the actual requested page was. */
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513 prvSendSamplePage();
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516 if( ucISR & tcpISR_TX_COMPLETE )
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518 /* We have a TX complete interrupt - which oddly does not
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519 indicate that the message being sent is complete so we cannot
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520 yet close the socket. Instead we read the position of the Tx
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521 pointer within the WIZnet device so we know how much data it
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522 has to send. Later we will read the ack pointer and compare
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523 this to the Tx pointer to ascertain whether the transmission
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526 /* First read the shadow register. */
\r
527 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
529 /* Now a short delay is required. */
\r
530 vTaskDelay( tcpSHORT_DELAY );
\r
532 /* Then we can read the real register. */
\r
533 prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
\r
535 /* We cannot do anything more here but need to remember that
\r
536 this interrupt has occurred. */
\r
537 lDataSent = pdTRUE;
\r
540 if( ucISR & tcpISR_CLOSED )
\r
542 /* The socket has been closed so we can leave this function. */
\r
543 lTransactionCompleted = pdFALSE;
\r
548 /* We have not received an interrupt from the WIZnet device for a
\r
549 while. Read the socket status and check that everything is as
\r
551 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
553 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
555 /* The socket is established and we have already received a Tx
\r
556 end interrupt. We must therefore be waiting for the Tx buffer
\r
557 inside the WIZnet device to be empty before we can close the
\r
560 Read the Ack pointer register to see if it has caught up with
\r
561 the Tx pointer register. First we have to read the shadow
\r
563 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
564 vTaskDelay( tcpSHORT_DELAY );
\r
565 prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
567 if( ulAckPointer == ulWritePointer )
\r
569 /* The Ack and write pointer are now equal and we can
\r
570 safely close the socket. */
\r
571 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
575 /* Keep a count of how many times we encounter the Tx
\r
576 buffer still containing data. */
\r
578 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
580 /* Assume we cannot complete sending the data and
\r
581 therefore cannot safely close the socket. Start over. */
\r
583 lTransactionCompleted = pdFALSE;
\r
587 else if( ucState != tcpSTATUS_LISTEN )
\r
589 /* If we have not yet received a Tx end interrupt we would only
\r
590 ever expect to find the socket still listening for any
\r
591 sustained period. */
\r
592 if( ucState == ucLastState )
\r
595 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
597 /* We are persistently in an unexpected state. Assume
\r
598 we cannot safely close the socket and start over. */
\r
600 lTransactionCompleted = pdFALSE;
\r
606 /* We are in the listen state so are happy that everything
\r
608 lSameStateCount = 0;
\r
611 /* Remember what state we are in this time around so we can check
\r
612 for a persistence on an unexpected state. */
\r
613 ucLastState = ucState;
\r
617 /* We are going to reinitialise the WIZnet device so do not want our
\r
618 interrupts from the WIZnet to be processed. */
\r
619 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
620 return lTransactionCompleted;
\r
622 /*-----------------------------------------------------------*/
\r
624 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress )
\r
626 unsigned portLONG ulSendAddress;
\r
628 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
630 /* Calculate the address to which we are going to write in the buffer. */
\r
631 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
633 /* Send the buffer to the calculated address. Use the semaphore so we
\r
634 can wait until the entire message has been transferred. */
\r
635 i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
637 /* Wait until the semaphore indicates that the message has been transferred. */
\r
638 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
643 /* Return the new address of the end of the buffer (within the WIZnet
\r
645 *pulTxAddress += ( unsigned portLONG ) lTxLen;
\r
647 /*-----------------------------------------------------------*/
\r
649 static void prvFlushBuffer( unsigned portLONG ulTxAddress )
\r
651 unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
653 /* We have written some data to the Tx buffer internal to the WIZnet
\r
654 device. Now we update the Tx pointer inside the WIZnet then send a
\r
655 Send command - which causes the data up to the new Tx pointer to be
\r
658 /* Make sure endieness is correct for transmission. */
\r
659 ulTxAddress = htonl( ulTxAddress );
\r
661 /* Place the new Tx pointer in the string to be transmitted. */
\r
662 ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
664 ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
666 ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
668 ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
671 /* And send it to the WIZnet device. */
\r
672 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
674 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
679 vTaskDelay( tcpSHORT_DELAY );
\r
682 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
684 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
689 /*-----------------------------------------------------------*/
\r
691 static void prvSendSamplePage( void )
\r
693 extern portLONG lErrorInTask;
\r
694 unsigned portLONG ulTxAddress;
\r
695 unsigned portCHAR ucShadow;
\r
697 static unsigned portLONG ulRefreshCount = 0x00;
\r
698 static portCHAR cPageBuffer[ tcpBUFFER_LEN ];
\r
701 /* This function just generates a sample page of HTML which gets
\r
702 sent each time a client attaches to the socket. The page is created
\r
703 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
704 with a bit of dynamically generated data in the middle. */
\r
706 /* We need to know the address to which the html string should be sent
\r
707 in the WIZnet Tx buffer. First read the shadow register. */
\r
708 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
710 /* Now a short delay is required. */
\r
711 vTaskDelay( tcpSHORT_DELAY );
\r
713 /* Now we can read the real pointer value. */
\r
714 prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
716 /* Make sure endieness is correct. */
\r
717 ulTxAddress = htonl( ulTxAddress );
\r
719 /* Send the start of the page. */
\r
720 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
722 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
724 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
725 lIndex = strlen( cPageBuffer );
\r
726 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
727 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
728 lIndex = strlen( cPageBuffer );
\r
729 ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
730 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
731 lIndex = strlen( cPageBuffer );
\r
732 ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
733 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
734 lIndex = strlen( cPageBuffer );
\r
735 ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
739 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
743 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
748 /* Send the dynamically generated string. */
\r
749 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
751 /* Finish the page. */
\r
752 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
754 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
755 prvFlushBuffer( ulTxAddress );
\r