2 FreeRTOS V7.0.0 - Copyright (C) 2011 Real Time Engineers Ltd.
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5 ***************************************************************************
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7 * FreeRTOS tutorial books are available in pdf and paperback. *
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8 * Complete, revised, and edited pdf reference manuals are also *
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11 * Purchasing FreeRTOS documentation will not only help you, by *
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12 * ensuring you get running as quickly as possible and with an *
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13 * in-depth knowledge of how to use FreeRTOS, it will also help *
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14 * the FreeRTOS project to continue with its mission of providing *
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15 * professional grade, cross platform, de facto standard solutions *
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16 * for microcontrollers - completely free of charge! *
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18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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20 * Thank you for using FreeRTOS, and thank you for your support! *
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22 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 >>>NOTE<<< The modification to the GPL is included to allow you to
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31 distribute a combined work that includes FreeRTOS without being obliged to
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32 provide the source code for proprietary components outside of the FreeRTOS
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33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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57 + Modified char* types to compile without warning when using GCC V4.0.1.
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58 + Corrected the address to which the MAC address is written. Thanks to
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59 Bill Knight for this correction.
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63 + Changed the default MAC address to something more realistic.
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67 /* Standard includes. */
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71 /* Scheduler include files. */
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72 #include "FreeRTOS.h"
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78 /* Application includes. */
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80 #include "html_pages.h"
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82 /*-----------------------------------------------------------*/
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84 /* Hardwired i2c address of the WIZNet device. */
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85 #define tcpDEVICE_ADDRESS ( ( unsigned char ) 0x00 )
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87 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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89 #define tcp8K_RX ( ( unsigned char ) 0x03 )
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90 #define tcp8K_TX ( ( unsigned char ) 0x03 )
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92 /* Constants used to generate the WIZnet internal buffer addresses. */
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93 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned long ) 0x1fff )
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94 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned long ) 0x4000 )
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96 /* Bit definitions of the commands that can be sent to the command register. */
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97 #define tcpRESET_CMD ( ( unsigned char ) 0x80 )
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98 #define tcpSYS_INIT_CMD ( ( unsigned char ) 0x01 )
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99 #define tcpSOCK_STREAM ( ( unsigned char ) 0x01 )
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100 #define tcpSOCK_INIT ( ( unsigned char ) 0x02 )
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101 #define tcpLISTEN_CMD ( ( unsigned char ) 0x08 )
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102 #define tcpRECEIVE_CMD ( ( unsigned char ) 0x40 )
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103 #define tcpDISCONNECT_CMD ( ( unsigned char ) 0x10 )
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104 #define tcpSEND_CMD ( ( unsigned char ) 0x20 )
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106 /* Constants required to handle the interrupts. */
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107 #define tcpCLEAR_EINT0 ( 1 )
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108 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned char ) 0xff )
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109 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned char ) 0x01 )
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110 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned char ) 0x00 )
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111 #define tcpWAKE_ON_EINT0 ( 1 )
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112 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned long ) 0x01 )
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113 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned long ) 0x4000 )
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114 #define tcpEINT0_VIC_CHANNEL ( ( unsigned long ) 14 )
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115 #define tcpEINT0_VIC_ENABLE ( ( unsigned long ) 0x0020 )
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117 /* Various delays used in the driver. */
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118 #define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )
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119 #define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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120 #define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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121 #define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS )
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122 #define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS )
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123 #define tcpNO_DELAY ( ( portTickType ) 0 )
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125 /* Length of the data to read for various register reads. */
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126 #define tcpSTATUS_READ_LEN ( ( unsigned long ) 1 )
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127 #define tcpSHADOW_READ_LEN ( ( unsigned long ) 1 )
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129 /* Register addresses within the WIZnet device. */
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130 #define tcpCOMMAND_REG ( ( unsigned short ) 0x0000 )
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131 #define tcpGATEWAY_ADDR_REG ( ( unsigned short ) 0x0080 )
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132 #define tcpSUBNET_MASK_REG ( ( unsigned short ) 0x0084 )
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133 #define tcpSOURCE_HA_REG ( ( unsigned short ) 0x0088 )
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134 #define tpcSOURCE_IP_REG ( ( unsigned short ) 0x008E )
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135 #define tpcSOCKET_OPT_REG ( ( unsigned short ) 0x00A1 )
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136 #define tcpSOURCE_PORT_REG ( ( unsigned short ) 0x00AE )
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137 #define tcpTX_WRITE_POINTER_REG ( ( unsigned short ) 0x0040 )
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138 #define tcpTX_READ_POINTER_REG ( ( unsigned short ) 0x0044 )
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139 #define tcpTX_ACK_POINTER_REG ( ( unsigned short ) 0x0018 )
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140 #define tcpTX_MEM_SIZE_REG ( ( unsigned short ) 0x0096 )
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141 #define tcpRX_MEM_SIZE_REG ( ( unsigned short ) 0x0095 )
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142 #define tcpINTERRUPT_STATUS_REG ( ( unsigned short ) 0x0004 )
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143 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned short ) 0x01F0 )
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144 #define tcpTX_ACK_SHADOW_REG ( ( unsigned short ) 0x01E2 )
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145 #define tcpISR_MASK_REG ( ( unsigned short ) 0x0009 )
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146 #define tcpINTERRUPT_REG ( ( unsigned short ) 0x0008 )
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147 #define tcpSOCKET_STATE_REG ( ( unsigned short ) 0x00a0 )
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149 /* Constants required for hardware setup. */
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150 #define tcpRESET_ACTIVE_LOW ( ( unsigned long ) 0x20 )
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151 #define tcpRESET_ACTIVE_HIGH ( ( unsigned long ) 0x10 )
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153 /* Constants defining the source of the WIZnet ISR. */
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154 #define tcpISR_SYS_INIT ( ( unsigned char ) 0x01 )
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155 #define tcpISR_SOCKET_INIT ( ( unsigned char ) 0x02 )
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156 #define tcpISR_ESTABLISHED ( ( unsigned char ) 0x04 )
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157 #define tcpISR_CLOSED ( ( unsigned char ) 0x08 )
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158 #define tcpISR_TIMEOUT ( ( unsigned char ) 0x10 )
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159 #define tcpISR_TX_COMPLETE ( ( unsigned char ) 0x20 )
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160 #define tcpISR_RX_COMPLETE ( ( unsigned char ) 0x40 )
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162 /* Constants defining the socket status bits. */
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163 #define tcpSTATUS_ESTABLISHED ( ( unsigned char ) 0x06 )
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164 #define tcpSTATUS_LISTEN ( ( unsigned char ) 0x02 )
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166 /* Misc constants. */
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167 #define tcpNO_STATUS_BITS ( ( unsigned char ) 0x00 )
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168 #define i2cNO_ADDR_REQUIRED ( ( unsigned short ) 0x0000 )
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169 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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170 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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171 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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172 #define tcpBUFFER_LEN ( 4 * 1024 )
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173 #define tcpMAX_REGISTER_LEN ( 4 )
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174 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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175 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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177 /* Message definitions. The IP address, MAC address, gateway address, etc.
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179 const unsigned char const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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180 const unsigned char const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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181 const unsigned char const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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182 const unsigned char const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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184 /* Other fixed messages. */
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185 const unsigned char const ucDataReset[] = { tcpRESET_CMD };
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186 const unsigned char const ucDataInit[] = { tcpSYS_INIT_CMD };
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187 const unsigned char const ucDataProtocol[] = { tcpSOCK_STREAM };
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188 const unsigned char const ucDataPort[] = { 0xBA, 0xCC };
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189 const unsigned char const ucDataSockInit[] = { tcpSOCK_INIT };
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190 const unsigned char const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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191 const unsigned char const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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192 const unsigned char const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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193 const unsigned char const ucDataListen[] = { tcpLISTEN_CMD };
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194 const unsigned char const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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195 const unsigned char const ucDataSetTxBufSize[] = { tcp8K_TX };
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196 const unsigned char const ucDataSetRxBufSize[] = { tcp8K_RX };
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197 const unsigned char const ucDataSend[] = { tcpSEND_CMD };
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198 const unsigned char const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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199 const unsigned char const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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200 const unsigned char const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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201 const unsigned char const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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203 static xSemaphoreHandle xMessageComplete = NULL;
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204 xQueueHandle xTCPISRQueue = NULL;
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206 /* Dynamically generate and send an html page. */
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207 static void prvSendSamplePage( void );
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209 /* Read a register from the WIZnet device via the i2c interface. */
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210 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength );
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212 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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213 static void prvFlushBuffer( unsigned long ulTxAddress );
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215 /* Write a string to the WIZnet Tx buffer. */
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216 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress );
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218 /* Convert a number to a string. */
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219 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore );
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221 /*-----------------------------------------------------------*/
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223 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore )
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225 unsigned long lNibble;
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228 /* Simple routine to convert an unsigned long value into a string in hex
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231 /* For each nibble in the number we are converting. */
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232 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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234 /* Take the top four bits of the number. */
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235 lNibble = ( ulVal >> 28 );
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237 /* We are converting it to a hex string, so is the number in the range
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241 pcBuffer[ lIndex ] = '0' + lNibble;
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246 pcBuffer[ lIndex ] = 'A' + lNibble;
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249 /* Shift off the top nibble so we use the next nibble next time around. */
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253 /* Mark the end of the string with a null terminator. */
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254 pcBuffer[ lIndex ] = 0x00;
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256 /*-----------------------------------------------------------*/
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258 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength )
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260 unsigned char ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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262 /* Read a register value from the WIZnet device. */
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264 /* First write out the address of the register we want to read. */
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265 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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267 /* Then read back from that address. */
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268 i2cMessage( ( unsigned char * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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270 /* I2C messages are queued so use the semaphore to wait for the read to
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271 complete - otherwise we will leave this function before the I2C
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272 transactions have completed. */
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273 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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275 /*-----------------------------------------------------------*/
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277 void vTCPHardReset( void )
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279 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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280 WIZnet reset lines active for a few milliseconds. */
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282 /* Make sure the interrupt from the WIZnet is disabled. */
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283 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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285 /* If xMessageComplete is NULL then this is the first time that this
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286 function has been called and the queue and semaphore used in this file
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287 have not yet been created. */
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288 if( xMessageComplete == NULL )
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290 /* Create and obtain the semaphore used when we want to wait for an i2c
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291 message to be completed. */
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292 vSemaphoreCreateBinary( xMessageComplete );
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293 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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295 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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296 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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299 /* Use the GPIO to reset the network hardware. */
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300 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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301 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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303 /* Delay with the network hardware in reset for a short while. */
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304 vTaskDelay( tcpRESET_DELAY );
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306 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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307 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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309 vTaskDelay( tcpINIT_DELAY );
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311 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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312 First enable the EINT0 function of the pin. */
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313 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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315 /* We want the TCP comms to wake us from power save. */
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316 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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318 /* Install the ISR into the VIC - but don't enable it yet! */
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319 portENTER_CRITICAL();
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321 extern void ( vEINT0_ISR_Wrapper )( void );
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323 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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324 VICVectAddr3 = ( long ) vEINT0_ISR_Wrapper;
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326 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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328 portEXIT_CRITICAL();
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330 /* Enable interrupts in the WIZnet itself. */
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331 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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333 vTaskDelay( tcpLONG_DELAY );
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335 /*-----------------------------------------------------------*/
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337 long lTCPSoftReset( void )
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339 unsigned char ucStatus;
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340 extern volatile long lTransactionCompleted;
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342 /* Send a message to the WIZnet device to tell it set all it's registers
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343 back to their default states. Then setup the WIZnet device as required. */
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345 /* Reset the internal WIZnet registers. */
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346 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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348 /* Now we can configure the protocol. Here the MAC address, gateway
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349 address, subnet mask and IP address are configured. */
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350 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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351 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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352 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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353 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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355 /* Next the memory buffers are configured to give all the WIZnet internal
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356 memory over to a single socket. This gives the socket the maximum internal
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357 Tx and Rx buffer space. */
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358 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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359 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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361 /* Send the sys init command so the above parameters take effect. */
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362 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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364 /* Seems to like a little wait here. */
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365 vTaskDelay( tcpINIT_DELAY );
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367 /* Read back the status to ensure the system initialised ok. */
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368 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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370 /* We should find that the sys init was successful. */
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371 if( ucStatus != tcpISR_SYS_INIT )
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373 return ( long ) pdFAIL;
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376 /* No i2c errors yet. */
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377 portENTER_CRITICAL();
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378 lTransactionCompleted = pdTRUE;
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379 portEXIT_CRITICAL();
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381 return ( long ) pdPASS;
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383 /*-----------------------------------------------------------*/
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385 long lTCPCreateSocket( void )
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387 unsigned char ucStatus;
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389 /* Create and configure a socket. */
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391 /* Setup and init the socket. Here the port number is set and the socket
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393 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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394 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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395 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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397 /* Wait for the Init command to be sent. */
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398 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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400 /* For some reason the message was not transmitted within our block
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402 return ( long ) pdFAIL;
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405 /* Allow the socket to initialise. */
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406 vTaskDelay( tcpINIT_DELAY );
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408 /* Read back the status to ensure the socket initialised ok. */
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409 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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411 /* We should find that the socket init was successful. */
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412 if( ucStatus != tcpISR_SOCKET_INIT )
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414 return ( long ) pdFAIL;
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418 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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419 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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420 vTaskDelay( tcpSHORT_DELAY );
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421 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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422 vTaskDelay( tcpSHORT_DELAY );
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423 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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424 vTaskDelay( tcpSHORT_DELAY );
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426 return ( long ) pdPASS;
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428 /*-----------------------------------------------------------*/
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430 void vTCPListen( void )
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432 unsigned char ucISR;
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434 /* Start a passive listen on the socket. */
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436 /* Enable interrupts in the WizNet device after ensuring none are
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437 currently pending. */
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438 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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440 /* The WIZnet device is still asserting and interrupt so tell it to
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442 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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443 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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446 SCB_EXTINT = tcpCLEAR_EINT0;
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449 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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451 /* Just clearing the queue used by the ISR routine to tell this task
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452 that the WIZnet device needs attention. */
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455 /* Now all the pending interrupts have been cleared we can enable the
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456 processor interrupts. */
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457 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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459 /* Then start listening for incoming connections. */
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460 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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462 /*-----------------------------------------------------------*/
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464 long lProcessConnection( void )
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466 unsigned char ucISR, ucState, ucLastState = 2, ucShadow;
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467 extern volatile long lTransactionCompleted;
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468 long lSameStateCount = 0, lDataSent = pdFALSE;
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469 unsigned long ulWritePointer, ulAckPointer;
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471 /* No I2C errors can yet have occurred. */
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472 portENTER_CRITICAL();
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473 lTransactionCompleted = pdTRUE;
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474 portEXIT_CRITICAL();
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476 /* Keep looping - processing interrupts, until we have completed a
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477 transaction. This uses the WIZnet in it's simplest form. The socket
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478 accepts a connection - we process the connection - then close the socket.
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479 We then go back to reinitialise everything and start again. */
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480 while( lTransactionCompleted == pdTRUE )
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482 /* Wait for a message on the queue from the WIZnet ISR. When the
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483 WIZnet device asserts an interrupt the ISR simply posts a message
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484 onto this queue to wake this task. */
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485 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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487 /* The ISR posted a message on this queue to tell us that the
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488 WIZnet device asserted an interrupt. The ISR cannot process
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489 an I2C message so cannot tell us what caused the interrupt so
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490 we have to query the device here. This task is the highest
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491 priority in the system so will run immediately following the ISR. */
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492 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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494 /* Once we have read what caused the ISR we can clear the interrupt
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496 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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498 /* Now we can clear the processor interrupt and re-enable ready for
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500 SCB_EXTINT = tcpCLEAR_EINT0;
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501 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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503 /* Process the interrupt ... */
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505 if( ucISR & tcpISR_ESTABLISHED )
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507 /* A connection has been established - respond by sending
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508 a receive command. */
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509 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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512 if( ucISR & tcpISR_RX_COMPLETE )
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514 /* We message has been received. This will be an HTTP get
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515 command. We only have one page to send so just send it without
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516 regard to what the actual requested page was. */
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517 prvSendSamplePage();
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520 if( ucISR & tcpISR_TX_COMPLETE )
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522 /* We have a TX complete interrupt - which oddly does not
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523 indicate that the message being sent is complete so we cannot
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524 yet close the socket. Instead we read the position of the Tx
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525 pointer within the WIZnet device so we know how much data it
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526 has to send. Later we will read the ack pointer and compare
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527 this to the Tx pointer to ascertain whether the transmission
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530 /* First read the shadow register. */
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531 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
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533 /* Now a short delay is required. */
\r
534 vTaskDelay( tcpSHORT_DELAY );
\r
536 /* Then we can read the real register. */
\r
537 prvReadRegister( ( unsigned char * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
\r
539 /* We cannot do anything more here but need to remember that
\r
540 this interrupt has occurred. */
\r
541 lDataSent = pdTRUE;
\r
544 if( ucISR & tcpISR_CLOSED )
\r
546 /* The socket has been closed so we can leave this function. */
\r
547 lTransactionCompleted = pdFALSE;
\r
552 /* We have not received an interrupt from the WIZnet device for a
\r
553 while. Read the socket status and check that everything is as
\r
555 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
557 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
559 /* The socket is established and we have already received a Tx
\r
560 end interrupt. We must therefore be waiting for the Tx buffer
\r
561 inside the WIZnet device to be empty before we can close the
\r
564 Read the Ack pointer register to see if it has caught up with
\r
565 the Tx pointer register. First we have to read the shadow
\r
567 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
568 vTaskDelay( tcpSHORT_DELAY );
\r
569 prvReadRegister( ( unsigned char * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
571 if( ulAckPointer == ulWritePointer )
\r
573 /* The Ack and write pointer are now equal and we can
\r
574 safely close the socket. */
\r
575 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
579 /* Keep a count of how many times we encounter the Tx
\r
580 buffer still containing data. */
\r
582 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
584 /* Assume we cannot complete sending the data and
\r
585 therefore cannot safely close the socket. Start over. */
\r
587 lTransactionCompleted = pdFALSE;
\r
591 else if( ucState != tcpSTATUS_LISTEN )
\r
593 /* If we have not yet received a Tx end interrupt we would only
\r
594 ever expect to find the socket still listening for any
\r
595 sustained period. */
\r
596 if( ucState == ucLastState )
\r
599 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
601 /* We are persistently in an unexpected state. Assume
\r
602 we cannot safely close the socket and start over. */
\r
604 lTransactionCompleted = pdFALSE;
\r
610 /* We are in the listen state so are happy that everything
\r
612 lSameStateCount = 0;
\r
615 /* Remember what state we are in this time around so we can check
\r
616 for a persistence on an unexpected state. */
\r
617 ucLastState = ucState;
\r
621 /* We are going to reinitialise the WIZnet device so do not want our
\r
622 interrupts from the WIZnet to be processed. */
\r
623 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
624 return lTransactionCompleted;
\r
626 /*-----------------------------------------------------------*/
\r
628 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress )
\r
630 unsigned long ulSendAddress;
\r
632 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
634 /* Calculate the address to which we are going to write in the buffer. */
\r
635 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
637 /* Send the buffer to the calculated address. Use the semaphore so we
\r
638 can wait until the entire message has been transferred. */
\r
639 i2cMessage( ( unsigned char * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned short ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
641 /* Wait until the semaphore indicates that the message has been transferred. */
\r
642 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
647 /* Return the new address of the end of the buffer (within the WIZnet
\r
649 *pulTxAddress += ( unsigned long ) lTxLen;
\r
651 /*-----------------------------------------------------------*/
\r
653 static void prvFlushBuffer( unsigned long ulTxAddress )
\r
655 unsigned char ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
657 /* We have written some data to the Tx buffer internal to the WIZnet
\r
658 device. Now we update the Tx pointer inside the WIZnet then send a
\r
659 Send command - which causes the data up to the new Tx pointer to be
\r
662 /* Make sure endieness is correct for transmission. */
\r
663 ulTxAddress = htonl( ulTxAddress );
\r
665 /* Place the new Tx pointer in the string to be transmitted. */
\r
666 ucTxBuffer[ 0 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
668 ucTxBuffer[ 1 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
670 ucTxBuffer[ 2 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
672 ucTxBuffer[ 3 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
675 /* And send it to the WIZnet device. */
\r
676 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
678 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
683 vTaskDelay( tcpSHORT_DELAY );
\r
686 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
688 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
693 /*-----------------------------------------------------------*/
\r
695 static void prvSendSamplePage( void )
\r
697 extern long lErrorInTask;
\r
698 unsigned long ulTxAddress;
\r
699 unsigned char ucShadow;
\r
701 static unsigned long ulRefreshCount = 0x00;
\r
702 static char cPageBuffer[ tcpBUFFER_LEN ];
\r
705 /* This function just generates a sample page of HTML which gets
\r
706 sent each time a client attaches to the socket. The page is created
\r
707 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
708 with a bit of dynamically generated data in the middle. */
\r
710 /* We need to know the address to which the html string should be sent
\r
711 in the WIZnet Tx buffer. First read the shadow register. */
\r
712 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
714 /* Now a short delay is required. */
\r
715 vTaskDelay( tcpSHORT_DELAY );
\r
717 /* Now we can read the real pointer value. */
\r
718 prvReadRegister( ( unsigned char * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
720 /* Make sure endieness is correct. */
\r
721 ulTxAddress = htonl( ulTxAddress );
\r
723 /* Send the start of the page. */
\r
724 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
726 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
728 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
729 lIndex = strlen( cPageBuffer );
\r
730 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
731 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
732 lIndex = strlen( cPageBuffer );
\r
733 ultoa( ( unsigned long ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
734 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
735 lIndex = strlen( cPageBuffer );
\r
736 ultoa( ( unsigned long ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
737 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
738 lIndex = strlen( cPageBuffer );
\r
739 ultoa( ( unsigned long ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
743 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
747 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
752 /* Send the dynamically generated string. */
\r
753 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
755 /* Finish the page. */
\r
756 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
758 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
759 prvFlushBuffer( ulTxAddress );
\r