2 FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.
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4 This file is part of the FreeRTOS distribution.
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6 FreeRTOS is free software; you can redistribute it and/or modify it under
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7 the terms of the GNU General Public License (version 2) as published by the
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8 Free Software Foundation and modified by the FreeRTOS exception.
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9 **NOTE** The exception to the GPL is included to allow you to distribute a
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10 combined work that includes FreeRTOS without being obliged to provide the
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11 source code for proprietary components outside of the FreeRTOS kernel.
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12 Alternative commercial license and support terms are also available upon
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13 request. See the licensing section of http://www.FreeRTOS.org for full
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16 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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21 You should have received a copy of the GNU General Public License along
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22 with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
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23 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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26 ***************************************************************************
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28 * Looking for a quick start? Then check out the FreeRTOS eBook! *
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29 * See http://www.FreeRTOS.org/Documentation for details *
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31 ***************************************************************************
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35 Please ensure to read the configuration and relevant port sections of the
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36 online documentation.
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38 http://www.FreeRTOS.org - Documentation, latest information, license and
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41 http://www.SafeRTOS.com - A version that is certified for use in safety
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44 http://www.OpenRTOS.com - Commercial support, development, porting,
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45 licensing and training services.
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51 + Modified char* types to compile without warning when using GCC V4.0.1.
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52 + Corrected the address to which the MAC address is written. Thanks to
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53 Bill Knight for this correction.
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57 + Changed the default MAC address to something more realistic.
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61 /* Standard includes. */
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65 /* Scheduler include files. */
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66 #include "FreeRTOS.h"
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72 /* Application includes. */
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74 #include "html_pages.h"
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76 /*-----------------------------------------------------------*/
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78 /* Hardwired i2c address of the WIZNet device. */
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79 #define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 )
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81 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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83 #define tcp8K_RX ( ( unsigned portCHAR ) 0x03 )
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84 #define tcp8K_TX ( ( unsigned portCHAR ) 0x03 )
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86 /* Constants used to generate the WIZnet internal buffer addresses. */
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87 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff )
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88 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 )
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90 /* Bit definitions of the commands that can be sent to the command register. */
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91 #define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 )
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92 #define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 )
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93 #define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 )
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94 #define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 )
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95 #define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 )
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96 #define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 )
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97 #define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 )
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98 #define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 )
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100 /* Constants required to handle the interrupts. */
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101 #define tcpCLEAR_EINT0 ( 1 )
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102 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff )
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103 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 )
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104 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 )
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105 #define tcpWAKE_ON_EINT0 ( 1 )
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106 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 )
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107 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 )
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108 #define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 )
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109 #define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
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111 /* Various delays used in the driver. */
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112 #define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )
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113 #define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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114 #define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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115 #define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS )
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116 #define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS )
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117 #define tcpNO_DELAY ( ( portTickType ) 0 )
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119 /* Length of the data to read for various register reads. */
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120 #define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 )
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121 #define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 )
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123 /* Register addresses within the WIZnet device. */
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124 #define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 )
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125 #define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 )
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126 #define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 )
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127 #define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 )
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128 #define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E )
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129 #define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 )
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130 #define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE )
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131 #define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 )
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132 #define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 )
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133 #define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 )
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134 #define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 )
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135 #define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 )
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136 #define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 )
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137 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 )
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138 #define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 )
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139 #define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 )
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140 #define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 )
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141 #define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 )
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143 /* Constants required for hardware setup. */
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144 #define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 )
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145 #define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 )
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147 /* Constants defining the source of the WIZnet ISR. */
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148 #define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 )
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149 #define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 )
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150 #define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 )
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151 #define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 )
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152 #define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 )
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153 #define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 )
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154 #define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 )
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156 /* Constants defining the socket status bits. */
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157 #define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 )
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158 #define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 )
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160 /* Misc constants. */
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161 #define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 )
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162 #define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 )
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163 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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164 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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165 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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166 #define tcpBUFFER_LEN ( 4 * 1024 )
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167 #define tcpMAX_REGISTER_LEN ( 4 )
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168 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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169 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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171 /* Message definitions. The IP address, MAC address, gateway address, etc.
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173 const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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174 const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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175 const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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176 const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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178 /* Other fixed messages. */
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179 const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD };
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180 const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD };
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181 const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM };
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182 const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC };
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183 const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT };
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184 const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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185 const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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186 const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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187 const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD };
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188 const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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189 const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX };
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190 const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX };
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191 const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD };
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192 const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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193 const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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194 const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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195 const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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197 static xSemaphoreHandle xMessageComplete = NULL;
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198 xQueueHandle xTCPISRQueue = NULL;
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200 /* Dynamically generate and send an html page. */
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201 static void prvSendSamplePage( void );
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203 /* Read a register from the WIZnet device via the i2c interface. */
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204 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength );
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206 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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207 static void prvFlushBuffer( unsigned portLONG ulTxAddress );
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209 /* Write a string to the WIZnet Tx buffer. */
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210 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress );
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212 /* Convert a number to a string. */
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213 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore );
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215 /*-----------------------------------------------------------*/
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217 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore )
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219 unsigned portLONG lNibble;
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222 /* Simple routine to convert an unsigned long value into a string in hex
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225 /* For each nibble in the number we are converting. */
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226 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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228 /* Take the top four bits of the number. */
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229 lNibble = ( ulVal >> 28 );
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231 /* We are converting it to a hex string, so is the number in the range
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235 pcBuffer[ lIndex ] = '0' + lNibble;
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240 pcBuffer[ lIndex ] = 'A' + lNibble;
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243 /* Shift off the top nibble so we use the next nibble next time around. */
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247 /* Mark the end of the string with a null terminator. */
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248 pcBuffer[ lIndex ] = 0x00;
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250 /*-----------------------------------------------------------*/
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252 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength )
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254 unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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256 /* Read a register value from the WIZnet device. */
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258 /* First write out the address of the register we want to read. */
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259 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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261 /* Then read back from that address. */
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262 i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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264 /* I2C messages are queued so use the semaphore to wait for the read to
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265 complete - otherwise we will leave this function before the I2C
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266 transactions have completed. */
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267 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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269 /*-----------------------------------------------------------*/
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271 void vTCPHardReset( void )
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273 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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274 WIZnet reset lines active for a few milliseconds. */
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276 /* Make sure the interrupt from the WIZnet is disabled. */
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277 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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279 /* If xMessageComplete is NULL then this is the first time that this
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280 function has been called and the queue and semaphore used in this file
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281 have not yet been created. */
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282 if( xMessageComplete == NULL )
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284 /* Create and obtain the semaphore used when we want to wait for an i2c
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285 message to be completed. */
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286 vSemaphoreCreateBinary( xMessageComplete );
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287 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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289 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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290 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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293 /* Use the GPIO to reset the network hardware. */
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294 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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295 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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297 /* Delay with the network hardware in reset for a short while. */
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298 vTaskDelay( tcpRESET_DELAY );
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300 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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301 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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303 vTaskDelay( tcpINIT_DELAY );
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305 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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306 First enable the EINT0 function of the pin. */
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307 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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309 /* We want the TCP comms to wake us from power save. */
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310 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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312 /* Install the ISR into the VIC - but don't enable it yet! */
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313 portENTER_CRITICAL();
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315 extern void ( vEINT0_ISR_Wrapper )( void );
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317 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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318 VICVectAddr3 = ( portLONG ) vEINT0_ISR_Wrapper;
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320 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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322 portEXIT_CRITICAL();
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324 /* Enable interrupts in the WIZnet itself. */
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325 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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327 vTaskDelay( tcpLONG_DELAY );
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329 /*-----------------------------------------------------------*/
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331 portLONG lTCPSoftReset( void )
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333 unsigned portCHAR ucStatus;
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334 extern volatile portLONG lTransactionCompleted;
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336 /* Send a message to the WIZnet device to tell it set all it's registers
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337 back to their default states. Then setup the WIZnet device as required. */
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339 /* Reset the internal WIZnet registers. */
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340 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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342 /* Now we can configure the protocol. Here the MAC address, gateway
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343 address, subnet mask and IP address are configured. */
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344 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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345 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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346 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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347 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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349 /* Next the memory buffers are configured to give all the WIZnet internal
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350 memory over to a single socket. This gives the socket the maximum internal
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351 Tx and Rx buffer space. */
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352 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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353 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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355 /* Send the sys init command so the above parameters take effect. */
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356 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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358 /* Seems to like a little wait here. */
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359 vTaskDelay( tcpINIT_DELAY );
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361 /* Read back the status to ensure the system initialised ok. */
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362 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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364 /* We should find that the sys init was successful. */
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365 if( ucStatus != tcpISR_SYS_INIT )
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367 return ( portLONG ) pdFAIL;
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370 /* No i2c errors yet. */
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371 portENTER_CRITICAL();
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372 lTransactionCompleted = pdTRUE;
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373 portEXIT_CRITICAL();
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375 return ( portLONG ) pdPASS;
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377 /*-----------------------------------------------------------*/
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379 portLONG lTCPCreateSocket( void )
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381 unsigned portCHAR ucStatus;
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383 /* Create and configure a socket. */
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385 /* Setup and init the socket. Here the port number is set and the socket
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387 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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388 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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389 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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391 /* Wait for the Init command to be sent. */
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392 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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394 /* For some reason the message was not transmitted within our block
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396 return ( portLONG ) pdFAIL;
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399 /* Allow the socket to initialise. */
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400 vTaskDelay( tcpINIT_DELAY );
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402 /* Read back the status to ensure the socket initialised ok. */
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403 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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405 /* We should find that the socket init was successful. */
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406 if( ucStatus != tcpISR_SOCKET_INIT )
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408 return ( portLONG ) pdFAIL;
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412 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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413 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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414 vTaskDelay( tcpSHORT_DELAY );
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415 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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416 vTaskDelay( tcpSHORT_DELAY );
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417 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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418 vTaskDelay( tcpSHORT_DELAY );
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420 return ( portLONG ) pdPASS;
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422 /*-----------------------------------------------------------*/
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424 void vTCPListen( void )
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426 unsigned portCHAR ucISR;
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428 /* Start a passive listen on the socket. */
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430 /* Enable interrupts in the WizNet device after ensuring none are
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431 currently pending. */
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432 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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434 /* The WIZnet device is still asserting and interrupt so tell it to
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436 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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437 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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440 SCB_EXTINT = tcpCLEAR_EINT0;
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443 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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445 /* Just clearing the queue used by the ISR routine to tell this task
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446 that the WIZnet device needs attention. */
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449 /* Now all the pending interrupts have been cleared we can enable the
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450 processor interrupts. */
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451 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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453 /* Then start listening for incoming connections. */
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454 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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456 /*-----------------------------------------------------------*/
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458 portLONG lProcessConnection( void )
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460 unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow;
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461 extern volatile portLONG lTransactionCompleted;
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462 portLONG lSameStateCount = 0, lDataSent = pdFALSE;
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463 unsigned portLONG ulWritePointer, ulAckPointer;
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465 /* No I2C errors can yet have occurred. */
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466 portENTER_CRITICAL();
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467 lTransactionCompleted = pdTRUE;
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468 portEXIT_CRITICAL();
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470 /* Keep looping - processing interrupts, until we have completed a
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471 transaction. This uses the WIZnet in it's simplest form. The socket
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472 accepts a connection - we process the connection - then close the socket.
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473 We then go back to reinitialise everything and start again. */
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474 while( lTransactionCompleted == pdTRUE )
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476 /* Wait for a message on the queue from the WIZnet ISR. When the
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477 WIZnet device asserts an interrupt the ISR simply posts a message
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478 onto this queue to wake this task. */
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479 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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481 /* The ISR posted a message on this queue to tell us that the
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482 WIZnet device asserted an interrupt. The ISR cannot process
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483 an I2C message so cannot tell us what caused the interrupt so
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484 we have to query the device here. This task is the highest
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485 priority in the system so will run immediately following the ISR. */
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486 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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488 /* Once we have read what caused the ISR we can clear the interrupt
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490 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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492 /* Now we can clear the processor interrupt and re-enable ready for
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494 SCB_EXTINT = tcpCLEAR_EINT0;
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495 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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497 /* Process the interrupt ... */
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499 if( ucISR & tcpISR_ESTABLISHED )
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501 /* A connection has been established - respond by sending
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502 a receive command. */
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503 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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506 if( ucISR & tcpISR_RX_COMPLETE )
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508 /* We message has been received. This will be an HTTP get
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509 command. We only have one page to send so just send it without
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510 regard to what the actual requested page was. */
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511 prvSendSamplePage();
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514 if( ucISR & tcpISR_TX_COMPLETE )
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516 /* We have a TX complete interrupt - which oddly does not
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517 indicate that the message being sent is complete so we cannot
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518 yet close the socket. Instead we read the position of the Tx
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519 pointer within the WIZnet device so we know how much data it
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520 has to send. Later we will read the ack pointer and compare
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521 this to the Tx pointer to ascertain whether the transmission
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524 /* First read the shadow register. */
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525 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
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527 /* Now a short delay is required. */
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528 vTaskDelay( tcpSHORT_DELAY );
\r
530 /* Then we can read the real register. */
\r
531 prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
\r
533 /* We cannot do anything more here but need to remember that
\r
534 this interrupt has occurred. */
\r
535 lDataSent = pdTRUE;
\r
538 if( ucISR & tcpISR_CLOSED )
\r
540 /* The socket has been closed so we can leave this function. */
\r
541 lTransactionCompleted = pdFALSE;
\r
546 /* We have not received an interrupt from the WIZnet device for a
\r
547 while. Read the socket status and check that everything is as
\r
549 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
551 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
553 /* The socket is established and we have already received a Tx
\r
554 end interrupt. We must therefore be waiting for the Tx buffer
\r
555 inside the WIZnet device to be empty before we can close the
\r
558 Read the Ack pointer register to see if it has caught up with
\r
559 the Tx pointer register. First we have to read the shadow
\r
561 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
562 vTaskDelay( tcpSHORT_DELAY );
\r
563 prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
565 if( ulAckPointer == ulWritePointer )
\r
567 /* The Ack and write pointer are now equal and we can
\r
568 safely close the socket. */
\r
569 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
573 /* Keep a count of how many times we encounter the Tx
\r
574 buffer still containing data. */
\r
576 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
578 /* Assume we cannot complete sending the data and
\r
579 therefore cannot safely close the socket. Start over. */
\r
581 lTransactionCompleted = pdFALSE;
\r
585 else if( ucState != tcpSTATUS_LISTEN )
\r
587 /* If we have not yet received a Tx end interrupt we would only
\r
588 ever expect to find the socket still listening for any
\r
589 sustained period. */
\r
590 if( ucState == ucLastState )
\r
593 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
595 /* We are persistently in an unexpected state. Assume
\r
596 we cannot safely close the socket and start over. */
\r
598 lTransactionCompleted = pdFALSE;
\r
604 /* We are in the listen state so are happy that everything
\r
606 lSameStateCount = 0;
\r
609 /* Remember what state we are in this time around so we can check
\r
610 for a persistence on an unexpected state. */
\r
611 ucLastState = ucState;
\r
615 /* We are going to reinitialise the WIZnet device so do not want our
\r
616 interrupts from the WIZnet to be processed. */
\r
617 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
618 return lTransactionCompleted;
\r
620 /*-----------------------------------------------------------*/
\r
622 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress )
\r
624 unsigned portLONG ulSendAddress;
\r
626 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
628 /* Calculate the address to which we are going to write in the buffer. */
\r
629 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
631 /* Send the buffer to the calculated address. Use the semaphore so we
\r
632 can wait until the entire message has been transferred. */
\r
633 i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
635 /* Wait until the semaphore indicates that the message has been transferred. */
\r
636 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
641 /* Return the new address of the end of the buffer (within the WIZnet
\r
643 *pulTxAddress += ( unsigned portLONG ) lTxLen;
\r
645 /*-----------------------------------------------------------*/
\r
647 static void prvFlushBuffer( unsigned portLONG ulTxAddress )
\r
649 unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
651 /* We have written some data to the Tx buffer internal to the WIZnet
\r
652 device. Now we update the Tx pointer inside the WIZnet then send a
\r
653 Send command - which causes the data up to the new Tx pointer to be
\r
656 /* Make sure endieness is correct for transmission. */
\r
657 ulTxAddress = htonl( ulTxAddress );
\r
659 /* Place the new Tx pointer in the string to be transmitted. */
\r
660 ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
662 ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
664 ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
666 ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
669 /* And send it to the WIZnet device. */
\r
670 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
672 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
677 vTaskDelay( tcpSHORT_DELAY );
\r
680 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
682 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
687 /*-----------------------------------------------------------*/
\r
689 static void prvSendSamplePage( void )
\r
691 extern portLONG lErrorInTask;
\r
692 unsigned portLONG ulTxAddress;
\r
693 unsigned portCHAR ucShadow;
\r
695 static unsigned portLONG ulRefreshCount = 0x00;
\r
696 static portCHAR cPageBuffer[ tcpBUFFER_LEN ];
\r
699 /* This function just generates a sample page of HTML which gets
\r
700 sent each time a client attaches to the socket. The page is created
\r
701 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
702 with a bit of dynamically generated data in the middle. */
\r
704 /* We need to know the address to which the html string should be sent
\r
705 in the WIZnet Tx buffer. First read the shadow register. */
\r
706 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
708 /* Now a short delay is required. */
\r
709 vTaskDelay( tcpSHORT_DELAY );
\r
711 /* Now we can read the real pointer value. */
\r
712 prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
714 /* Make sure endieness is correct. */
\r
715 ulTxAddress = htonl( ulTxAddress );
\r
717 /* Send the start of the page. */
\r
718 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
720 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
722 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
723 lIndex = strlen( cPageBuffer );
\r
724 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
725 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
726 lIndex = strlen( cPageBuffer );
\r
727 ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
728 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
729 lIndex = strlen( cPageBuffer );
\r
730 ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
731 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
732 lIndex = strlen( cPageBuffer );
\r
733 ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
737 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
741 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
746 /* Send the dynamically generated string. */
\r
747 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
749 /* Finish the page. */
\r
750 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
752 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
753 prvFlushBuffer( ulTxAddress );
\r