2 FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 ***************************************************************************
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29 * SAVE TIME AND MONEY! Why not get us to quote to get FreeRTOS.org *
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30 * running on your hardware - or even write all or part of your application*
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31 * for you? See http://www.OpenRTOS.com for details. *
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33 ***************************************************************************
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34 ***************************************************************************
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36 Please ensure to read the configuration and relevant port sections of the
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37 online documentation.
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39 http://www.FreeRTOS.org - Documentation, latest information, license and
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42 http://www.SafeRTOS.com - A version that is certified for use in safety
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45 http://www.OpenRTOS.com - Commercial support, development, porting,
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46 licensing and training services.
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52 + Modified char* types to compile without warning when using GCC V4.0.1.
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53 + Corrected the address to which the MAC address is written. Thanks to
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54 Bill Knight for this correction.
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58 + Changed the default MAC address to something more realistic.
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62 /* Standard includes. */
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66 /* Scheduler include files. */
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67 #include "FreeRTOS.h"
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73 /* Application includes. */
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75 #include "html_pages.h"
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77 /*-----------------------------------------------------------*/
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79 /* Hardwired i2c address of the WIZNet device. */
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80 #define tcpDEVICE_ADDRESS ( ( unsigned portCHAR ) 0x00 )
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82 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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84 #define tcp8K_RX ( ( unsigned portCHAR ) 0x03 )
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85 #define tcp8K_TX ( ( unsigned portCHAR ) 0x03 )
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87 /* Constants used to generate the WIZnet internal buffer addresses. */
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88 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned portLONG ) 0x1fff )
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89 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned portLONG ) 0x4000 )
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91 /* Bit definitions of the commands that can be sent to the command register. */
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92 #define tcpRESET_CMD ( ( unsigned portCHAR ) 0x80 )
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93 #define tcpSYS_INIT_CMD ( ( unsigned portCHAR ) 0x01 )
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94 #define tcpSOCK_STREAM ( ( unsigned portCHAR ) 0x01 )
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95 #define tcpSOCK_INIT ( ( unsigned portCHAR ) 0x02 )
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96 #define tcpLISTEN_CMD ( ( unsigned portCHAR ) 0x08 )
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97 #define tcpRECEIVE_CMD ( ( unsigned portCHAR ) 0x40 )
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98 #define tcpDISCONNECT_CMD ( ( unsigned portCHAR ) 0x10 )
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99 #define tcpSEND_CMD ( ( unsigned portCHAR ) 0x20 )
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101 /* Constants required to handle the interrupts. */
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102 #define tcpCLEAR_EINT0 ( 1 )
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103 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned portCHAR ) 0xff )
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104 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned portCHAR ) 0x01 )
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105 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned portCHAR ) 0x00 )
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106 #define tcpWAKE_ON_EINT0 ( 1 )
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107 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned portLONG ) 0x01 )
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108 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x4000 )
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109 #define tcpEINT0_VIC_CHANNEL ( ( unsigned portLONG ) 14 )
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110 #define tcpEINT0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
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112 /* Various delays used in the driver. */
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113 #define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )
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114 #define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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115 #define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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116 #define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS )
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117 #define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS )
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118 #define tcpNO_DELAY ( ( portTickType ) 0 )
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120 /* Length of the data to read for various register reads. */
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121 #define tcpSTATUS_READ_LEN ( ( unsigned portLONG ) 1 )
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122 #define tcpSHADOW_READ_LEN ( ( unsigned portLONG ) 1 )
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124 /* Register addresses within the WIZnet device. */
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125 #define tcpCOMMAND_REG ( ( unsigned portSHORT ) 0x0000 )
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126 #define tcpGATEWAY_ADDR_REG ( ( unsigned portSHORT ) 0x0080 )
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127 #define tcpSUBNET_MASK_REG ( ( unsigned portSHORT ) 0x0084 )
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128 #define tcpSOURCE_HA_REG ( ( unsigned portSHORT ) 0x0088 )
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129 #define tpcSOURCE_IP_REG ( ( unsigned portSHORT ) 0x008E )
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130 #define tpcSOCKET_OPT_REG ( ( unsigned portSHORT ) 0x00A1 )
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131 #define tcpSOURCE_PORT_REG ( ( unsigned portSHORT ) 0x00AE )
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132 #define tcpTX_WRITE_POINTER_REG ( ( unsigned portSHORT ) 0x0040 )
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133 #define tcpTX_READ_POINTER_REG ( ( unsigned portSHORT ) 0x0044 )
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134 #define tcpTX_ACK_POINTER_REG ( ( unsigned portSHORT ) 0x0018 )
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135 #define tcpTX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0096 )
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136 #define tcpRX_MEM_SIZE_REG ( ( unsigned portSHORT ) 0x0095 )
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137 #define tcpINTERRUPT_STATUS_REG ( ( unsigned portSHORT ) 0x0004 )
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138 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned portSHORT ) 0x01F0 )
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139 #define tcpTX_ACK_SHADOW_REG ( ( unsigned portSHORT ) 0x01E2 )
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140 #define tcpISR_MASK_REG ( ( unsigned portSHORT ) 0x0009 )
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141 #define tcpINTERRUPT_REG ( ( unsigned portSHORT ) 0x0008 )
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142 #define tcpSOCKET_STATE_REG ( ( unsigned portSHORT ) 0x00a0 )
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144 /* Constants required for hardware setup. */
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145 #define tcpRESET_ACTIVE_LOW ( ( unsigned portLONG ) 0x20 )
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146 #define tcpRESET_ACTIVE_HIGH ( ( unsigned portLONG ) 0x10 )
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148 /* Constants defining the source of the WIZnet ISR. */
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149 #define tcpISR_SYS_INIT ( ( unsigned portCHAR ) 0x01 )
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150 #define tcpISR_SOCKET_INIT ( ( unsigned portCHAR ) 0x02 )
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151 #define tcpISR_ESTABLISHED ( ( unsigned portCHAR ) 0x04 )
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152 #define tcpISR_CLOSED ( ( unsigned portCHAR ) 0x08 )
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153 #define tcpISR_TIMEOUT ( ( unsigned portCHAR ) 0x10 )
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154 #define tcpISR_TX_COMPLETE ( ( unsigned portCHAR ) 0x20 )
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155 #define tcpISR_RX_COMPLETE ( ( unsigned portCHAR ) 0x40 )
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157 /* Constants defining the socket status bits. */
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158 #define tcpSTATUS_ESTABLISHED ( ( unsigned portCHAR ) 0x06 )
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159 #define tcpSTATUS_LISTEN ( ( unsigned portCHAR ) 0x02 )
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161 /* Misc constants. */
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162 #define tcpNO_STATUS_BITS ( ( unsigned portCHAR ) 0x00 )
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163 #define i2cNO_ADDR_REQUIRED ( ( unsigned portSHORT ) 0x0000 )
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164 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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165 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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166 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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167 #define tcpBUFFER_LEN ( 4 * 1024 )
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168 #define tcpMAX_REGISTER_LEN ( 4 )
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169 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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170 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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172 /* Message definitions. The IP address, MAC address, gateway address, etc.
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174 const unsigned portCHAR const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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175 const unsigned portCHAR const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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176 const unsigned portCHAR const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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177 const unsigned portCHAR const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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179 /* Other fixed messages. */
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180 const unsigned portCHAR const ucDataReset[] = { tcpRESET_CMD };
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181 const unsigned portCHAR const ucDataInit[] = { tcpSYS_INIT_CMD };
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182 const unsigned portCHAR const ucDataProtocol[] = { tcpSOCK_STREAM };
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183 const unsigned portCHAR const ucDataPort[] = { 0xBA, 0xCC };
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184 const unsigned portCHAR const ucDataSockInit[] = { tcpSOCK_INIT };
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185 const unsigned portCHAR const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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186 const unsigned portCHAR const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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187 const unsigned portCHAR const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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188 const unsigned portCHAR const ucDataListen[] = { tcpLISTEN_CMD };
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189 const unsigned portCHAR const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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190 const unsigned portCHAR const ucDataSetTxBufSize[] = { tcp8K_TX };
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191 const unsigned portCHAR const ucDataSetRxBufSize[] = { tcp8K_RX };
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192 const unsigned portCHAR const ucDataSend[] = { tcpSEND_CMD };
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193 const unsigned portCHAR const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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194 const unsigned portCHAR const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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195 const unsigned portCHAR const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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196 const unsigned portCHAR const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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198 static xSemaphoreHandle xMessageComplete = NULL;
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199 xQueueHandle xTCPISRQueue = NULL;
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201 /* Dynamically generate and send an html page. */
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202 static void prvSendSamplePage( void );
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204 /* Read a register from the WIZnet device via the i2c interface. */
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205 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength );
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207 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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208 static void prvFlushBuffer( unsigned portLONG ulTxAddress );
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210 /* Write a string to the WIZnet Tx buffer. */
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211 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress );
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213 /* Convert a number to a string. */
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214 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore );
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216 /*-----------------------------------------------------------*/
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218 void ultoa( unsigned portLONG ulVal, portCHAR *pcBuffer, portLONG lIgnore )
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220 unsigned portLONG lNibble;
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223 /* Simple routine to convert an unsigned long value into a string in hex
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226 /* For each nibble in the number we are converting. */
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227 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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229 /* Take the top four bits of the number. */
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230 lNibble = ( ulVal >> 28 );
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232 /* We are converting it to a hex string, so is the number in the range
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236 pcBuffer[ lIndex ] = '0' + lNibble;
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241 pcBuffer[ lIndex ] = 'A' + lNibble;
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244 /* Shift off the top nibble so we use the next nibble next time around. */
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248 /* Mark the end of the string with a null terminator. */
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249 pcBuffer[ lIndex ] = 0x00;
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251 /*-----------------------------------------------------------*/
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253 static void prvReadRegister( unsigned portCHAR *pucDestination, unsigned portSHORT usAddress, unsigned portLONG ulLength )
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255 unsigned portCHAR ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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257 /* Read a register value from the WIZnet device. */
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259 /* First write out the address of the register we want to read. */
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260 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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262 /* Then read back from that address. */
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263 i2cMessage( ( unsigned portCHAR * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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265 /* I2C messages are queued so use the semaphore to wait for the read to
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266 complete - otherwise we will leave this function before the I2C
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267 transactions have completed. */
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268 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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270 /*-----------------------------------------------------------*/
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272 void vTCPHardReset( void )
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274 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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275 WIZnet reset lines active for a few milliseconds. */
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277 /* Make sure the interrupt from the WIZnet is disabled. */
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278 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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280 /* If xMessageComplete is NULL then this is the first time that this
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281 function has been called and the queue and semaphore used in this file
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282 have not yet been created. */
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283 if( xMessageComplete == NULL )
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285 /* Create and obtain the semaphore used when we want to wait for an i2c
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286 message to be completed. */
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287 vSemaphoreCreateBinary( xMessageComplete );
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288 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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290 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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291 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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294 /* Use the GPIO to reset the network hardware. */
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295 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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296 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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298 /* Delay with the network hardware in reset for a short while. */
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299 vTaskDelay( tcpRESET_DELAY );
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301 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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302 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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304 vTaskDelay( tcpINIT_DELAY );
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306 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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307 First enable the EINT0 function of the pin. */
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308 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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310 /* We want the TCP comms to wake us from power save. */
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311 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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313 /* Install the ISR into the VIC - but don't enable it yet! */
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314 portENTER_CRITICAL();
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316 extern void ( vEINT0_ISR_Wrapper )( void );
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318 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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319 VICVectAddr3 = ( portLONG ) vEINT0_ISR_Wrapper;
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321 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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323 portEXIT_CRITICAL();
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325 /* Enable interrupts in the WIZnet itself. */
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326 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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328 vTaskDelay( tcpLONG_DELAY );
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330 /*-----------------------------------------------------------*/
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332 portLONG lTCPSoftReset( void )
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334 unsigned portCHAR ucStatus;
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335 extern volatile portLONG lTransactionCompleted;
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337 /* Send a message to the WIZnet device to tell it set all it's registers
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338 back to their default states. Then setup the WIZnet device as required. */
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340 /* Reset the internal WIZnet registers. */
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341 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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343 /* Now we can configure the protocol. Here the MAC address, gateway
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344 address, subnet mask and IP address are configured. */
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345 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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346 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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347 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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348 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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350 /* Next the memory buffers are configured to give all the WIZnet internal
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351 memory over to a single socket. This gives the socket the maximum internal
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352 Tx and Rx buffer space. */
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353 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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354 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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356 /* Send the sys init command so the above parameters take effect. */
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357 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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359 /* Seems to like a little wait here. */
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360 vTaskDelay( tcpINIT_DELAY );
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362 /* Read back the status to ensure the system initialised ok. */
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363 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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365 /* We should find that the sys init was successful. */
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366 if( ucStatus != tcpISR_SYS_INIT )
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368 return ( portLONG ) pdFAIL;
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371 /* No i2c errors yet. */
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372 portENTER_CRITICAL();
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373 lTransactionCompleted = pdTRUE;
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374 portEXIT_CRITICAL();
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376 return ( portLONG ) pdPASS;
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378 /*-----------------------------------------------------------*/
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380 portLONG lTCPCreateSocket( void )
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382 unsigned portCHAR ucStatus;
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384 /* Create and configure a socket. */
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386 /* Setup and init the socket. Here the port number is set and the socket
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388 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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389 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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390 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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392 /* Wait for the Init command to be sent. */
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393 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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395 /* For some reason the message was not transmitted within our block
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397 return ( portLONG ) pdFAIL;
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400 /* Allow the socket to initialise. */
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401 vTaskDelay( tcpINIT_DELAY );
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403 /* Read back the status to ensure the socket initialised ok. */
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404 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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406 /* We should find that the socket init was successful. */
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407 if( ucStatus != tcpISR_SOCKET_INIT )
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409 return ( portLONG ) pdFAIL;
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413 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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414 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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415 vTaskDelay( tcpSHORT_DELAY );
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416 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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417 vTaskDelay( tcpSHORT_DELAY );
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418 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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419 vTaskDelay( tcpSHORT_DELAY );
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421 return ( portLONG ) pdPASS;
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423 /*-----------------------------------------------------------*/
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425 void vTCPListen( void )
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427 unsigned portCHAR ucISR;
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429 /* Start a passive listen on the socket. */
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431 /* Enable interrupts in the WizNet device after ensuring none are
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432 currently pending. */
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433 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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435 /* The WIZnet device is still asserting and interrupt so tell it to
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437 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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438 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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441 SCB_EXTINT = tcpCLEAR_EINT0;
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444 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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446 /* Just clearing the queue used by the ISR routine to tell this task
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447 that the WIZnet device needs attention. */
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450 /* Now all the pending interrupts have been cleared we can enable the
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451 processor interrupts. */
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452 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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454 /* Then start listening for incoming connections. */
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455 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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457 /*-----------------------------------------------------------*/
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459 portLONG lProcessConnection( void )
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461 unsigned portCHAR ucISR, ucState, ucLastState = 2, ucShadow;
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462 extern volatile portLONG lTransactionCompleted;
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463 portLONG lSameStateCount = 0, lDataSent = pdFALSE;
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464 unsigned portLONG ulWritePointer, ulAckPointer;
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466 /* No I2C errors can yet have occurred. */
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467 portENTER_CRITICAL();
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468 lTransactionCompleted = pdTRUE;
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469 portEXIT_CRITICAL();
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471 /* Keep looping - processing interrupts, until we have completed a
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472 transaction. This uses the WIZnet in it's simplest form. The socket
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473 accepts a connection - we process the connection - then close the socket.
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474 We then go back to reinitialise everything and start again. */
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475 while( lTransactionCompleted == pdTRUE )
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477 /* Wait for a message on the queue from the WIZnet ISR. When the
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478 WIZnet device asserts an interrupt the ISR simply posts a message
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479 onto this queue to wake this task. */
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480 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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482 /* The ISR posted a message on this queue to tell us that the
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483 WIZnet device asserted an interrupt. The ISR cannot process
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484 an I2C message so cannot tell us what caused the interrupt so
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485 we have to query the device here. This task is the highest
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486 priority in the system so will run immediately following the ISR. */
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487 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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489 /* Once we have read what caused the ISR we can clear the interrupt
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491 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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493 /* Now we can clear the processor interrupt and re-enable ready for
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495 SCB_EXTINT = tcpCLEAR_EINT0;
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496 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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498 /* Process the interrupt ... */
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500 if( ucISR & tcpISR_ESTABLISHED )
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502 /* A connection has been established - respond by sending
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503 a receive command. */
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504 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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507 if( ucISR & tcpISR_RX_COMPLETE )
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509 /* We message has been received. This will be an HTTP get
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510 command. We only have one page to send so just send it without
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511 regard to what the actual requested page was. */
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512 prvSendSamplePage();
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515 if( ucISR & tcpISR_TX_COMPLETE )
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517 /* We have a TX complete interrupt - which oddly does not
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518 indicate that the message being sent is complete so we cannot
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519 yet close the socket. Instead we read the position of the Tx
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520 pointer within the WIZnet device so we know how much data it
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521 has to send. Later we will read the ack pointer and compare
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522 this to the Tx pointer to ascertain whether the transmission
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525 /* First read the shadow register. */
\r
526 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
528 /* Now a short delay is required. */
\r
529 vTaskDelay( tcpSHORT_DELAY );
\r
531 /* Then we can read the real register. */
\r
532 prvReadRegister( ( unsigned portCHAR * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
\r
534 /* We cannot do anything more here but need to remember that
\r
535 this interrupt has occurred. */
\r
536 lDataSent = pdTRUE;
\r
539 if( ucISR & tcpISR_CLOSED )
\r
541 /* The socket has been closed so we can leave this function. */
\r
542 lTransactionCompleted = pdFALSE;
\r
547 /* We have not received an interrupt from the WIZnet device for a
\r
548 while. Read the socket status and check that everything is as
\r
550 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
552 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
554 /* The socket is established and we have already received a Tx
\r
555 end interrupt. We must therefore be waiting for the Tx buffer
\r
556 inside the WIZnet device to be empty before we can close the
\r
559 Read the Ack pointer register to see if it has caught up with
\r
560 the Tx pointer register. First we have to read the shadow
\r
562 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
563 vTaskDelay( tcpSHORT_DELAY );
\r
564 prvReadRegister( ( unsigned portCHAR * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
566 if( ulAckPointer == ulWritePointer )
\r
568 /* The Ack and write pointer are now equal and we can
\r
569 safely close the socket. */
\r
570 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
574 /* Keep a count of how many times we encounter the Tx
\r
575 buffer still containing data. */
\r
577 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
579 /* Assume we cannot complete sending the data and
\r
580 therefore cannot safely close the socket. Start over. */
\r
582 lTransactionCompleted = pdFALSE;
\r
586 else if( ucState != tcpSTATUS_LISTEN )
\r
588 /* If we have not yet received a Tx end interrupt we would only
\r
589 ever expect to find the socket still listening for any
\r
590 sustained period. */
\r
591 if( ucState == ucLastState )
\r
594 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
596 /* We are persistently in an unexpected state. Assume
\r
597 we cannot safely close the socket and start over. */
\r
599 lTransactionCompleted = pdFALSE;
\r
605 /* We are in the listen state so are happy that everything
\r
607 lSameStateCount = 0;
\r
610 /* Remember what state we are in this time around so we can check
\r
611 for a persistence on an unexpected state. */
\r
612 ucLastState = ucState;
\r
616 /* We are going to reinitialise the WIZnet device so do not want our
\r
617 interrupts from the WIZnet to be processed. */
\r
618 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
619 return lTransactionCompleted;
\r
621 /*-----------------------------------------------------------*/
\r
623 static void prvWriteString( const portCHAR * const pucTxBuffer, portLONG lTxLen, unsigned portLONG *pulTxAddress )
\r
625 unsigned portLONG ulSendAddress;
\r
627 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
629 /* Calculate the address to which we are going to write in the buffer. */
\r
630 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
632 /* Send the buffer to the calculated address. Use the semaphore so we
\r
633 can wait until the entire message has been transferred. */
\r
634 i2cMessage( ( unsigned portCHAR * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned portSHORT ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
636 /* Wait until the semaphore indicates that the message has been transferred. */
\r
637 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
642 /* Return the new address of the end of the buffer (within the WIZnet
\r
644 *pulTxAddress += ( unsigned portLONG ) lTxLen;
\r
646 /*-----------------------------------------------------------*/
\r
648 static void prvFlushBuffer( unsigned portLONG ulTxAddress )
\r
650 unsigned portCHAR ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
652 /* We have written some data to the Tx buffer internal to the WIZnet
\r
653 device. Now we update the Tx pointer inside the WIZnet then send a
\r
654 Send command - which causes the data up to the new Tx pointer to be
\r
657 /* Make sure endieness is correct for transmission. */
\r
658 ulTxAddress = htonl( ulTxAddress );
\r
660 /* Place the new Tx pointer in the string to be transmitted. */
\r
661 ucTxBuffer[ 0 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
663 ucTxBuffer[ 1 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
665 ucTxBuffer[ 2 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
667 ucTxBuffer[ 3 ] = ( unsigned portCHAR ) ( ulTxAddress & 0xff );
\r
670 /* And send it to the WIZnet device. */
\r
671 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
673 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
678 vTaskDelay( tcpSHORT_DELAY );
\r
681 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
683 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
688 /*-----------------------------------------------------------*/
\r
690 static void prvSendSamplePage( void )
\r
692 extern portLONG lErrorInTask;
\r
693 unsigned portLONG ulTxAddress;
\r
694 unsigned portCHAR ucShadow;
\r
696 static unsigned portLONG ulRefreshCount = 0x00;
\r
697 static portCHAR cPageBuffer[ tcpBUFFER_LEN ];
\r
700 /* This function just generates a sample page of HTML which gets
\r
701 sent each time a client attaches to the socket. The page is created
\r
702 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
703 with a bit of dynamically generated data in the middle. */
\r
705 /* We need to know the address to which the html string should be sent
\r
706 in the WIZnet Tx buffer. First read the shadow register. */
\r
707 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
709 /* Now a short delay is required. */
\r
710 vTaskDelay( tcpSHORT_DELAY );
\r
712 /* Now we can read the real pointer value. */
\r
713 prvReadRegister( ( unsigned portCHAR * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
715 /* Make sure endieness is correct. */
\r
716 ulTxAddress = htonl( ulTxAddress );
\r
718 /* Send the start of the page. */
\r
719 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
721 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
723 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
724 lIndex = strlen( cPageBuffer );
\r
725 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
726 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
727 lIndex = strlen( cPageBuffer );
\r
728 ultoa( ( unsigned portLONG ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
729 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
730 lIndex = strlen( cPageBuffer );
\r
731 ultoa( ( unsigned portLONG ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
732 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
733 lIndex = strlen( cPageBuffer );
\r
734 ultoa( ( unsigned portLONG ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
738 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
742 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
747 /* Send the dynamically generated string. */
\r
748 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
750 /* Finish the page. */
\r
751 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
753 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
754 prvFlushBuffer( ulTxAddress );
\r