2 FreeRTOS V5.4.0 - Copyright (C) 2003-2009 Richard Barry.
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4 This file is part of the FreeRTOS distribution.
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6 FreeRTOS is free software; you can redistribute it and/or modify it under
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7 the terms of the GNU General Public License (version 2) as published by the
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8 Free Software Foundation and modified by the FreeRTOS exception.
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9 **NOTE** The exception to the GPL is included to allow you to distribute a
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10 combined work that includes FreeRTOS without being obliged to provide the
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11 source code for proprietary components outside of the FreeRTOS kernel.
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12 Alternative commercial license and support terms are also available upon
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13 request. See the licensing section of http://www.FreeRTOS.org for full
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16 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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21 You should have received a copy of the GNU General Public License along
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22 with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
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23 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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26 ***************************************************************************
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28 * Looking for a quick start? Then check out the FreeRTOS eBook! *
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29 * See http://www.FreeRTOS.org/Documentation for details *
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31 ***************************************************************************
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35 Please ensure to read the configuration and relevant port sections of the
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36 online documentation.
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38 http://www.FreeRTOS.org - Documentation, latest information, license and
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41 http://www.SafeRTOS.com - A version that is certified for use in safety
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44 http://www.OpenRTOS.com - Commercial support, development, porting,
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45 licensing and training services.
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49 /* Standard includes. */
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52 /* Scheduler include files. */
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53 #include "FreeRTOS.h"
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57 /* Application includes. */
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60 /*-----------------------------------------------------------*/
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62 /* Constants to setup the microcontroller IO. */
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63 #define mainSDA_ENABLE ( ( unsigned portLONG ) 0x0040 )
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64 #define mainSCL_ENABLE ( ( unsigned portLONG ) 0x0010 )
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66 /* Bit definitions within the I2CONCLR register. */
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67 #define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 )
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68 #define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 )
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69 #define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 )
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71 /* Constants required to setup the VIC. */
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72 #define i2cI2C_VIC_CHANNEL ( ( unsigned portLONG ) 0x0009 )
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73 #define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0200 )
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74 #define i2cI2C_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
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76 /* Misc constants. */
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77 #define i2cNO_BLOCK ( ( portTickType ) 0 )
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78 #define i2cQUEUE_LENGTH ( ( unsigned portCHAR ) 5 )
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79 #define i2cEXTRA_MESSAGES ( ( unsigned portCHAR ) 2 )
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80 #define i2cREAD_TX_LEN ( ( unsigned portLONG ) 2 )
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81 #define i2cACTIVE_MASTER_MODE ( ( unsigned portCHAR ) 0x40 )
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82 #define i2cTIMERL ( 200 )
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83 #define i2cTIMERH ( 200 )
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85 /* Array of message definitions. See the header file for more information
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86 on the structure members. There are two more places in the queue than as
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87 defined by i2cQUEUE_LENGTH. This is to ensure that there is always a free
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88 message available - one can be in the process of being transmitted and one
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89 can be left free. */
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90 static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ];
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92 /* Function in the ARM part of the code used to create the queues. */
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93 extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree );
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95 /* Index to the next free message in the xTxMessages array. */
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96 unsigned portLONG ulNextFreeMessage = ( unsigned portLONG ) 0;
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98 /* Queue of messages that are waiting transmission. */
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99 static xQueueHandle xMessagesForTx;
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101 /* Flag to indicate the state of the I2C ISR state machine. */
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102 static unsigned portLONG *pulBusFree;
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104 /*-----------------------------------------------------------*/
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105 void i2cMessage( const unsigned portCHAR * const pucMessage, portLONG lMessageLength, unsigned portCHAR ucSlaveAddress, unsigned portSHORT usBufferAddress, unsigned portLONG ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime )
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107 extern volatile xI2CMessage *pxCurrentMessage;
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108 xI2CMessage *pxNextFreeMessage;
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109 signed portBASE_TYPE xReturn;
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111 portENTER_CRITICAL();
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113 /* This message is guaranteed to be free as there are two more messages
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114 than spaces in the queue allowing for one message to be in process of
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115 being transmitted and one to be left free. */
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116 pxNextFreeMessage = &( xTxMessages[ ulNextFreeMessage ] );
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118 /* Fill the message with the data to be sent. */
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120 /* Pointer to the actual data. Only a pointer is stored (i.e. the
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121 actual data is not copied, so the data being pointed to must still
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122 be valid when the message eventually gets sent (it may be queued for
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124 pxNextFreeMessage->pucBuffer = ( unsigned portCHAR * ) pucMessage;
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126 /* This is the address of the I2C device we are going to transmit this
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128 pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned portCHAR ) ulDirection;
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130 /* A semaphore can be used to allow the I2C ISR to indicate that the
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131 message has been sent. This can be NULL if you don't want to wait for
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132 the message transmission to complete. */
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133 pxNextFreeMessage->xMessageCompleteSemaphore = xMessageCompleteSemaphore;
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135 /* How many bytes are to be sent? */
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136 pxNextFreeMessage->lMessageLength = lMessageLength;
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138 /* The address within the WIZnet device to which the data will be
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139 written. This could be the address of a register, or alternatively
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140 a location within the WIZnet Tx buffer. */
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141 pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff );
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143 /* Second byte of the address. */
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144 usBufferAddress >>= 8;
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145 pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned portCHAR ) ( usBufferAddress & 0xff );
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147 /* Increment to the next message in the array - with a wrap around check. */
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148 ulNextFreeMessage++;
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149 if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) )
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151 ulNextFreeMessage = ( unsigned portLONG ) 0;
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154 /* Is the I2C interrupt in the middle of transmitting a message? */
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155 if( *pulBusFree == ( unsigned portLONG ) pdTRUE )
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157 /* No message is currently being sent or queued to be sent. We
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158 can start the ISR sending this message immediately. */
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159 pxCurrentMessage = pxNextFreeMessage;
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161 I2C_I2CONCLR = i2cSI_BIT;
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162 I2C_I2CONSET = i2cSTA_BIT;
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164 *pulBusFree = ( unsigned portLONG ) pdFALSE;
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168 /* The I2C interrupt routine is mid sending a message. Queue
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169 this message ready to be sent. */
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170 xReturn = xQueueSend( xMessagesForTx, &pxNextFreeMessage, xBlockTime );
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172 /* We may have blocked while trying to queue the message. If this
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173 was the case then the interrupt would have been enabled and we may
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174 now find that the I2C interrupt routine is no longer sending a
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176 if( ( *pulBusFree == ( unsigned portLONG ) pdTRUE ) && ( xReturn == pdPASS ) )
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178 /* Get the next message in the queue (this should be the
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179 message we just posted) and start off the transmission
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181 xQueueReceive( xMessagesForTx, &pxNextFreeMessage, i2cNO_BLOCK );
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182 pxCurrentMessage = pxNextFreeMessage;
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184 I2C_I2CONCLR = i2cSI_BIT;
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185 I2C_I2CONSET = i2cSTA_BIT;
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187 *pulBusFree = ( unsigned portLONG ) pdFALSE;
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191 portEXIT_CRITICAL();
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193 /*-----------------------------------------------------------*/
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195 void i2cInit( void )
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197 extern void ( vI2C_ISR_Wrapper )( void );
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199 /* Create the queue used to send messages to the ISR. */
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200 vI2CISRCreateQueues( i2cQUEUE_LENGTH, &xMessagesForTx, &pulBusFree );
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202 /* Configure the I2C hardware. */
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204 I2C_I2CONCLR = 0xff;
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206 PCB_PINSEL0 |= mainSDA_ENABLE;
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207 PCB_PINSEL0 |= mainSCL_ENABLE;
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209 I2C_I2SCLL = i2cTIMERL;
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210 I2C_I2SCLH = i2cTIMERH;
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211 I2C_I2CONSET = i2cACTIVE_MASTER_MODE;
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213 portENTER_CRITICAL();
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215 /* Setup the VIC for the i2c interrupt. */
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216 VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT );
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217 VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT;
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218 VICVectAddr2 = ( portLONG ) vI2C_ISR_Wrapper;
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220 VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE;
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222 portEXIT_CRITICAL();
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