2 FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd.
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4 This file is part of the FreeRTOS distribution.
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6 FreeRTOS is free software; you can redistribute it and/or modify it under
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7 the terms of the GNU General Public License (version 2) as published by the
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8 Free Software Foundation and modified by the FreeRTOS exception.
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9 **NOTE** The exception to the GPL is included to allow you to distribute a
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10 combined work that includes FreeRTOS without being obliged to provide the
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11 source code for proprietary components outside of the FreeRTOS kernel.
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12 Alternative commercial license and support terms are also available upon
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13 request. See the licensing section of http://www.FreeRTOS.org for full
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16 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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21 You should have received a copy of the GNU General Public License along
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22 with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
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23 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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26 ***************************************************************************
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28 * The FreeRTOS eBook and reference manual are available to purchase for a *
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29 * small fee. Help yourself get started quickly while also helping the *
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30 * FreeRTOS project! See http://www.FreeRTOS.org/Documentation for details *
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32 ***************************************************************************
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36 Please ensure to read the configuration and relevant port sections of the
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37 online documentation.
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39 http://www.FreeRTOS.org - Documentation, latest information, license and
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42 http://www.SafeRTOS.com - A version that is certified for use in safety
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45 http://www.OpenRTOS.com - Commercial support, development, porting,
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46 licensing and training services.
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50 /* Standard includes. */
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53 /* Scheduler include files. */
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54 #include "FreeRTOS.h"
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58 /* Application includes. */
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61 /*-----------------------------------------------------------*/
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63 /* Constants to setup the microcontroller IO. */
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64 #define mainSDA_ENABLE ( ( unsigned long ) 0x0040 )
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65 #define mainSCL_ENABLE ( ( unsigned long ) 0x0010 )
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67 /* Bit definitions within the I2CONCLR register. */
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68 #define i2cSTA_BIT ( ( unsigned char ) 0x20 )
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69 #define i2cSI_BIT ( ( unsigned char ) 0x08 )
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70 #define i2cSTO_BIT ( ( unsigned char ) 0x10 )
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72 /* Constants required to setup the VIC. */
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73 #define i2cI2C_VIC_CHANNEL ( ( unsigned long ) 0x0009 )
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74 #define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0200 )
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75 #define i2cI2C_VIC_ENABLE ( ( unsigned long ) 0x0020 )
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77 /* Misc constants. */
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78 #define i2cNO_BLOCK ( ( portTickType ) 0 )
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79 #define i2cQUEUE_LENGTH ( ( unsigned char ) 5 )
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80 #define i2cEXTRA_MESSAGES ( ( unsigned char ) 2 )
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81 #define i2cREAD_TX_LEN ( ( unsigned long ) 2 )
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82 #define i2cACTIVE_MASTER_MODE ( ( unsigned char ) 0x40 )
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83 #define i2cTIMERL ( 200 )
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84 #define i2cTIMERH ( 200 )
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86 /* Array of message definitions. See the header file for more information
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87 on the structure members. There are two more places in the queue than as
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88 defined by i2cQUEUE_LENGTH. This is to ensure that there is always a free
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89 message available - one can be in the process of being transmitted and one
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90 can be left free. */
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91 static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ];
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93 /* Function in the ARM part of the code used to create the queues. */
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94 extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned long **ppulBusFree );
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96 /* Index to the next free message in the xTxMessages array. */
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97 unsigned long ulNextFreeMessage = ( unsigned long ) 0;
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99 /* Queue of messages that are waiting transmission. */
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100 static xQueueHandle xMessagesForTx;
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102 /* Flag to indicate the state of the I2C ISR state machine. */
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103 static unsigned long *pulBusFree;
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105 /*-----------------------------------------------------------*/
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106 void i2cMessage( const unsigned char * const pucMessage, long lMessageLength, unsigned char ucSlaveAddress, unsigned short usBufferAddress, unsigned long ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime )
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108 extern volatile xI2CMessage *pxCurrentMessage;
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109 xI2CMessage *pxNextFreeMessage;
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110 signed portBASE_TYPE xReturn;
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112 portENTER_CRITICAL();
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114 /* This message is guaranteed to be free as there are two more messages
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115 than spaces in the queue allowing for one message to be in process of
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116 being transmitted and one to be left free. */
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117 pxNextFreeMessage = &( xTxMessages[ ulNextFreeMessage ] );
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119 /* Fill the message with the data to be sent. */
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121 /* Pointer to the actual data. Only a pointer is stored (i.e. the
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122 actual data is not copied, so the data being pointed to must still
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123 be valid when the message eventually gets sent (it may be queued for
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125 pxNextFreeMessage->pucBuffer = ( unsigned char * ) pucMessage;
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127 /* This is the address of the I2C device we are going to transmit this
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129 pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned char ) ulDirection;
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131 /* A semaphore can be used to allow the I2C ISR to indicate that the
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132 message has been sent. This can be NULL if you don't want to wait for
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133 the message transmission to complete. */
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134 pxNextFreeMessage->xMessageCompleteSemaphore = xMessageCompleteSemaphore;
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136 /* How many bytes are to be sent? */
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137 pxNextFreeMessage->lMessageLength = lMessageLength;
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139 /* The address within the WIZnet device to which the data will be
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140 written. This could be the address of a register, or alternatively
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141 a location within the WIZnet Tx buffer. */
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142 pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned char ) ( usBufferAddress & 0xff );
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144 /* Second byte of the address. */
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145 usBufferAddress >>= 8;
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146 pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned char ) ( usBufferAddress & 0xff );
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148 /* Increment to the next message in the array - with a wrap around check. */
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149 ulNextFreeMessage++;
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150 if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) )
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152 ulNextFreeMessage = ( unsigned long ) 0;
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155 /* Is the I2C interrupt in the middle of transmitting a message? */
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156 if( *pulBusFree == ( unsigned long ) pdTRUE )
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158 /* No message is currently being sent or queued to be sent. We
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159 can start the ISR sending this message immediately. */
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160 pxCurrentMessage = pxNextFreeMessage;
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162 I2C_I2CONCLR = i2cSI_BIT;
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163 I2C_I2CONSET = i2cSTA_BIT;
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165 *pulBusFree = ( unsigned long ) pdFALSE;
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169 /* The I2C interrupt routine is mid sending a message. Queue
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170 this message ready to be sent. */
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171 xReturn = xQueueSend( xMessagesForTx, &pxNextFreeMessage, xBlockTime );
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173 /* We may have blocked while trying to queue the message. If this
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174 was the case then the interrupt would have been enabled and we may
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175 now find that the I2C interrupt routine is no longer sending a
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177 if( ( *pulBusFree == ( unsigned long ) pdTRUE ) && ( xReturn == pdPASS ) )
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179 /* Get the next message in the queue (this should be the
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180 message we just posted) and start off the transmission
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182 xQueueReceive( xMessagesForTx, &pxNextFreeMessage, i2cNO_BLOCK );
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183 pxCurrentMessage = pxNextFreeMessage;
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185 I2C_I2CONCLR = i2cSI_BIT;
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186 I2C_I2CONSET = i2cSTA_BIT;
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188 *pulBusFree = ( unsigned long ) pdFALSE;
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192 portEXIT_CRITICAL();
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194 /*-----------------------------------------------------------*/
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196 void i2cInit( void )
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198 extern void ( vI2C_ISR_Wrapper )( void );
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200 /* Create the queue used to send messages to the ISR. */
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201 vI2CISRCreateQueues( i2cQUEUE_LENGTH, &xMessagesForTx, &pulBusFree );
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203 /* Configure the I2C hardware. */
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205 I2C_I2CONCLR = 0xff;
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207 PCB_PINSEL0 |= mainSDA_ENABLE;
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208 PCB_PINSEL0 |= mainSCL_ENABLE;
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210 I2C_I2SCLL = i2cTIMERL;
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211 I2C_I2SCLH = i2cTIMERH;
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212 I2C_I2CONSET = i2cACTIVE_MASTER_MODE;
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214 portENTER_CRITICAL();
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216 /* Setup the VIC for the i2c interrupt. */
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217 VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT );
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218 VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT;
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219 VICVectAddr2 = ( long ) vI2C_ISR_Wrapper;
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221 VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE;
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223 portEXIT_CRITICAL();
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