2 FreeRTOS.org V4.0.4 - copyright (C) 2003-2006 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 See http://www.FreeRTOS.org for documentation, latest information, license
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28 and contact details. Please ensure to read the configuration and relevant
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29 port sections of the online documentation.
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30 ***************************************************************************
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34 /* Standard includes. */
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37 /* Scheduler include files. */
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38 #include "FreeRTOS.h"
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43 /* Application includes. */
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46 /*-----------------------------------------------------------*/
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48 /* Bit definitions within the I2CONCLR register. */
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49 #define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 )
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50 #define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 )
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51 #define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 )
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52 #define i2cAA_BIT ( ( unsigned portCHAR ) 0x04 )
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54 /* Status codes for the I2STAT register. */
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55 #define i2cSTATUS_START_TXED ( 0x08 )
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56 #define i2cSTATUS_REP_START_TXED ( 0x10 )
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57 #define i2cSTATUS_TX_ADDR_ACKED ( 0x18 )
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58 #define i2cSTATUS_DATA_TXED ( 0x28 )
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59 #define i2cSTATUS_RX_ADDR_ACKED ( 0x40 )
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60 #define i2cSTATUS_DATA_RXED ( 0x50 )
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61 #define i2cSTATUS_LAST_BYTE_RXED ( 0x58 )
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63 /* Constants for operation of the VIC. */
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64 #define i2cCLEAR_VIC_INTERRUPT ( 0 )
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66 /* Misc constants. */
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67 #define i2cJUST_ONE_BYTE_TO_RX ( 1 )
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68 #define i2cBUFFER_ADDRESS_BYTES ( 2 )
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70 /* End the current transmission and free the bus. */
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71 #define i2cEND_TRANSMISSION( lStatus ) \
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73 I2C_I2CONCLR = i2cAA_BIT; \
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74 I2C_I2CONSET = i2cSTO_BIT; \
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75 eCurrentState = eSentStart; \
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76 lTransactionCompleted = lStatus; \
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78 /*-----------------------------------------------------------*/
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80 /* Valid i2c communication states. */
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83 eSentStart, /*<< Last action was the transmission of a start bit. */
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84 eSentAddressForWrite, /*<< Last action was the transmission of the slave address we are to write to. */
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85 eSentAddressForRead, /*<< Last action was the transmission of the slave address we are to read from. */
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86 eSentData, /*<< Last action was the transmission of a data byte. */
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87 eReceiveData /*<< We expected data to be received. */
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89 /*-----------------------------------------------------------*/
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91 /* Points to the message currently being sent. */
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92 volatile xI2CMessage *pxCurrentMessage = NULL;
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94 /* The queue of messages waiting to be transmitted. */
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95 static xQueueHandle xMessagesForTx;
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97 /* Flag used to indicate whether or not the ISR is amid sending a message. */
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98 unsigned portLONG ulBusFree = ( unsigned portLONG ) pdTRUE;
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100 /* Setting this to true will cause the TCP task to think a message is
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101 complete and thus restart. It can therefore be used under error states
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102 to force a restart. */
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103 volatile portLONG lTransactionCompleted = pdTRUE;
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105 /*-----------------------------------------------------------*/
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107 void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree )
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109 /* Create the queues used to hold Rx and Tx characters. */
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110 xMessagesForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( xI2CMessage * ) );
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112 /* Pass back a reference to the queue and bus free flag so the I2C API file
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113 can post messages. */
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114 *pxTxMessages = xMessagesForTx;
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115 *ppulBusFree = &ulBusFree;
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117 /*-----------------------------------------------------------*/
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119 void vI2C_ISR( void ) __attribute__ (( naked ));
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120 void vI2C_ISR( void )
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122 portENTER_SWITCHING_ISR();
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124 /* Holds the current transmission state. */
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125 static I2C_STATE eCurrentState = eSentStart;
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126 static portLONG lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; /* There are two address bytes to send prior to the data. */
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127 portBASE_TYPE xTaskWokenByTx = pdFALSE;
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128 portLONG lBytesLeft;
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130 /* The action taken for this interrupt depends on our current state. */
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131 switch( eCurrentState )
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135 /* We sent a start bit, if it was successful we can
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136 go on to send the slave address. */
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137 if( ( I2C_I2STAT == i2cSTATUS_START_TXED ) || ( I2C_I2STAT == i2cSTATUS_REP_START_TXED ) )
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139 /* Send the slave address. */
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140 I2C_I2DAT = pxCurrentMessage->ucSlaveAddress;
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142 if( pxCurrentMessage->ucSlaveAddress & i2cREAD )
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144 /* We are then going to read bytes back from the
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146 eCurrentState = eSentAddressForRead;
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148 /* Initialise the buffer index so the first byte goes
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149 into the first buffer position. */
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154 /* We are then going to write some data to the slave. */
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155 eCurrentState = eSentAddressForWrite;
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157 /* When writing bytes we first have to send the two
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158 byte buffer address so lMessageIndex is set negative,
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159 when it reaches 0 it is time to send the actual data. */
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160 lMessageIndex = -i2cBUFFER_ADDRESS_BYTES;
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165 /* Could not send the start bit so give up. */
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166 i2cEND_TRANSMISSION( pdFAIL );
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169 I2C_I2CONCLR = i2cSTA_BIT;
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173 case eSentAddressForWrite :
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175 /* We sent the address of the slave we are going to write to.
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176 If this was acknowledged we can go on to send the data. */
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177 if( I2C_I2STAT == i2cSTATUS_TX_ADDR_ACKED )
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179 /* Start the first byte transmitting which is the
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180 first byte of the buffer address to which the data will
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182 I2C_I2DAT = pxCurrentMessage->ucBufferAddressHighByte;
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183 eCurrentState = eSentData;
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187 /* Address was not acknowledged so give up. */
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188 i2cEND_TRANSMISSION( pdFAIL );
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192 case eSentAddressForRead :
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194 /* We sent the address of the slave we are going to read from.
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195 If this was acknowledged we can go on to read the data. */
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196 if( I2C_I2STAT == i2cSTATUS_RX_ADDR_ACKED )
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198 eCurrentState = eReceiveData;
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199 if( pxCurrentMessage->lMessageLength > i2cJUST_ONE_BYTE_TO_RX )
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201 /* Don't ack the last byte of the message. */
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202 I2C_I2CONSET = i2cAA_BIT;
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207 /* Something unexpected happened - give up. */
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208 i2cEND_TRANSMISSION( pdFAIL );
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212 case eReceiveData :
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214 /* We have just received a byte from the slave. */
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215 if( ( I2C_I2STAT == i2cSTATUS_DATA_RXED ) || ( I2C_I2STAT == i2cSTATUS_LAST_BYTE_RXED ) )
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217 /* Buffer the byte just received then increment the index
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218 so it points to the next free space. */
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219 pxCurrentMessage->pucBuffer[ lMessageIndex ] = I2C_I2DAT;
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222 /* How many more bytes are we expecting to receive? */
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223 lBytesLeft = pxCurrentMessage->lMessageLength - lMessageIndex;
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224 if( lBytesLeft == ( unsigned portLONG ) 0 )
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226 /* This was the last byte in the message. */
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227 i2cEND_TRANSMISSION( pdPASS );
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229 /* If xMessageCompleteSemaphore is not null then there
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230 is a task waiting for this message to complete and we
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231 must 'give' the semaphore so the task is woken.*/
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232 if( pxCurrentMessage->xMessageCompleteSemaphore )
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234 xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx );
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237 /* Are there any other messages to transact? */
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238 if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE )
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240 /* Start the next message - which was
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241 retrieved from the queue. */
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242 I2C_I2CONSET = i2cSTA_BIT;
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246 /* No more messages were found to be waiting for
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247 transaction so the bus is free. */
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248 ulBusFree = ( unsigned portLONG ) pdTRUE;
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253 /* There are more bytes to receive but don't ack the
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255 if( lBytesLeft <= i2cJUST_ONE_BYTE_TO_RX )
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257 I2C_I2CONCLR = i2cAA_BIT;
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263 /* Something unexpected happened - give up. */
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264 i2cEND_TRANSMISSION( pdFAIL );
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271 /* We sent a data byte, if successful send the next byte in
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273 if( I2C_I2STAT == i2cSTATUS_DATA_TXED )
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275 /* Index to the next byte to send. */
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277 if( lMessageIndex < 0 )
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279 /* lMessage index is still negative so we have so far
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280 only sent the first byte of the buffer address. Send
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281 the second byte now, then initialise the buffer index
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282 to zero so the next byte sent comes from the actual
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284 I2C_I2DAT = pxCurrentMessage->ucBufferAddressLowByte;
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286 else if( lMessageIndex < pxCurrentMessage->lMessageLength )
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288 /* Simply send the next byte in the tx buffer. */
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289 I2C_I2DAT = pxCurrentMessage->pucBuffer[ lMessageIndex ];
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293 /* No more bytes in this message to be send. Finished
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294 sending message - send a stop bit. */
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295 i2cEND_TRANSMISSION( pdPASS );
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297 /* If xMessageCompleteSemaphore is not null then there
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298 is a task waiting for this message to be sent and the
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299 semaphore must be 'given' to wake the task. */
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300 if( pxCurrentMessage->xMessageCompleteSemaphore )
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302 xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx );
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305 /* Are there any other messages to transact? */
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306 if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE )
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308 /* Start the next message from the Tx queue. */
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309 I2C_I2CONSET = i2cSTA_BIT;
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313 /* No more message were queues for transaction so
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314 the bus is free. */
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315 ulBusFree = ( unsigned portLONG ) pdTRUE;
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321 /* Something unexpected happened, give up. */
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322 i2cEND_TRANSMISSION( pdFAIL );
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328 /* Should never get here. */
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329 eCurrentState = eSentStart;
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333 /* Clear the interrupt. */
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334 I2C_I2CONCLR = i2cSI_BIT;
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335 VICVectAddr = i2cCLEAR_VIC_INTERRUPT;
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337 portEXIT_SWITCHING_ISR( ( xTaskWokenByTx ) );
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339 /*-----------------------------------------------------------*/
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