2 // You must select RAM, ROM for your controller 04-26-2000
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3 // Your TERN controller is installed with SRAM and ROM with different sizes.
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4 // For debug, 128K or 512K SRAM can be selected
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5 // For build a ROM, you need to select the ROM size.
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7 // 1) commend out the unwanted #define RAM size line with "//"
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8 // 2) delete the "//" preceding the wanted #define RAM size line
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11 // #define RAM 32 // 32KB SRAM installed
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12 #define RAM 128 // 128KB SRAM installed
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13 // #define RAM 512 // 512KB SRAM installed
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15 // #define ROM 32 // Use 32KB ROM chip 27C256-70
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16 #define ROM 64 // Use 64KB ROM chip 27C512-70
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17 // #define ROM 128 // Use 128KB ROM chip 27C010-70
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18 // #define ROM 256 // Use 256KB ROM chip 27C020-70
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19 // #define ROM 512 // Use 512KB ROM chip 27C040-70, Change Jumper on board
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22 cputype Am186ES // AMD188/6 based controllers
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24 #if defined(__PDREMOTE__)
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27 map 0x00000 to 0x00fff as reserved // interrupt vector table
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28 map 0x01000 to 0x03fff as rdwr // System RAM area (60KB RAM)
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29 map 0x04000 to 0x07fff as rdonly // Simulated EPROM area (64KB RAM)
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30 map 0x08000 to 0xfffff as reserved // No access allowed
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31 #define CODE_START 0x0400 // Start of application code, STEP2 !
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34 map 0x00000 to 0x00fff as reserved // interrupt vector table
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35 map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM)
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36 map 0x08000 to 0x1ffff as rdonly // Simulated EPROM area (64KB RAM)
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37 map 0x20000 to 0xfffff as reserved // No access allowed
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38 #define CODE_START 0x0800 // Start of application code
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41 map 0x00000 to 0x00fff as reserved // interrupt vector table
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42 map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM)
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43 map 0x08000 to 0x7ffff as rdonly // Simulated EPROM area(480KB RAM)
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44 map 0x80000 to 0xfffff as reserved // No access allowed
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45 #define CODE_START 0x0800 // Start of application code
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48 #define DATA_START 0x0100 // Start of application data
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49 #define BOOT_START 0x1fc0 // Start of initialization code
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53 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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54 map 0x20000 to 0xf7fff as reserved // No access
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55 map 0xF8000 to 0xfffff as rdonly // 32KB EPROM address space
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56 #define CODE_START 0xF800 // Start of application code
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58 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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59 map 0x20000 to 0xEffff as reserved // No access
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60 map 0xF0000 to 0xfffff as rdonly // 64KB EPROM address space
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61 #define CODE_START 0xF000 // Start of application code
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63 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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64 map 0x20000 to 0xDffff as reserved // No access
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65 map 0xE0000 to 0xfffff as rdonly // 128KB EPROM address space
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66 #define CODE_START 0xE000 // Start of application code
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68 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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69 map 0x20000 to 0xBffff as reserved // No access
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70 map 0xC0000 to 0xfffff as rdonly // 256KB EPROM address space
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71 #define CODE_START 0xC000 // Start of application code
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73 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
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74 map 0x20000 to 0x7ffff as reserved // No access
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75 map 0x80000 to 0xfffff as rdonly // 512KB EPROM address space
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76 #define CODE_START 0x8000 // Start of application code
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79 #define DATA_START 0x0040 // Start of application data
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80 #define BOOT_START 0xffc0 // Start of initialization code
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82 initcode reset \ // Reset vector to program entry point
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83 umcs = 0x80bf \ // 512K ROM, 3 wait states
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84 lmcs = 0x7fbf \ // 512K RAM, 3 wait states
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89 class ??LOCATE = BOOT_START // Chip select initialization
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92 #if ROM == 32 // 27C256-90 EPROM or FLASH
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93 hexfile binary offset=0xf8000 size=32 // for 27C256, bin file
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94 #elif ROM == 64 // 27C512-90 EPROM or FLASH
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95 hexfile binary offset=0xF0000 size=64 // for 27C512
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96 #elif ROM == 128 // 27C010-90 EPROM or FLASH
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97 hexfile binary offset=0xE0000 size=128 // for 27C010
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98 #elif ROM == 256 // 27C020-90 EPROM or FLASH
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99 hexfile binary offset=0xC0000 size=256 // for 27C020
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100 #elif ROM == 512 // 27C040-90 EPROM or FLASH
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101 hexfile Intel86 offset=0x80000 size=512 // for 27C040, output .HEX file
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108 // Start of common configuration file settings.
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111 absfile axe86 // Paradigm C++ debugging output
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112 listfile segments // Absolute segment map
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114 dup DATA ROMDATA // Make a copy of initialized data
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115 dup FAR_DATA ROMFARDATA // Make a copy of far initialized data
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117 #if defined(__COMPFARDATA__) // Compress and display results
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118 compress ROMFARDATA
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119 display compression
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122 class CODE = CODE_START // Application code
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123 class DATA = DATA_START // Application data
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125 order DATA \ // RAM class organization
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130 FAR_DATA ENDFAR_DATA \
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131 FAR_BSS ENDFAR_BSS \
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132 FAR_HEAP ENDFAR_HEAP
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134 order CODE \ // EPROM class organization
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135 INITDATA EXITDATA \
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136 FAR_CONST ENDFAR_CONST \
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137 ROMDATA ENDROMDATA \
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138 ROMFARDATA ENDROMFARDATA
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140 output CODE \ // Classes in the output file(s)
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141 INITDATA EXITDATA \
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142 FAR_CONST ENDFAR_CONST \
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143 ROMDATA ENDROMDATA \
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144 ROMFARDATA ENDROMFARDATA
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