2 ********************************************************************************
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4 * (c) Copyright 2005, http://www.tern.com
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6 * - Created to support i2chip module on a variety of TERN hardware platforms.
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7 ********************************************************************************
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10 #ifndef _I2CHIP_HW_H_
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11 #define _I2CHIP_HW_H_
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15 #ifdef TERN_SC // SensorCore controller, has mapping identical to the RL
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19 #ifdef TERN_RL // R-Engine-L controller, with mapping at MCS0.
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20 #define I2CHIP_MCS_DIRECT
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38 void p51_window(unsigned int page);
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39 #define I2CHIP_WINDOW
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47 #define I2CHIP_WINDOW_IO
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52 #define TERN_EE // C-Eye configured with onboard i2chip, same as EE
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57 #define I2CHIP_MCS_DIRECT
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63 #define I2CHIP_WINDOW
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74 #define I2CHIP_WINDOW_IO
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80 void interrupt far int0_isr(void);
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81 void interrupt far spu_m_isr(void);
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82 void interrupt far spu_1_isr(void);
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83 void interrupt far spu_2_isr(void);
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92 #define I2CHIP_SHIFTED_ADDRESS
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97 #ifndef I2CHIP_MCS_DIRECT
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98 #ifndef I2CHIP_WINDOW
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99 #ifndef I2CHIP_WINDOW_IO
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100 #error You must define the TERN address mapping used to drive the I2CHIP module!
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101 #endif // I2CHIP_WINDOW_IO
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102 #endif // I2CHIP_MMC_WINDOW
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103 #endif // I2CHIP_MCS_DIRECT
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105 #ifndef I2CHIP_INT0
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106 #ifndef I2CHIP_INT3
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107 #ifndef I2CHIP_INT4
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108 #ifndef I2CHIP_POLL
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109 #error You must specify an interrupt/polling mechanism for the I2CHIP module!
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110 #endif // I2CHIP_POLL
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111 #endif // I2CHIP_INT3
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112 #endif // I2CHIP_INT4
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113 #endif // I2CHIP_INT0
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116 #define I2CHIP_POLL_ISR(a) { delay_ms(20); disable(); a(); enable(); }
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117 #define INT_INIT(isr)
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119 #endif // I2CHIP_POLL
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122 #define INT_INIT(isr) int4_init(1, isr)
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123 #define INT_EOI outport(0xff22,0x0010)
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124 #define I2CHIP_POLL_ISR(a)
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128 #define INT_INIT(isr) int3_init(1, isr)
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129 #define INT_EOI outport(0xff22,0x000f)
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130 #define I2CHIP_POLL_ISR(a)
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134 #define INT_INIT(isr) int0_init(1, isr)
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135 #define INT_EOI outportb(_MPICOCW2_IO,0x61); // 586 only EOI
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136 #define I2CHIP_POLL_ISR(a)
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140 #ifdef I2CHIP_SHIFTED_ADDRESS
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141 #define SA_OFFSET(a) ((a) << 1)
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143 #define SA_OFFSET(a) a
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144 #endif // I2CHIP_SHIFTED_ADDRESS ... *if*
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147 // -------------------- WINDOW-RELATED DEFINES ----------------------
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148 #ifdef I2CHIP_WINDOW
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149 void i2chip_set_page(u_int addr);
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150 #define I2CHIP_SET_PAGE(p) i2chip_set_page(p)
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152 u_char far* i2chip_mkptr(u_int addr);
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153 void i2chip_push_window(u_int addr);
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154 void i2chip_pop_window(void);
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155 u_int i2chip_get_window(void);
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156 void i2chip_set_window(u_int window_addr);
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158 // Set to command window.
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159 // Note that if you're using other MMC chips within your application, you will
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160 // need to call this function regularly, if you've changed the MMC chip/page
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161 // selection via mmc_window(). The driver code otherwise assume that you never
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162 // change away from chip 7, page 0.
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163 #define WINDOW_RESTORE_BASE i2chip_mkptr(0)
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165 // ----------------------- I2CHIP_WINDOW_IO ----------------------------
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166 #ifdef I2CHIP_WINDOW_IO
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169 #define I2CHIP_BASE_SEG 0x2000 // Address offset for W3100A
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171 #define I2CHIP_BASE_SEG 0x1800 // Address offset for W3100A
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174 #define COMMAND_BASE_SEG 0x0000
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175 #define SEND_DATA_BUF 0x4000 // Internal Tx buffer address of W3100A
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176 #define RECV_DATA_BUF 0x6000 // Internal Rx buffer address of W3100A
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177 #define WINDOW_BASE_SEGM COMMAND_BASE_SEG
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179 #define MK_FP_WINDOW(a, b) i2chip_mkptr(a+SA_OFFSET(b))
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180 #define MK_FP_SA MK_FP_WINDOW
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182 u_char io_read_value(u_char far* addr);
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183 void io_write_value(u_char far* addr, u_char value);
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184 #define READ_VALUE(a) io_read_value(a)
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185 #define WRITE_VALUE(a, v) io_write_value(a, v)
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187 #define WINDOW_PTR_INC(a) \
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188 if ((FP_OFF(a) & 0xff) == 0xff) \
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189 a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \
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193 #endif // I2CHIP_WINDOW_IO
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195 // -------------------- !NOT! I2CHIP_WINDOW_IO ----------------------------
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196 #ifndef I2CHIP_WINDOW_IO
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198 #define READ_VALUE(a) *(a)
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199 #define WRITE_VALUE(a, v) *(a) = v
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201 #define WINDOW_BASE_SEGM 0x8000
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202 #define MK_FP_WINDOW(a, b) i2chip_mkptr(a+SA_OFFSET(b))
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203 #define MK_FP_SA MK_FP_WINDOW
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205 #ifdef I2CHIP_SHIFTED_ADDRESS
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206 #define COMMAND_BASE_SEG 0x0000
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207 #define SEND_DATA_BUF 0x8000
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208 #define RECV_DATA_BUF 0xC000
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209 #define WINDOW_PTR_INC(a) \
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210 if ((FP_OFF(a) & 0xff) == 0xfe) \
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211 a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \
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215 #define COMMAND_BASE_SEG 0x0000
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216 #define SEND_DATA_BUF 0x4000
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217 #define RECV_DATA_BUF 0x6000
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218 #define WINDOW_PTR_INC(a) \
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219 if ((FP_OFF(a) & 0xff) == 0xff) \
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220 a = MK_FP_WINDOW(i2chip_get_window() + 0x100, 0); \
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223 #endif // I2CHIP_SHIFTED_ADDRESS
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224 #endif // NOT I2CHIP_WINDOW_IO
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226 #endif // I2CHIP_WINDOW
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228 // -------------------- I2CHIP_DIRECT ----------------------------
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229 #ifdef I2CHIP_MCS_DIRECT
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231 #define READ_VALUE(a) *(a)
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232 #define WRITE_VALUE(a, v) *(a) = v
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234 #define I2CHIP_BASE_SEG 0x8000
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235 #define MK_FP_SA(a, b) MK_FP(a, SA_OFFSET(b))
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236 #define WINDOW_PTR_INC(a) a+=SA_OFFSET(1);
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237 #define WINDOW_RESTORE_BASE
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238 #define MK_FP_WINDOW MK_FP_SA
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239 #define WINDOW_BASE_SEG I2CHIP_BASE_SEG
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240 #define COMMAND_BASE_SEG I2CHIP_BASE_SEG
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242 #ifdef I2CHIP_SHIFTED_ADDRESS
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243 #define SEND_DATA_BUF 0x8800 // Internal Tx buffer address of W3100A
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244 #define RECV_DATA_BUF 0x8C00 // Internal Rx buffer address of W3100A
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246 #define SEND_DATA_BUF 0x8400 // Internal Tx buffer address of W3100A
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247 #define RECV_DATA_BUF 0x8600 // Internal Rx buffer address of W3100A
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248 #endif // I2CHIP_SHIFTED_ADDRESS
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250 #endif // I2CHIP_MCS_DIRECT
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252 /* Internal register set of W3100A */
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253 #define COMMAND(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, i)))
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254 #define INT_STATUS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_C0_ISR + i)))
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255 #define INT_REG ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_IR)))
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256 #define INTMASK ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, I2CHIP_IMR)))
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257 #define RESETSOCK ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x0A)))
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259 #define RX_PTR_BASE I2CHIP_C0_RW_PR
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260 #define RX_PTR_SIZE (I2CHIP_C1_RW_PR - I2CHIP_C0_RW_PR)
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262 #define RX_WR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i)))
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263 #define RX_RD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i + 0x04)))
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264 #define RX_ACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i + 0x08)))
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266 #define TX_PTR_BASE I2CHIP_C0_TW_PR
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267 #define TX_PTR_SIZE (I2CHIP_C1_TW_PR - I2CHIP_C0_TW_PR)
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269 #define TX_WR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i)))
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270 #define TX_RD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, TX_PTR_BASE + TX_PTR_SIZE * i + 0x04)))
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271 #define TX_ACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, RX_PTR_BASE + RX_PTR_SIZE * i + 0x08)))
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273 /* Shadow Register Pointer Define */
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274 /* For windowing purposes, these are definitely outside the first 256-byte Window...
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275 therefore, use the MK_FP_WINDOW macros instead. */
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276 #define SHADOW_RXWR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E0 + 3*i)))
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277 #define SHADOW_RXRD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E1 + 3*i)))
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278 #define SHADOW_TXACK_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1E2 + 3*i)))
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279 #define SHADOW_TXWR_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1F0 + 3*i)))
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280 #define SHADOW_TXRD_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, 0x1F1 + 3*i)))
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282 #define SOCK_BASE I2CHIP_C0_SSR
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283 #define SOCK_SIZE (I2CHIP_C1_SSR - I2CHIP_C0_SSR)
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285 #define SOCK_STATUS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i)))
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286 #define OPT_PROTOCOL(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x01)))
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287 #define DST_HA_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x02)))
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288 #define DST_IP_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x08)))
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289 #define DST_PORT_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x0C)))
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290 #define SRC_PORT_PTR(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x0E)))
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291 #define IP_PROTOCOL(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x10)))
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292 #define TOS(i) ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,SOCK_BASE + SOCK_SIZE * i + 0x11)))
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293 #define MSS(i) ((u_int far *)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x12)))
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294 #define P_WINDOW(i) ((u_int far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,SOCK_BASE + SOCK_SIZE * i + 0x14)))
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295 #define WINDOW(i) ((u_int far*)(MK_FP_WINDOW(COMMAND_BASE_SEG, SOCK_BASE + SOCK_SIZE * i + 0x16)))
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297 #define GATEWAY_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_GAR)))
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298 #define SUBNET_MASK_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SMR)))
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300 #define SRC_HA_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SHAR)))
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301 #define SRC_IP_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_SIPR)))
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302 #define TIMEOUT_PTR ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_IRTR)))
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304 #define RX_DMEM_SIZE ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_RMSR)))
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305 #define TX_DMEM_SIZE ((u_char far *)(MK_FP_WINDOW(COMMAND_BASE_SEG,I2CHIP_TMSR)))
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307 void i2chip_init(void);
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309 #endif // _irchip_hw_h
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