2 ********************************************************************************
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4 * (c) Copyright 2005, http://www.tern.com
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6 * - Created to support i2chip module on a variety of TERN hardware platforms.
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7 ********************************************************************************
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10 #include <embedded.h>
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11 #include "i2chip_hw.h"
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17 void i2chip_init(void)
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22 poke(MMCR,_BOOTCSCTL_,peek(MMCR,_BOOTCSCTL_)&0xffc9); // ROM 1 wait
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23 poke(MMCR,_ROMCS2CTL_,peek(MMCR,_ROMCS2CTL_)&0xffc8); // SRAM 0 wait
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25 pokeb(MMCR, _GPCSRT_, 24); // set the GP CS recovery time, 12 works
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26 pokeb(MMCR, _GPCSPW_, 128); // set the GP CS width, 64 works
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27 pokeb(MMCR, _GPCSOFF_, 16); // set the GP CS offset, 8 works
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28 pokeb(MMCR, _GPRDW_, 80); // set the GP RD pulse width, 50 works
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29 pokeb(MMCR, _GPRDOFF_, 30); // set the GP RD offset, 15 works
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30 pokeb(MMCR, _GPWRW_, 80); // set the GP WR pulse width, 50
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31 pokeb(MMCR, _GPWROFF_, 30); // set the GP WR offset, 15
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35 pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0xf7); // set /CS3-/CSM Data Width=8
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36 pokeb(MMCR, _CSPFS_, peekb(MMCR, _CSPFS_)|0x08); // set the GP CS3 PIN Function
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37 poke(MMCR, _PAR15_, 0x2000); // set CS3 I/O region
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38 poke(MMCR, _PAR15_+2, 0x2dff); // set CS3 I/O region, 512 bytes
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40 pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0x7f); // CS7=J4.3 Data Width=8, /CSI
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41 // pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)|0x80); // CS7=J4.3 Data Width=16
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42 pokeb(MMCR, _CSPFS_, peekb(MMCR, _CSPFS_)|0x80); // set the GP CS7 PIN Function
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43 poke(MMCR, _PAR7_, 0x4000); // set CS7 I/O region
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44 poke(MMCR, _PAR7_+2, 0x3dff); // set CS7 I/O region, 512 bytes
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46 // If it's not 5E, then it must be 5P... in which case, we use PCS0 and
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47 // PCS1 as the chip-selects.
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48 pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0xfe); // CS0 Data Width=8
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49 poke(MMCR, _PIOPFS31_16_, peek(MMCR,_PIOPFS31_16_)|0x0800); // P27=/CS0
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50 poke(MMCR, _PAR13_, 0x1800); // CS0 I/O region
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51 poke(MMCR, _PAR13_+2, 0x21ff); // CS0 I/O RW, 512 bytes, start 0x1800
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54 a HLPRsetvect(0x47, (void far *) spu_m_isr);
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55 HLPRsetvect(0x4f, (void far *) spu_1_isr);
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56 HLPRsetvect(0x57, (void far *) spu_2_isr);
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57 #endif // 186, or RE
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60 pio_init(18, 0); // P18=CTS1 for /PCS2
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63 outport(0xfff2, 2); // AUXCON, MCS, Bus 16-bit
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66 #ifdef I2CHIP_MCS_DIRECT
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67 outport(0xffa0,0xc0bf); // UMCS, 256K ROM, disable AD15-0
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68 outport(0xfff0,inport(0xfff0)|0x4000 ); // SYSCON, MCS0 0x80000-0xbffff
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69 outport(0xffa8,0xa0bf ); // MPCS, MCS0=P14, 64KB, PCS I/O,
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70 outport(0xffa6,0x81ff); // MMCS, base 0x80000,
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71 outport(0xffa2,0x7fbf); // 512K RAM,
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72 outport(0xffa4,0x007d); // PACS, base 0,
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76 outport( 0xffa0,0xc0bf); // UMCS, 256K ROM, 3 wait, disable AD15-0
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77 outport( 0xfff0,inport(0xfff0)|0x4000 ); // SYSCON, MCS0 0x80000-0xbffff
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78 // outport( 0xffa8,0xa0bc ); // MPCS, MCS0=P14, 64KB, PCS I/O 0 wait
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79 // outport( 0xffa8,0xa0bd ); // MPCS, MCS0=P14, 64KB, PCS I/O 1 wait
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80 outport( 0xffa8,0xa0bf ); // MPCS, MCS0=P14, 64KB, PCS I/O 1 wait
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81 #endif // I2CHIP_MCS_DIRECT
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83 #ifndef TERN_RE // 80 MHz R- boards can't tolerate zero wait state.
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84 outport( 0xffa6,0x81ff ); // MMCS, base 0x80000
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85 outport(0xffa2,0x7fbe); // 512K RAM, 0 wait states
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86 outport(0xffa4,0x007d); // PACS, base 0, 0 wait
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88 pio_init(14,0); // Enable /MCS0
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93 #ifdef I2CHIP_WINDOW
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94 #ifdef I2CHIP_SHIFTED_ADDRESS
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95 pio_init(12, 2); // Configure P12 as A7, an output we'll be using.
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96 pio_wr(12, 0); // Set A7 low, initially.
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98 WINDOW_RESTORE_BASE; // Equivalent to calling mmc_window(7, 0);
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102 #ifdef I2CHIP_WINDOW
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104 void i2chip_set_page(u_int page)
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106 u_int new_page = page;
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108 #ifdef I2CHIP_SHIFTED_ADDRESS
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109 if (page & 0x01) // ... we're checking the right-most bit in the page.
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110 outport(0xff74, inport(0xff74) | 0x1000 ); // Using P12 as A7...
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112 outport(0xff74, inport(0xff74) & 0xefff );
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114 new_page = page >> 1;
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118 mmc_window(7, new_page); // See mmc.c
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121 p51_window(new_page);
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125 static u_int s_addr = 0xffff;
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126 u_char far* i2chip_mkptr(u_int addr)
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128 if ((s_addr & 0xff00) == (addr & 0xff00)) // No point... no point...
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129 return MK_FP(WINDOW_BASE_SEGM, addr & 0xff);
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133 // So the argument to this function is... what again?
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134 // I think it should be the highest 16-bits... or, in other words,
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135 // FP_SEG of a huge ptr.
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136 // Ok, and the *return* value should be a UINT value for the new
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137 // segment address to be used, if it's at all needed. TODO
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138 I2CHIP_SET_PAGE(s_addr >> 8); // Portable version
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139 // outportb(0x00, addr>>8); // quicker version
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141 return MK_FP(WINDOW_BASE_SEGM, addr & 0xff);
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144 void i2chip_set_window(u_int window_addr)
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146 s_addr = window_addr;
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147 I2CHIP_SET_PAGE(s_addr >> 8);
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150 // Still inside #define I2CHIP_WINDOW ...
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152 u_int i2chip_get_window(void)
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154 return s_addr & 0xff00;
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157 void i2chip_push_window(u_int addr)
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159 I2CHIP_SET_PAGE(addr>>8);
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162 void i2chip_pop_window(void)
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164 I2CHIP_SET_PAGE(s_addr >> 8);
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167 #ifdef I2CHIP_WINDOW_IO
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168 u_char io_read_value(u_char far* addr)
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170 // return value ... we assume the page is already set. So, instead,
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171 // we just go ahead and output valeu.
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172 return inportb(I2CHIP_BASE_SEG + (FP_OFF(addr) & 0xff));
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175 void io_write_value(u_char far* addr, u_char value)
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177 // Get the last whatever bytes... and write value.
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178 outportb(I2CHIP_BASE_SEG + (FP_OFF(addr) & 0xff), value);
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181 #endif // I2CHIP_WINDOW_IO
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185 void p51_window(unsigned int page)
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189 #ifdef I2CHIP_WINDOW_IO
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197 #endif // I2CHIP_P51
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199 #endif // I2CHIP_WINDOW
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203 // Function: spu_m_isr
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204 // P22=Master PIC IR7, interrupt vector=0x47, /INTA
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206 void interrupt far spu_m_isr(void)
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209 // Issue the EOI to interrupt controller
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210 outportb(_MPICOCW2_IO,0x67); // Specific EQI for master IR7
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215 // Function: spu_1_isr
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216 // P10=slave1 PIC IR7, Master IR2, interrupt vector=0x4f, /INTC
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218 void interrupt far spu_1_isr(void)
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221 // Issue the EOI to interrupt controller
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222 outportb(_S1PICOCW2_IO,0x67); // Specific EOI for slave 1 IR7
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223 outportb(_MPICOCW2_IO,0x62); // Specific EQI for master IR2
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228 // Function: spu_2_isr
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229 // P20=Slave2 PIC IR7, Master IR5, interrupt vector=0x57, GPIRQ7=PIO16 GP timer1
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231 void interrupt far spu_2_isr(void)
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234 // Issue the EOI to interrupt controller
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235 outportb(_S2PICOCW2_IO,0x67); // Specific EOI for slave 1 IR7
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236 outportb(_MPICOCW2_IO,0x65); // Specific EQI for master IR5
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