2 FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 ***************************************************************************
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29 * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
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30 * and even write all or part of your application on your behalf. *
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31 * See http://www.OpenRTOS.com for details of the services we provide to *
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32 * expedite your project. *
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34 ***************************************************************************
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35 ***************************************************************************
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37 Please ensure to read the configuration and relevant port sections of the
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38 online documentation.
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40 http://www.FreeRTOS.org - Documentation, latest information, license and
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43 http://www.SafeRTOS.com - A version that is certified for use in safety
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46 http://www.OpenRTOS.com - Commercial support, development, porting,
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47 licensing and training services.
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51 * Interrupt driven driver for the EMAC peripheral. This driver is not
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52 * reentrant, re-entrancy is handled by a semaphore at the network interface
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60 + Corrected the byte order when writing the MAC address to the MAC.
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61 + Support added for MII interfaces. Previously only RMII was supported.
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65 + The MII interface is now the default.
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66 + Modified the initialisation sequence slightly to allow auto init more
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71 + Made the function vClearEMACTxBuffer() more robust by moving the index
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72 manipulation into the if() statement. This allows the tx interrupt to
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73 execute even when there is no data to handle.
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77 + Corrected the Rx frame length mask when obtaining the length from the
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82 /* Standard includes. */
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85 /* Scheduler includes. */
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86 #include "FreeRTOS.h"
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90 /* Demo app includes. */
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91 #include "SAM7_EMAC.h"
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93 /* Hardware specific includes. */
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96 #include "AT91SAM7X256.h"
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99 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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100 to use an MII interface. */
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101 #define USE_RMII_INTERFACE 0
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104 /* The buffer addresses written into the descriptors must be aligned so the
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105 last few bits are zero. These bits have special meaning for the EMAC
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106 peripheral and cannot be used as part of the address. */
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107 #define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )
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109 /* Bit used within the address stored in the descriptor to mark the last
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110 descriptor in the array. */
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111 #define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )
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113 /* Bit used within the Tx descriptor status to indicate whether the
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114 descriptor is under the control of the EMAC or the software. */
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115 #define emacTX_BUF_USED ( ( unsigned portLONG ) 0x80000000 )
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117 /* A short delay is used to wait for a buffer to become available, should
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118 one not be immediately available when trying to transmit a frame. */
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119 #define emacBUFFER_WAIT_DELAY ( 2 )
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120 #define emacMAX_WAIT_CYCLES ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
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122 /* The time to block waiting for input. */
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123 #define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( portTickType ) 100 )
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125 /* Peripheral setup for the EMAC. */
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126 #define emacPERIPHERAL_A_SETUP ( ( unsigned portLONG ) AT91C_PB2_ETX0 ) | \
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127 ( ( unsigned portLONG ) AT91C_PB12_ETXER ) | \
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128 ( ( unsigned portLONG ) AT91C_PB16_ECOL ) | \
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129 ( ( unsigned portLONG ) AT91C_PB11_ETX3 ) | \
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130 ( ( unsigned portLONG ) AT91C_PB6_ERX1 ) | \
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131 ( ( unsigned portLONG ) AT91C_PB15_ERXDV ) | \
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132 ( ( unsigned portLONG ) AT91C_PB13_ERX2 ) | \
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133 ( ( unsigned portLONG ) AT91C_PB3_ETX1 ) | \
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134 ( ( unsigned portLONG ) AT91C_PB8_EMDC ) | \
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135 ( ( unsigned portLONG ) AT91C_PB5_ERX0 ) | \
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136 ( ( unsigned portLONG ) AT91C_PB14_ERX3 ) | \
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137 ( ( unsigned portLONG ) AT91C_PB4_ECRS_ECRSDV ) | \
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138 ( ( unsigned portLONG ) AT91C_PB1_ETXEN ) | \
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139 ( ( unsigned portLONG ) AT91C_PB10_ETX2 ) | \
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140 ( ( unsigned portLONG ) AT91C_PB0_ETXCK_EREFCK ) | \
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141 ( ( unsigned portLONG ) AT91C_PB9_EMDIO ) | \
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142 ( ( unsigned portLONG ) AT91C_PB7_ERXER ) | \
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143 ( ( unsigned portLONG ) AT91C_PB17_ERXCK );
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145 /* Misc defines. */
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146 #define emacINTERRUPT_LEVEL ( 5 )
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147 #define emacNO_DELAY ( 0 )
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148 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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149 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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150 #define emacRESET_KEY ( ( unsigned portLONG ) 0xA5000000 )
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151 #define emacRESET_LENGTH ( ( unsigned portLONG ) ( 0x01 << 8 ) )
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153 /* The Atmel header file only defines the TX frame length mask. */
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154 #define emacRX_LENGTH_FRAME ( 0xfff )
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156 /*-----------------------------------------------------------*/
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158 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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159 comment above the emacADDRESS_MASK definition. */
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160 static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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162 /* Buffer read by the EMAC DMA. Must be aligned as described by the comment
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163 above the emacADDRESS_MASK definition. */
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164 static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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166 /* Descriptors used to communicate between the program and the EMAC peripheral.
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167 These descriptors hold the locations and state of the Rx and Tx buffers. */
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168 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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169 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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171 /* The IP and Ethernet addresses are read from the header files. */
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172 const portCHAR cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
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173 const unsigned char ucIPAddress[ 4 ] = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };
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175 /*-----------------------------------------------------------*/
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177 /* See the header file for descriptions of public functions. */
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180 * Prototype for the EMAC interrupt function.
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182 void vEMACISR_Wrapper( void ) __attribute__ ((naked));
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185 * Initialise both the Tx and Rx descriptors used by the EMAC.
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187 static void prvSetupDescriptors(void);
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190 * Write our MAC address into the EMAC.
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192 static void prvSetupMACAddress( void );
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195 * Configure the EMAC and AIC for EMAC interrupts.
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197 static void prvSetupEMACInterrupt( void );
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200 * Some initialisation functions taken from the Atmel EMAC sample code.
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202 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
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203 static portBASE_TYPE xGetLinkSpeed( void );
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204 static portBASE_TYPE prvProbePHY( void );
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205 #if USE_RMII_INTERFACE != 1
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206 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
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210 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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211 static xSemaphoreHandle xSemaphore = NULL;
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213 /* Holds the index to the next buffer from which data will be read. */
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214 static volatile unsigned portLONG ulNextRxBuffer = 0;
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216 /*-----------------------------------------------------------*/
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218 /* See the header file for descriptions of public functions. */
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219 portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame )
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221 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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222 portBASE_TYPE xWaitCycles = 0;
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223 portLONG lReturn = pdPASS;
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224 portCHAR *pcBuffer;
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225 unsigned portLONG ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
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227 /* If the length of data to be transmitted is greater than each individual
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228 transmit buffer then the data will be split into more than one buffer.
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229 Loop until the entire length has been buffered. */
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230 while( ulDataBuffered < ulLength )
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232 /* Is a buffer available? */
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233 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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235 /* There is no room to write the Tx data to the Tx buffer. Wait a
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236 short while, then try again. */
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238 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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246 vTaskDelay( emacBUFFER_WAIT_DELAY );
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250 /* lReturn will only be pdPASS if a buffer is available. */
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251 if( lReturn == pdPASS )
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253 portENTER_CRITICAL();
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255 /* Get the address of the buffer from the descriptor, then copy
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256 the data into the buffer. */
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257 pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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259 /* How much can we write to the buffer? */
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260 ulDataRemainingToSend = ulLength - ulDataBuffered;
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261 if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
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263 /* We can write all the remaining bytes. */
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264 ulLengthToSend = ulDataRemainingToSend;
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268 /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
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269 ulLengthToSend = ETH_TX_BUFFER_SIZE;
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272 /* Copy the data into the buffer. */
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273 memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
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274 ulDataBuffered += ulLengthToSend;
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276 /* Is this the last data for the frame? */
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277 if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
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279 /* No more data remains for this frame so we can start the
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281 ulLastBuffer = AT91C_LAST_BUFFER;
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285 /* More data to come for this frame. */
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289 /* Fill out the necessary in the descriptor to get the data sent,
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290 then move to the next descriptor, wrapping if necessary. */
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291 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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293 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
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295 | AT91C_TRANSMIT_WRAP;
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296 uxTxBufferIndex = 0;
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300 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
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305 /* If this is the last buffer to be sent for this frame we can
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306 start the transmission. */
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309 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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312 portEXIT_CRITICAL();
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322 /*-----------------------------------------------------------*/
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324 /* See the header file for descriptions of public functions. */
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325 unsigned portLONG ulEMACInputLength( void )
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327 register unsigned portLONG ulIndex, ulLength = 0;
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329 /* Skip any fragments. We are looking for the first buffer that contains
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330 data and has the SOF (start of frame) bit set. */
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331 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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333 /* Ignoring this buffer. Mark it as free again. */
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334 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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336 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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338 ulNextRxBuffer = 0;
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342 /* We are going to walk through the descriptors that make up this frame,
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343 but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
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344 from finding the data. Therefore use a copy of ulNextRxBuffer instead. */
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345 ulIndex = ulNextRxBuffer;
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347 /* Walk through the descriptors until we find the last buffer for this
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348 frame. The last buffer will give us the length of the entire frame. */
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349 while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )
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351 ulLength = xRxDescriptors[ ulIndex ].U_Status.status & emacRX_LENGTH_FRAME;
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353 /* Increment to the next buffer, wrapping if necessary. */
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355 if( ulIndex >= NB_RX_BUFFERS )
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363 /*-----------------------------------------------------------*/
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365 /* See the header file for descriptions of public functions. */
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366 void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength )
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368 static unsigned portLONG ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
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369 static portCHAR *pcSource;
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370 register unsigned portLONG ulBytesRemainingInBuffer, ulRemainingSectionBytes;
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372 /* Read ulSectionLength bytes from the Rx buffers. This is not necessarily any
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373 correspondence between the length of our Rx buffers, and the length of the
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374 data we are returning or the length of the data being requested. Therefore,
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375 between calls we have to remember not only which buffer we are currently
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376 processing, but our position within that buffer. This would be greatly
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377 simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
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378 the size of each Rx buffer, and that memory fragmentation did not occur.
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380 This function should only be called after a call to ulEMACInputLength().
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381 This will ensure ulNextRxBuffer is set to the correct buffer. */
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385 /* vEMACRead is called with pcTo set to NULL to indicate that we are about
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386 to read a new frame. Any fragments remaining in the frame we were
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387 processing during the last call should be dropped. */
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390 /* How many bytes are indicated as being in this buffer? If none then
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391 the buffer is completely full and the frame is contained within more
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392 than one buffer. */
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394 /* Reset our state variables ready for the next read from this buffer. */
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395 pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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396 ulFameBytesReadSoFar = ( unsigned portLONG ) 0;
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397 ulBufferPosition = ( unsigned portLONG ) 0;
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401 /* Loop until we have obtained the required amount of data. */
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402 ulSectionBytesReadSoFar = 0;
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403 while( ulSectionBytesReadSoFar < ulSectionLength )
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405 /* We may have already read some data from this buffer. How much
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406 data remains in the buffer? */
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407 ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
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409 /* How many more bytes do we need to read before we have the
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410 required amount of data? */
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411 ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
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413 /* Do we want more data than remains in the buffer? */
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414 if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
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416 /* We want more data than remains in the buffer so we can
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417 write the remains of the buffer to the destination, then move
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418 onto the next buffer to get the rest. */
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419 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
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420 ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
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421 ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
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423 /* Mark the buffer as free again. */
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424 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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426 /* Move onto the next buffer. */
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428 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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430 ulNextRxBuffer = ( unsigned portLONG ) 0;
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433 /* Reset the variables for the new buffer. */
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434 pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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435 ulBufferPosition = ( unsigned portLONG ) 0;
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439 /* We have enough data in this buffer to send back. Read out
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440 enough data and remember how far we read up to. */
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441 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
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443 /* There may be more data in this buffer yet. Increment our
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444 position in this buffer past the data we have just read. */
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445 ulBufferPosition += ulRemainingSectionBytes;
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446 ulSectionBytesReadSoFar += ulRemainingSectionBytes;
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447 ulFameBytesReadSoFar += ulRemainingSectionBytes;
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449 /* Have we now finished with this buffer? */
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450 if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
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452 /* Mark the buffer as free again. */
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453 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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455 /* Move onto the next buffer. */
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457 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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459 ulNextRxBuffer = 0;
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462 pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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463 ulBufferPosition = 0;
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469 /*-----------------------------------------------------------*/
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471 /* See the header file for descriptions of public functions. */
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472 xSemaphoreHandle xEMACInit( void )
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474 /* Code supplied by Atmel -------------------------------*/
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476 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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477 PHY has internal pull down. */
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478 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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480 #if USE_RMII_INTERFACE != 1
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481 /* PHY has internal pull down : set MII mode. */
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482 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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485 /* Clear PB18 <=> PHY powerdown. */
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486 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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487 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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488 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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490 /* After PHY power up, hardware reset. */
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491 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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492 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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494 /* Wait for hardware reset end. */
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495 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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497 __asm volatile ( "NOP" );
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499 __asm volatile ( "NOP" );
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501 /* Setup the pins. */
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502 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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503 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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505 /* Enable com between EMAC PHY.
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507 Enable management port. */
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508 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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510 /* MDC = MCK/32. */
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511 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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513 /* Wait for PHY auto init end (rather crude delay!). */
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514 vTaskDelay( emacPHY_INIT_DELAY );
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516 /* PHY configuration. */
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517 #if USE_RMII_INTERFACE != 1
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519 unsigned portLONG ulControl;
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521 /* PHY has internal pull down : disable MII isolate. */
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522 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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523 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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524 ulControl &= ~BMCR_ISOLATE;
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525 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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529 /* Disable management port again. */
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530 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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532 #if USE_RMII_INTERFACE != 1
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533 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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534 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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536 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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538 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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541 /* End of code supplied by Atmel ------------------------*/
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543 /* Setup the buffers and descriptors. */
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544 prvSetupDescriptors();
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546 /* Load our MAC address into the EMAC. */
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547 prvSetupMACAddress();
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549 /* Are we connected? */
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550 if( prvProbePHY() )
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552 /* Enable the interrupt! */
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553 portENTER_CRITICAL();
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555 prvSetupEMACInterrupt();
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556 vPassEMACSemaphore( xSemaphore );
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558 portEXIT_CRITICAL();
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563 /*-----------------------------------------------------------*/
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565 /* See the header file for descriptions of public functions. */
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566 void vClearEMACTxBuffer( void )
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568 static unsigned portBASE_TYPE uxNextBufferToClear = 0;
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570 /* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each
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571 Tx buffer within the frame just transmitted. This marks all the buffers
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572 as available again.
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574 The first buffer in the frame should have the bit set automatically. */
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575 if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )
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577 /* Loop through the other buffers in the frame. */
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578 while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )
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580 uxNextBufferToClear++;
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582 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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584 uxNextBufferToClear = 0;
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587 xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;
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590 /* Start with the next buffer the next time a Tx interrupt is called. */
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591 uxNextBufferToClear++;
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593 /* Do we need to wrap back to the first buffer? */
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594 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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596 uxNextBufferToClear = 0;
\r
600 /*-----------------------------------------------------------*/
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602 static void prvSetupDescriptors(void)
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604 unsigned portBASE_TYPE xIndex;
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605 unsigned portLONG ulAddress;
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607 /* Initialise xRxDescriptors descriptor. */
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608 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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610 /* Calculate the address of the nth buffer within the array. */
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611 ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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613 /* Write the buffer address into the descriptor. The DMA will place
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614 the data at this address when this descriptor is being used. Mask off
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615 the bottom bits of the address as these have special meaning. */
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616 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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619 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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620 to the first buffer. */
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621 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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623 /* Initialise xTxDescriptors. */
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624 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
\r
626 /* Calculate the address of the nth buffer within the array. */
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627 ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
\r
629 /* Write the buffer address into the descriptor. The DMA will read
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630 data from here when the descriptor is being used. */
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631 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
632 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
\r
635 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
636 to the first buffer. */
\r
637 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
\r
639 /* Tell the EMAC where to find the descriptors. */
\r
640 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
\r
641 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
\r
643 /* Clear all the bits in the receive status register. */
\r
644 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
\r
646 /* Enable the copy of data into the buffers, ignore broadcasts,
\r
647 and don't copy FCS. */
\r
648 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
\r
650 /* Enable Rx and Tx, plus the stats register. */
\r
651 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
653 /*-----------------------------------------------------------*/
\r
655 static void prvSetupMACAddress( void )
\r
657 /* Must be written SA1L then SA1H. */
\r
658 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
\r
659 ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
\r
660 ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) |
\r
663 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
\r
666 /*-----------------------------------------------------------*/
\r
668 static void prvSetupEMACInterrupt( void )
\r
670 /* Create the semaphore used to trigger the EMAC task. */
\r
671 vSemaphoreCreateBinary( xSemaphore );
\r
674 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
\r
675 first interrupt occurs. */
\r
676 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
677 portENTER_CRITICAL();
\r
679 /* We want to interrupt on Rx and Tx events. */
\r
680 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
\r
682 /* Enable the interrupts in the AIC. */
\r
683 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
\r
684 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
686 portEXIT_CRITICAL();
\r
695 * The following functions are initialisation functions taken from the Atmel
\r
696 * EMAC sample code.
\r
700 static portBASE_TYPE prvProbePHY( void )
\r
702 unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
\r
703 portBASE_TYPE xReturn = pdPASS;
\r
705 /* Code supplied by Atmel (reformatted) -----------------*/
\r
707 /* Enable management port */
\r
708 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
709 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
711 /* Read the PHY ID. */
\r
712 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
713 vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
718 Bits 3:0 Revision Number Four bit manufacturer?s revision number.
\r
719 0001 stands for Rev. A, etc.
\r
721 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
723 /* Did not expect this ID. */
\r
728 ulStatus = xGetLinkSpeed();
\r
730 if( ulStatus != pdPASS )
\r
736 /* Disable management port */
\r
737 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
739 /* End of code supplied by Atmel ------------------------*/
\r
743 /*-----------------------------------------------------------*/
\r
745 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
\r
747 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
749 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
750 | (2 << 16) | (2 << 28)
\r
751 | ((ucPHYAddress & 0x1f) << 23)
\r
752 | (ucAddress << 18);
\r
754 /* Wait until IDLE bit in Network Status register is cleared. */
\r
755 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
760 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
762 /* End of code supplied by Atmel ------------------------*/
\r
764 /*-----------------------------------------------------------*/
\r
766 #if USE_RMII_INTERFACE != 1
\r
767 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
\r
769 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
771 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
772 | (2 << 16) | (1 << 28)
\r
773 | ((ucPHYAddress & 0x1f) << 23)
\r
774 | (ucAddress << 18))
\r
775 | (ulValue & 0xffff);
\r
777 /* Wait until IDLE bit in Network Status register is cleared */
\r
778 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
783 /* End of code supplied by Atmel ------------------------*/
\r
786 /*-----------------------------------------------------------*/
\r
788 static portBASE_TYPE xGetLinkSpeed( void )
\r
790 unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
792 /* Code supplied by Atmel (reformatted) -----------------*/
\r
794 /* Link status is latched, so read twice to get current value */
\r
795 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
796 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
798 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
804 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
805 if (ulBMCR & BMCR_ANENABLE)
\r
807 /* AutoNegotiation is enabled. */
\r
808 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
810 /* Auto-negotitation in progress. */
\r
814 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
815 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
817 ulSpeed = SPEED_100;
\r
821 ulSpeed = SPEED_10;
\r
824 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
826 ulDuplex = DUPLEX_FULL;
\r
830 ulDuplex = DUPLEX_HALF;
\r
835 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
836 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
839 /* Update the MAC */
\r
840 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
841 if( ulSpeed == SPEED_100 )
\r
843 if( ulDuplex == DUPLEX_FULL )
\r
845 /* 100 Full Duplex */
\r
846 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
850 /* 100 Half Duplex */
\r
851 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
856 if (ulDuplex == DUPLEX_FULL)
\r
858 /* 10 Full Duplex */
\r
859 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
862 { /* 10 Half Duplex */
\r
863 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
867 /* End of code supplied by Atmel ------------------------*/
\r
871 /*-----------------------------------------------------------*/
\r
873 void vEMACWaitForInput( void )
\r
875 /* Just wait until we are signled from an ISR that data is available, or
\r
876 we simply time out. */
\r
877 xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
\r