2 * Copyright (c) 2006 Christian Walter
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 * 3. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
19 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
21 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
27 * Author: Christian Walter <wolti@sil.at>
30 * - Introduce another task create function in the sys_arch layer which allows
31 * for passing the stack size.
32 * - Avoid copying the buffers - this requires changeing the nbuf driver code
33 * to use the lwIP pbuf buffer implementation.
35 * File: $Id: fec.c,v 1.3 2006/08/29 18:53:46 wolti Exp $
38 /* ------------------------ System includes ------------------------------- */
41 /* ------------------------ Platform includes ----------------------------- */
47 /* ------------------------ lwIP includes --------------------------------- */
51 #include "lwip/pbuf.h"
53 #include "lwip/stats.h"
54 #include "lwip/debug.h"
55 #include "netif/etharp.h"
57 /* ------------------------ Defines --------------------------------------- */
59 #define FEC_DEBUG_INIT \
62 MCF_GPIO_PDDR_FECI2C = ( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 | \
63 MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \
66 #define FEC_DEBUG_RX_TIMING( x ) \
70 MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0; \
72 MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 ); \
75 #define FEC_DEBUG_TX_TIMING( x ) \
79 MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1; \
81 MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \
85 #define FEC_DEBUG DBG_OFF
86 #define FEC_DEBUG_INIT
87 #define FEC_DEBUG_RX_TIMING( x )
88 #define FEC_DEBUG_TX_TIMING( x )
91 #define MCF_FEC_INT_LEVEL ( 6 )
92 #define MCF_FEC_INT_PRIORITY ( 0 )
93 #define MCF_FEC_VEC_RXF ( 64 + 27 )
94 #define MCF_FEC_MTU ( 1518 )
96 #define ETH_ADDR_LEN ( 6 )
98 #define TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
100 /* ------------------------ Type definitions ------------------------------ */
103 struct netif *netif; /* lwIP network interface. */
104 struct eth_addr *self; /* MAC address of FEC interface. */
105 sys_sem_t tx_sem; /* Control access to transmitter. */
106 sys_sem_t rx_sem; /* Semaphore to signal receive thread. */
109 /* ------------------------ Static variables ------------------------------ */
110 static mcf523xfec_if_t *fecif_g;
112 /* ------------------------ Static functions ------------------------------ */
113 static err_t mcf523xfec_output( struct netif *, struct pbuf *, struct ip_addr * );
114 static err_t mcf523xfec_output_raw( struct netif *, struct pbuf * );
116 static void mcf523xfec_reset( mcf523xfec_if_t * fecif );
117 static void mcf523xfec_enable( mcf523xfec_if_t * fecif );
118 static void mcf523xfec_disable( mcf523xfec_if_t * fecif );
119 static void mcf523xfec_get_mac( mcf523xfec_if_t * fecif, struct eth_addr *mac );
120 static void mcf523xfec_rx_irq( void );
121 static void mcf523xfec_rx_task( void *arg );
123 static void arp_timer( void *arg );
124 static void eth_input( struct netif *netif, struct pbuf *p );
126 /* ------------------------ Start implementation -------------------------- */
129 arp_timer( void *arg )
133 sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
137 mcf523xfec_output_raw( struct netif *netif, struct pbuf *p )
141 mcf523xfec_if_t *fecif = netif->state;
146 pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */
150 /* Test if we can handle such big frames. If not drop it. */
151 if( p->tot_len > MCF_FEC_MTU )
154 lwip_stats.link.lenerr++;
158 /* Test if our network buffer scheme can handle a packet of this size. If
159 * not drop it and return a memory error. */
160 else if( p->tot_len > TX_BUFFER_SIZE )
163 lwip_stats.link.memerr++;
167 /* Allocate a transmit buffer. If no buffer is available drop the frame. */
168 else if( ( pNBuf = nbuf_tx_allocate( ) ) == NULL )
170 LWIP_ASSERT( "mcf523xfec_output_raw: pNBuf != NULL\n", pNBuf != NULL );
172 lwip_stats.link.memerr++;
182 memcpy( &pNBuf->data[i], q->payload, q->len );
185 while( ( q = q->next ) != NULL );
186 pNBuf->length = p->tot_len;
188 /* Set Frame ready for transmission. */
189 pNBuf->status |= TX_BD_R;
190 /* Mark the buffer as not in use so the FEC can take it. */
191 nbuf_tx_release( pNBuf );
192 /* Indicate that a new transmit buffer has been produced. */
195 lwip_stats.link.xmit++;
200 sys_sem_signal( fecif->tx_sem );
202 buf_header( p, ETH_PAD_SIZE );
208 /* This function is called by the TCP/IP stack when an IP packet should be
209 * sent. It uses the ethernet ARP module provided by lwIP to resolve the
210 * destination MAC address. The ARP module will later call our low level
211 * output function mcf523xfec_output_raw.
214 mcf523xfec_output( struct netif * netif, struct pbuf * p, struct ip_addr * ipaddr )
217 mcf523xfec_if_t *fecif = netif->state;
219 FEC_DEBUG_TX_TIMING( 1 );
220 /* Make sure only one thread is in this function. */
221 sys_sem_wait( fecif->tx_sem );
222 res = etharp_output( netif, ipaddr, p );
223 FEC_DEBUG_TX_TIMING( 0 );
228 mcf523xfec_rx_task( void *arg )
230 mcf523xfec_if_t *fecif = arg;
237 sys_sem_wait( fecif->rx_sem );
238 while( nbuf_rx_next_ready( ) )
240 pNBuf = nbuf_rx_allocate( );
243 LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->status & RX_BD_L ",
244 pNBuf->status & RX_BD_L );
246 /* This flags indicate that the frame has been damaged. In
247 * this case we must update the link stats if enabled and
248 * remove the frame from the FEC. */
249 if ( pNBuf->status & ( RX_BD_LG | RX_BD_NO |
250 RX_BD_CR | RX_BD_OV ) )
253 lwip_stats.link.drop++;
254 if ( pNBuf->status & RX_BD_LG)
256 lwip_stats.link.lenerr++;
258 else if ( pNBuf->status & ( RX_BD_NO | RX_BD_OV ) )
260 lwip_stats.link.err++;
264 lwip_stats.link.chkerr++;
270 /* The frame must no be valid. Perform some checks to see if the FEC
271 * driver is working correctly.
273 LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->length != 0", pNBuf->length != 0 );
274 p = pbuf_alloc( PBUF_RAW, pNBuf->length, PBUF_POOL );
278 pbuf_header( p, -ETH_PAD_SIZE );
280 pPayLoad = pNBuf->data;
281 for( q = p; q != NULL; q = q->next )
283 memcpy( q->payload, pPayLoad, q->len );
287 pbuf_header( p, ETH_PAD_SIZE );
290 /* Ethernet frame received. Handling it is not device
291 * dependent and therefore done in another function.
293 eth_input( fecif->netif, p );
296 nbuf_rx_release( pNBuf );
298 /* Tell the HW that there are new free RX buffers. */
304 lwip_stats.link.memerr++;
305 lwip_stats.link.drop++;
309 /* Set RX Debug PIN to low since handling of next frame is possible. */
310 FEC_DEBUG_RX_TIMING( 0 );
316 eth_input( struct netif *netif, struct pbuf *p )
318 struct eth_hdr *eth_hdr = p->payload;
320 LWIP_ASSERT( "eth_input: p != NULL ", p != NULL );
322 switch ( htons( eth_hdr->type ) )
325 /* Pass to ARP layer. */
326 etharp_ip_input( netif, p );
328 /* Skip Ethernet header. */
329 pbuf_header( p, ( s16_t ) - sizeof( struct eth_hdr ) );
331 /* Pass to network layer. */
332 netif->input( p, netif );
336 /* Pass to ARP layer. */
337 etharp_arp_input( netif, ( struct eth_addr * )netif->hwaddr, p );
347 mcf523xfec_rx_irq( void )
349 static portBASE_TYPE xNeedSwitch = pdFALSE;
351 /* Workaround GCC if frame pointers are enabled. This is an ISR and
352 * we must not modify the stack before portENTER_SWITCHING_ISR( )
353 * has been called. */
354 #if _GCC_USES_FP == 1
355 asm volatile ( "unlk %fp\n\t" );
358 /* This ISR can cause a context switch, so the first statement must be
359 * a call to the portENTER_SWITCHING_ISR() macro.
361 portENTER_SWITCHING_ISR( );
363 /* Set Debug PIN to high to measure RX latency. */
364 FEC_DEBUG_RX_TIMING( 1 );
366 /* Clear FEC RX Event from the Event Register (by writing 1) */
367 if( MCF_FEC_EIR & ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF ) )
369 /* Clear interrupt from EIR register immediately */
370 MCF_FEC_EIR = ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF );
371 xNeedSwitch = xSemaphoreGiveFromISR( fecif_g->rx_sem, pdFALSE );
373 portEXIT_SWITCHING_ISR( xNeedSwitch );
377 mcf523xfec_reset( mcf523xfec_if_t * fecif )
379 extern void ( *__RAMVEC[] ) ( );
381 int old_ipl = asm_set_ipl( 7 );
383 /* Reset the FEC - equivalent to a hard reset */
384 MCF_FEC_ECR = MCF_FEC_ECR_RESET;
386 /* Wait for the reset sequence to complete */
387 while( MCF_FEC_ECR & MCF_FEC_ECR_RESET );
389 /* Disable all FEC interrupts by clearing the EIMR register */
392 /* Clear any interrupts by setting all bits in the EIR register */
393 MCF_FEC_EIR = 0xFFFFFFFFUL;
395 /* Configure Interrupt vectors. */
396 __RAMVEC[MCF_FEC_VEC_RXF] = mcf523xfec_rx_irq;
398 /* Set the source address for the controller */
400 ( fecif->self->addr[0] << 24U ) | ( fecif->self->addr[1] << 16U ) |
401 ( fecif->self->addr[2] << 8U ) | ( fecif->self->addr[3] << 0U );
402 MCF_FEC_PAUR = ( fecif->self->addr[4] << 24U ) | ( fecif->self->addr[5] << 16U );
404 /* Initialize the hash table registers */
408 /* Set Receive Buffer Size */
409 #if RX_BUFFER_SIZE != 2048
410 #error "RX_BUFFER_SIZE must be set to 2048 for safe FEC operation."
412 MCF_FEC_EMRBR = RX_BUFFER_SIZE - 1;
414 /* Point to the start of the circular Rx buffer descriptor queue */
415 MCF_FEC_ERDSR = nbuf_get_start( NBUF_RX );
417 /* Point to the start of the circular Tx buffer descriptor queue */
418 MCF_FEC_ETDSR = nbuf_get_start( NBUF_TX );
420 /* Set the tranceiver interface to MII mode */
421 MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL( MCF_FEC_MTU ) | MCF_FEC_RCR_MII_MODE;
423 /* Set MII Speed Control Register for 2.5Mhz */
424 MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( FSYS_2 / ( 2UL * 2500000UL ) );
426 /* Only operate in half-duplex, no heart beat control */
429 /* Enable Debug support */
431 FEC_DEBUG_RX_TIMING( 0 );
432 FEC_DEBUG_TX_TIMING( 0 );
433 ( void )asm_set_ipl( old_ipl );
437 mcf523xfec_get_mac( mcf523xfec_if_t * hw, struct eth_addr *mac )
440 static const struct eth_addr mac_default = {
441 {0x00, 0xCF, 0x52, 0x35, 0x00, 0x01}
446 for( i = 0; i < ETH_ADDR_LEN; i++ )
448 mac->addr[i] = mac_default.addr[i];
453 mcf523xfec_enable( mcf523xfec_if_t * fecif )
457 int old_ipl = asm_set_ipl( 7 );
459 /* Configure I/O pins for the FEC. */
460 MCF_GPIO_PAR_FECI2C = ( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );
462 /* Allow interrupts by setting IMR register */
463 MCF_FEC_EIMR = MCF_FEC_EIMR_RXF;
465 /* Configure the interrupt controller. */
466 MCF_INTC0_ICR27 = ( MCF_INTC0_ICRn_IL( MCF_FEC_INT_LEVEL ) |
467 MCF_INTC0_ICRn_IP( MCF_FEC_INT_PRIORITY ) );
468 MCF_INTC0_IMRL &= ~( MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_MASKALL );
471 MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;
473 /* Indicate that there have been empty receive buffers produced */
475 ( void )asm_set_ipl( old_ipl );
479 mcf523xfec_disable( mcf523xfec_if_t * fecif )
483 int old_ipl = asm_set_ipl( 7 );
485 /* Set the Graceful Transmit Stop bit */
486 MCF_FEC_TCR = ( MCF_FEC_TCR | MCF_FEC_TCR_GTS );
488 /* Wait for the current transmission to complete */
489 while( !( MCF_FEC_EIR & MCF_FEC_EIR_GRA ) );
491 /* Clear the GRA event */
492 MCF_FEC_EIR = MCF_FEC_EIR_GRA;
494 /* Disable the FEC */
497 /* Disable all FEC interrupts by clearing the IMR register */
500 /* Unconfigure the interrupt controller. */
501 MCF_INTC0_ICR27 = MCF_INTC0_ICRn_IL( 0 ) | MCF_INTC0_ICRn_IP( 0 );
502 MCF_INTC0_IMRL |= MCF_INTC0_IMRL_INT_MASK27;
504 /* Clear the GTS bit so frames can be tranmitted when restarted */
505 MCF_FEC_TCR = ( MCF_FEC_TCR & ~MCF_FEC_TCR_GTS );
507 /* Disable I/O pins used by the FEC. */
508 MCF_GPIO_PAR_FECI2C &= ~( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC |
509 MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );
510 ( void )asm_set_ipl( old_ipl );
514 mcf523xfec_init( struct netif *netif )
518 mcf523xfec_if_t *fecif = mem_malloc( sizeof( mcf523xfec_if_t ) );
522 /* Global copy used in ISR. */
524 fecif->self = ( struct eth_addr * )&netif->hwaddr[0];
525 fecif->netif = netif;
526 fecif->tx_sem = NULL;
527 fecif->rx_sem = NULL;
529 if( ( fecif->tx_sem = sys_sem_new( 1 ) ) == NULL )
533 else if( ( fecif->rx_sem = sys_sem_new( 0 ) ) == NULL )
537 else if( sys_thread_new( mcf523xfec_rx_task, fecif, TASK_PRIORITY ) == NULL )
543 netif->state = fecif;
544 netif->name[0] = 'C';
545 netif->name[1] = 'F';
546 netif->hwaddr_len = ETH_ADDR_LEN;
547 netif->mtu = MCF_FEC_MTU;
548 netif->flags = NETIF_FLAG_BROADCAST;
549 netif->output = mcf523xfec_output;
550 netif->linkoutput = mcf523xfec_output_raw;
553 mcf523xfec_get_mac( fecif, fecif->self );
554 mcf523xfec_reset( fecif );
555 mcf523xfec_enable( fecif );
558 sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
566 if( fecif->tx_sem != NULL )
568 mem_free( fecif->tx_sem );
570 if( fecif->rx_sem != NULL )
572 mem_free( fecif->rx_sem );