2 FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 See http://www.FreeRTOS.org for documentation, latest information, license
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28 and contact details. Please ensure to read the configuration and relevant
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29 port sections of the online documentation.
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30 ***************************************************************************
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34 * Basic interrupt driven driver for the EMAC peripheral. This driver is not
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35 * reentrant as with uIP the buffers are only ever accessed from a single task.
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37 * The simple buffer management used within uIP allows the EMAC driver to also
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38 * be simplistic. The driver contained within the lwIP demo is more
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46 + Corrected the byte order when writing the MAC address to the MAC.
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47 + Support added for MII interfaces. Previously only RMII was supported.
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51 + The MII interface is now the default.
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52 + Modified the initialisation sequence slightly to allow auto init more
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57 + Also read the EMAC_RSR register in the EMAC ISR as a work around the
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58 the EMAC bug that can reset the RX bit in EMAC_ISR register before the
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62 /* Standard includes. */
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65 /* Scheduler includes. */
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66 #include "FreeRTOS.h"
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73 /* Hardware specific includes. */
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78 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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79 to use an MII interface. */
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80 #define USE_RMII_INTERFACE 0
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82 /* The buffer addresses written into the descriptors must be aligned so the
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83 last few bits are zero. These bits have special meaning for the EMAC
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84 peripheral and cannot be used as part of the address. */
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85 #define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )
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87 /* Bit used within the address stored in the descriptor to mark the last
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88 descriptor in the array. */
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89 #define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )
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91 /* Bit used within the Tx descriptor status to indicate whether the
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92 descriptor is under the control of the EMAC or the software. */
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93 #define emacTX_BUF_USED ( ( unsigned portLONG ) 0x80000000 )
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95 /* A short delay is used to wait for a buffer to become available, should
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96 one not be immediately available when trying to transmit a frame. */
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97 #define emacBUFFER_WAIT_DELAY ( 2 )
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98 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
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100 /* Misc defines. */
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101 #define emacINTERRUPT_LEVEL ( 5 )
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102 #define emacNO_DELAY ( 0 )
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103 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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104 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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105 #define emacRESET_KEY ( ( unsigned portLONG ) 0xA5000000 )
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106 #define emacRESET_LENGTH ( ( unsigned portLONG ) ( 0x01 << 8 ) )
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108 /*-----------------------------------------------------------*/
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111 * Prototype for the EMAC interrupt asm wrapper.
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113 extern void vEMACISREntry( void );
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116 * Prototype for the EMAC interrupt function - called by the asm wrapper.
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118 __arm void vEMACISR( void );
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121 * Initialise both the Tx and Rx descriptors used by the EMAC.
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123 static void prvSetupDescriptors(void);
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126 * Write our MAC address into the EMAC. The MAC address is set as one of the
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129 static void prvSetupMACAddress( void );
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132 * Configure the EMAC and AIC for EMAC interrupts.
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134 static void prvSetupEMACInterrupt( void );
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137 * Some initialisation functions taken from the Atmel EMAC sample code.
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139 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
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140 #if USE_RMII_INTERFACE != 1
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141 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
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143 static portBASE_TYPE xGetLinkSpeed( void );
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144 static portBASE_TYPE prvProbePHY( void );
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146 /*-----------------------------------------------------------*/
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148 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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149 comment above the emacADDRESS_MASK definition. */
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150 #pragma data_alignment=8
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151 static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
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153 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
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154 above the emacADDRESS_MASK definition. */
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155 #pragma data_alignment=8
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156 static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
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158 /* Descriptors used to communicate between the program and the EMAC peripheral.
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159 These descriptors hold the locations and state of the Rx and Tx buffers. */
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160 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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161 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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163 /* The IP and Ethernet addresses are read from the uIP setup. */
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164 const portCHAR cMACAddress[ 6 ] = { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 };
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165 const unsigned char ucIPAddress[ 4 ] = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 };
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167 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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168 static xSemaphoreHandle xSemaphore = NULL;
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170 /*-----------------------------------------------------------*/
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172 xSemaphoreHandle xEMACInit( void )
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174 /* Code supplied by Atmel (modified) --------------------*/
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176 /* disable pull up on RXDV => PHY normal mode (not in test mode),
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177 PHY has internal pull down. */
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178 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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180 #if USE_RMII_INTERFACE != 1
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181 /* PHY has internal pull down : set MII mode. */
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182 AT91C_BASE_PIOB->PIO_PPUDR= 1 << 16;
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185 /* clear PB18 <=> PHY powerdown. */
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186 AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 ) ;
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187 AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, 1 << 18) ;
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189 /* After PHY power up, hardware reset. */
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190 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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191 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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193 /* Wait for hardware reset end. */
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194 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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200 /* EMAC IO init for EMAC-PHY com. Remove EF100 config. */
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201 AT91F_EMAC_CfgPIO();
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203 /* Enable com between EMAC PHY.
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205 Enable management port. */
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206 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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208 /* MDC = MCK/32. */
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209 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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211 /* Wait for PHY auto init end (rather crude delay!). */
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212 vTaskDelay( emacPHY_INIT_DELAY );
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214 /* PHY configuration. */
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215 #if USE_RMII_INTERFACE != 1
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217 unsigned portLONG ulControl;
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219 /* PHY has internal pull down : disable MII isolate. */
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220 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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221 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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222 ulControl &= ~BMCR_ISOLATE;
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223 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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227 /* Disable management port again. */
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228 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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230 #if USE_RMII_INTERFACE != 1
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231 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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232 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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234 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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236 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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239 /* End of code supplied by Atmel ------------------------*/
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241 /* Setup the buffers and descriptors. */
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242 prvSetupDescriptors();
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244 /* Load our MAC address into the EMAC. */
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245 prvSetupMACAddress();
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247 /* Try to connect. */
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248 if( prvProbePHY() )
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250 /* Enable the interrupt! */
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251 prvSetupEMACInterrupt();
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256 /*-----------------------------------------------------------*/
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258 portLONG lEMACSend( void )
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260 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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261 portBASE_TYPE xWaitCycles = 0;
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262 portLONG lReturn = pdPASS;
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263 portCHAR *pcBuffer;
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265 /* Is a buffer available? */
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266 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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268 /* There is no room to write the Tx data to the Tx buffer. Wait a
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269 short while, then try again. */
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271 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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279 vTaskDelay( emacBUFFER_WAIT_DELAY );
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283 /* lReturn will only be pdPASS if a buffer is available. */
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284 if( lReturn == pdPASS )
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286 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
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287 pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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288 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
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290 /* If there is room, also copy in the application data if any. */
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291 if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
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293 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
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297 portENTER_CRITICAL();
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299 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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301 /* Fill out the necessary in the descriptor to get the data sent. */
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302 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
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303 | AT91C_LAST_BUFFER
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304 | AT91C_TRANSMIT_WRAP;
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305 uxTxBufferIndex = 0;
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309 /* Fill out the necessary in the descriptor to get the data sent. */
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310 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
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311 | AT91C_LAST_BUFFER;
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315 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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317 portEXIT_CRITICAL();
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322 /*-----------------------------------------------------------*/
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324 unsigned portLONG ulEMACPoll( void )
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326 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
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327 unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
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328 portCHAR *pcSource;
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330 /* Skip any fragments. */
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331 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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333 /* Mark the buffer as free again. */
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334 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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336 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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338 ulNextRxBuffer = 0;
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342 /* Is there a packet ready? */
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344 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
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346 pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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347 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_LENGTH_FRAME;
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349 if( ulSectionLength == 0 )
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351 /* The frame is longer than the buffer pointed to by this
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352 descriptor so copy the entire buffer to uIP - then move onto
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353 the next descriptor to get the rest of the frame. */
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354 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
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356 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
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357 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
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362 /* This is the last section of the frame. Copy the section to
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364 if( ulSectionLength < UIP_BUFSIZE )
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366 /* The section length holds the length of the entire frame.
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367 ulLengthSoFar holds the length of the frame sections already
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368 copied to uIP, so the length of the final section is
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369 ulSectionLength - ulLengthSoFar; */
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370 if( ulSectionLength > ulLengthSoFar )
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372 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
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376 /* Is this the last buffer for the frame? If not why? */
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377 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
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380 /* Mark the buffer as free again. */
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381 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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383 /* Increment to the next buffer, wrapping if necessary. */
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385 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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387 ulNextRxBuffer = 0;
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391 /* If we obtained data but for some reason did not find the end of the
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392 frame then discard the data as it must contain an error. */
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395 ulSectionLength = 0;
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398 return ulSectionLength;
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400 /*-----------------------------------------------------------*/
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402 static void prvSetupDescriptors(void)
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404 unsigned portBASE_TYPE xIndex;
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405 unsigned portLONG ulAddress;
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407 /* Initialise xRxDescriptors descriptor. */
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408 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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410 /* Calculate the address of the nth buffer within the array. */
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411 ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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413 /* Write the buffer address into the descriptor. The DMA will place
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414 the data at this address when this descriptor is being used. Mask off
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415 the bottom bits of the address as these have special meaning. */
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416 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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419 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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420 to the first buffer. */
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421 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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423 /* Initialise xTxDescriptors. */
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424 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
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426 /* Calculate the address of the nth buffer within the array. */
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427 ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
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429 /* Write the buffer address into the descriptor. The DMA will read
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430 data from here when the descriptor is being used. */
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431 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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432 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
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435 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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436 to the first buffer. */
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437 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
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439 /* Tell the EMAC where to find the descriptors. */
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440 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
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441 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
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443 /* Clear all the bits in the receive status register. */
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444 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
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446 /* Enable the copy of data into the buffers, ignore broadcasts,
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447 and don't copy FCS. */
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448 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
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450 /* Enable Rx and Tx, plus the stats register. */
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451 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
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453 /*-----------------------------------------------------------*/
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455 static void prvSetupMACAddress( void )
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457 /* Must be written SA1L then SA1H. */
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458 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
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459 ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
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460 ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) |
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463 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
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466 /*-----------------------------------------------------------*/
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468 static void prvSetupEMACInterrupt( void )
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470 /* Create the semaphore used to trigger the EMAC task. */
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471 vSemaphoreCreateBinary( xSemaphore );
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474 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
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475 first interrupt occurs. */
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476 xSemaphoreTake( xSemaphore, emacNO_DELAY );
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477 portENTER_CRITICAL();
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479 /* We want to interrupt on Rx events. */
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480 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
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482 /* Enable the interrupts in the AIC. */
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483 AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISREntry );
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484 AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_EMAC );
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486 portEXIT_CRITICAL();
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489 /*-----------------------------------------------------------*/
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491 __arm void vEMACISR( void )
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493 volatile unsigned portLONG ulIntStatus, ulRxStatus;
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494 portBASE_TYPE xSwitchRequired = pdFALSE;
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496 ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
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497 ulRxStatus = AT91C_BASE_EMAC->EMAC_RSR;
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499 if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulRxStatus & AT91C_EMAC_REC ) )
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501 /* A frame has been received, signal the uIP task so it can process
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502 the Rx descriptors. */
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503 xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
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504 AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
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507 /* If a task was woken by either a character being received or a character
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508 being transmitted then we may need to switch to another task. */
\r
509 portEND_SWITCHING_ISR( xSwitchRequired );
\r
511 /* Clear the interrupt. */
\r
512 AT91C_BASE_AIC->AIC_EOICR = 0;
\r
514 /*-----------------------------------------------------------*/
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519 * The following functions are initialisation functions taken from the Atmel
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520 * EMAC sample code.
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523 static portBASE_TYPE prvProbePHY( void )
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525 unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
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526 portBASE_TYPE xReturn = pdPASS;
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528 /* Code supplied by Atmel (reformatted) -----------------*/
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530 /* Enable management port */
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531 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
532 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
534 /* Read the PHY ID. */
\r
535 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
536 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
541 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
542 0001 stands for Rev. A, etc.
\r
544 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
546 /* Did not expect this ID. */
\r
551 ulStatus = xGetLinkSpeed();
\r
553 if( ulStatus != pdPASS )
\r
559 /* Disable management port */
\r
560 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
562 /* End of code supplied by Atmel ------------------------*/
\r
566 /*-----------------------------------------------------------*/
\r
568 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
\r
570 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
572 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
573 | (2 << 16) | (2 << 28)
\r
574 | ((ucPHYAddress & 0x1f) << 23)
\r
575 | (ucAddress << 18);
\r
577 /* Wait until IDLE bit in Network Status register is cleared. */
\r
578 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
583 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
585 /* End of code supplied by Atmel ------------------------*/
\r
587 /*-----------------------------------------------------------*/
\r
589 #if USE_RMII_INTERFACE != 1
\r
590 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
\r
592 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
594 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
595 | (2 << 16) | (1 << 28)
\r
596 | ((ucPHYAddress & 0x1f) << 23)
\r
597 | (ucAddress << 18))
\r
598 | (ulValue & 0xffff);
\r
600 /* Wait until IDLE bit in Network Status register is cleared */
\r
601 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
606 /* End of code supplied by Atmel ------------------------*/
\r
609 /*-----------------------------------------------------------*/
\r
611 static portBASE_TYPE xGetLinkSpeed( void )
\r
613 unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
615 /* Code supplied by Atmel (reformatted) -----------------*/
\r
617 /* Link status is latched, so read twice to get current value */
\r
618 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
619 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
621 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
627 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
628 if (ulBMCR & BMCR_ANENABLE)
\r
630 /* AutoNegotiation is enabled. */
\r
631 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
633 /* Auto-negotiation in progress. */
\r
637 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
638 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
640 ulSpeed = SPEED_100;
\r
644 ulSpeed = SPEED_10;
\r
647 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
649 ulDuplex = DUPLEX_FULL;
\r
653 ulDuplex = DUPLEX_HALF;
\r
658 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
659 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
662 /* Update the MAC */
\r
663 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
664 if( ulSpeed == SPEED_100 )
\r
666 if( ulDuplex == DUPLEX_FULL )
\r
668 /* 100 Full Duplex */
\r
669 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
673 /* 100 Half Duplex */
\r
674 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
679 if (ulDuplex == DUPLEX_FULL)
\r
681 /* 10 Full Duplex */
\r
682 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
686 /* 10 Half Duplex */
\r
687 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
691 /* End of code supplied by Atmel ------------------------*/
\r